[coreboot-gerrit] Patch set updated for coreboot: cpu/amd/family_10h-family_15h: Fix incorrect revision detection

[Timothy Pearson]

Timothy Pearson ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12026

-gerrit

commit b11f6b902764a761f9aa67067194e374bee47527
Author: Timothy Pearson 
Date:   Sun Aug 2 21:31:48 2015 -0500

cpu/amd/family_10h-family_15h: Fix incorrect revision detection

Change-Id: I7a881a94d62ed455415f9dfc887fd698ac919429
    Signed-off-by: Timothy Pearson 
---
 src/cpu/amd/family_10h-family_15h/fidvid.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/src/cpu/amd/family_10h-family_15h/fidvid.c b/src/cpu/amd/family_10h-family_15h/fidvid.c
index 8a006cb..66bb3a2 100644
--- a/src/cpu/amd/family_10h-family_15h/fidvid.c
+++ b/src/cpu/amd/family_10h-family_15h/fidvid.c
@@ -371,7 +371,7 @@ static void recalculateVsSlamTimeSettingOnCorePre(device_t dev)
    pci_write_config32(dev, 0xd8, dtemp);
 }

-static u32 nb_clk_did(int node, u32 cpuRev,u8 procPkg) {
+static u32 nb_clk_did(int node, uint64_t cpuRev, uint8_t procPkg) {
         u8 link0isGen3 = 0;
         u8 offset;
         if (AMD_CpuFindCapability(node, 0, &offset)) {
@@ -442,7 +442,7 @@ static u32 power_up_down(int node, u8 procPkg) {
         return dword;
 }

-static void config_clk_power_ctrl_reg0(int node, u32 cpuRev, u8 procPkg) {
+static void config_clk_power_ctrl_reg0(int node, uint64_t cpuRev, uint8_t procPkg) {
        	device_t dev = NODE_PCI(node, 3);

/* Program fields in Clock Power/Control register0 (F3xD4) */
@@ -467,7 +467,7 @@ static void config_clk_power_ctrl_reg0(int node, u32 cpuRev, u8 procPkg) {

}

-static void config_power_ctrl_misc_reg(device_t dev,u32 cpuRev, u8 procPkg) {
+static void config_power_ctrl_misc_reg(device_t dev, uint64_t cpuRev, uint8_t procPkg) {
    /* check PVI/SVI */
    u32 dword = pci_read_config32(dev, 0xa0);

@@ -500,7 +500,7 @@ static void config_power_ctrl_misc_reg(device_t dev,u32 cpuRev, u8 procPkg) {
    pci_write_config32(dev, 0xa0, dword);
 }

-static void config_nb_syn_ptr_adj(device_t dev, u32 cpuRev) {
+static void config_nb_syn_ptr_adj(device_t dev, uint64_t cpuRev) {
    /* Note the following settings are additional from the ported
     * function setFidVidRegs()
     */
@@ -522,7 +522,7 @@ static void config_nb_syn_ptr_adj(device_t dev, u32 cpuRev) {
    pci_write_config32(dev, 0xdc, dword);
 }

-static void config_acpi_pwr_state_ctrl_regs(device_t dev, u32 cpuRev, u8 procPkg) {
+static void config_acpi_pwr_state_ctrl_regs(device_t dev, uint64_t cpuRev, uint8_t procPkg) {
    if (is_fam15h()) {
    	/* Family 15h BKDG Rev. 3.14 D18F3x80 recommended settings */
    	pci_write_config32(dev, 0x80, 0xe20be281);