[coreboot-gerrit] Change in coreboot[master]: sc7280: enable bl31

[Ravi kumar (Code Review)]

Ravi kumar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47904 )

Change subject: sc7280: enable bl31
......................................................................

sc7280: enable bl31

Developer/Reviewer, be aware of this patch from Napali:
https://review.coreboot.org/c/coreboot/+/28014/44

Signed-off-by: Ravi Kumar Bokka 
Change-Id: I61c695fb4fef3ae36ffc5a263236b9d40c299dc4
---
M src/soc/qualcomm/sc7280/Kconfig
M src/soc/qualcomm/sc7280/memlayout.ld
2 files changed, 2 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/47904/1

diff --git a/src/soc/qualcomm/sc7280/Kconfig b/src/soc/qualcomm/sc7280/Kconfig
index d6f56ba..6882457 100644
--- a/src/soc/qualcomm/sc7280/Kconfig
+++ b/src/soc/qualcomm/sc7280/Kconfig
@@ -6,6 +6,7 @@
    select ARCH_RAMSTAGE_ARMV8_64
    select ARCH_ROMSTAGE_ARMV8_64
    select ARCH_VERSTAGE_ARMV8_64
+	select ARM64_USE_ARM_TRUSTED_FIRMWARE
    select GENERIC_GPIO_LIB
    select GENERIC_UDELAY
    select HAVE_MONOTONIC_TIMER
diff --git a/src/soc/qualcomm/sc7280/memlayout.ld b/src/soc/qualcomm/sc7280/memlayout.ld
index a3a785e..fed3a72 100644
--- a/src/soc/qualcomm/sc7280/memlayout.ld
+++ b/src/soc/qualcomm/sc7280/memlayout.ld
@@ -50,7 +50,7 @@
    /* Various hardware/software subsystems make use of this area */
    REGION(dram_aop,  0x80800000, 0x040000, 0x1000)
    REGION(dram_soc,  0x80900000, 0x200000, 0x1000)
-	BL31(0x80B00000, 1M)
    POSTRAM_CBFS_CACHE(0x9F800000, 16M)
    RAMSTAGE(0xA0800000, 16M)
+	BL31(0xC0000000, 1M)
 }