Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36137 )
Change subject: soc/intel: skl,cnl,icl: consolidate ebda and memmap and move to common code ......................................................................
Patch Set 19:
(6 comments)
https://review.coreboot.org/c/coreboot/+/36137/19/src/soc/intel/common/block... File src/soc/intel/common/block/memmap/memmap.c:
https://review.coreboot.org/c/coreboot/+/36137/19/src/soc/intel/common/block... PS19, Line 40: also maps into MC address space
Does anybody know what this means?
nope :/
https://review.coreboot.org/c/coreboot/+/36137/19/src/soc/intel/common/block... PS19, Line 54: * +---------------------------+ TOLUM / top_of_ram (aligned)
This is the same as cbmem_top
Done
https://review.coreboot.org/c/coreboot/+/36137/19/src/soc/intel/common/block... PS19, Line 54: aligned
Aligned to what?
I have no idea, copied from the original one
https://review.coreboot.org/c/coreboot/+/36137/19/src/soc/intel/common/block... PS19, Line 56: * +---------------------------+ cbmem_top
Not cbmem_top, as CBMEM root is part of CBMEM
Done
https://review.coreboot.org/c/coreboot/+/36137/19/src/soc/intel/common/block... PS19, Line 62: FSP TOLUM
FSP makes no sense here. If anything, the above TOLUM would be the FSP one.
According to Skylake FSP IG this is FSP TOLUM
https://review.coreboot.org/c/coreboot/+/36137/19/src/soc/intel/common/block... PS19, Line 66: * Some of the base registers above can be equal making the size of those : * regions 0. The reason is because the memory controller internally subtracts : * the base registers from each other to determine sizes of the regions. In : * other words, the memory map is in a fixed order no matter what.
This confuses me. […]
IMHO no, I removed that