David Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/57438 )
Change subject: mb/google/brya/variants/kano: Update GPIOs config for kano ......................................................................
mb/google/brya/variants/kano: Update GPIOs config for kano
Based on latest schematic to update GPIOs config.
BUG=b:192370253 BRANCH=None TEST=FW_NAME=kano emerge-brya coreboot
Signed-off-by: David Wu david_wu@quanta.corp-partner.google.com Change-Id: I96be95a127f42b005d97a3c02650af13419524a3 --- M src/mainboard/google/brya/variants/kano/fw_config.c M src/mainboard/google/brya/variants/kano/gpio.c 2 files changed, 36 insertions(+), 24 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/57438/1
diff --git a/src/mainboard/google/brya/variants/kano/fw_config.c b/src/mainboard/google/brya/variants/kano/fw_config.c index ade89da..5163803 100644 --- a/src/mainboard/google/brya/variants/kano/fw_config.c +++ b/src/mainboard/google/brya/variants/kano/fw_config.c @@ -6,17 +6,17 @@ #include <gpio.h>
static const struct pad_config dmic_enable_pads[] = { - PAD_CFG_NF(GPP_S2, NONE, DEEP, NF2), /* DMIC_CLK0_R */ - PAD_CFG_NF(GPP_S3, NONE, DEEP, NF2), /* DMIC_DATA0_R */ - PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2), /* DMIC_CLK1_R */ - PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2), /* DMIC_DATA1_R */ + PAD_CFG_NF(GPP_R4, NONE, DEEP, NF3), /* DMIC_CLK0_R */ + PAD_CFG_NF(GPP_R5, NONE, DEEP, NF3), /* DMIC_DATA0_R */ + PAD_CFG_NF(GPP_R6, NONE, DEEP, NF3), /* DMIC_CLK1_R */ + PAD_CFG_NF(GPP_R7, NONE, DEEP, NF3), /* DMIC_DATA1_R */ };
static const struct pad_config dmic_disable_pads[] = { - PAD_NC(GPP_S2, NONE), - PAD_NC(GPP_S3, NONE), - PAD_NC(GPP_S6, NONE), - PAD_NC(GPP_S7, NONE), + PAD_NC(GPP_R4, NONE), + PAD_NC(GPP_R5, NONE), + PAD_NC(GPP_R6, NONE), + PAD_NC(GPP_R7, NONE), };
static const struct pad_config i2s_enable_pads[] = { @@ -24,10 +24,10 @@ PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), /* I2S_HP_SFRM_R */ PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2), /* I2S_PCH_TX_HP_RX_STRAP */ PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), /* I2S_PCH_RX_HP_TX */ - PAD_CFG_NF(GPP_R4, NONE, DEEP, NF2), /* I2S_SPKR_SCLK_R */ - PAD_CFG_NF(GPP_R5, NONE, DEEP, NF2), /* I2S_SPKR_SFRM_R */ - PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2), /* I2S_PCH_TX_SPKR_RX_R */ - PAD_CFG_NF(GPP_R7, NONE, DEEP, NF2), /* I2S_PCH_RX_SPKR_TX */ + PAD_CFG_NF(GPP_S0, NONE, DEEP, NF2), /* I2S_SPKR_SCLK_R */ + PAD_CFG_NF(GPP_S1, NONE, DEEP, NF2), /* I2S_SPKR_SFRM_R */ + PAD_CFG_NF(GPP_S2, NONE, DEEP, NF3), /* I2S_PCH_TX_SPKR_RX_R */ + PAD_CFG_NF(GPP_S3, NONE, DEEP, NF3), /* I2S_PCH_RX_SPKR_TX */ };
static const struct pad_config i2s_disable_pads[] = { @@ -35,10 +35,10 @@ PAD_NC(GPP_R1, NONE), PAD_NC(GPP_R2, NONE), PAD_NC(GPP_R3, NONE), - PAD_NC(GPP_R4, NONE), - PAD_NC(GPP_R5, NONE), - PAD_NC(GPP_R6, NONE), - PAD_NC(GPP_R7, NONE), + PAD_NC(GPP_S0, NONE), + PAD_NC(GPP_S1, NONE), + PAD_NC(GPP_S2, NONE), + PAD_NC(GPP_S3, NONE), };
static void fw_config_handle(void *unused) diff --git a/src/mainboard/google/brya/variants/kano/gpio.c b/src/mainboard/google/brya/variants/kano/gpio.c index cc6a870..8d21c88 100644 --- a/src/mainboard/google/brya/variants/kano/gpio.c +++ b/src/mainboard/google/brya/variants/kano/gpio.c @@ -29,14 +29,12 @@
/* D3 : ISH_GP3 ==> NC */ PAD_NC(GPP_D3, NONE), - /* D5 : SRCCLKREQ0# ==> NC */ - PAD_NC(GPP_D5, NONE), + /* D5 : SRCCLKREQ0# ==> SSD_CLKREQ_ODL */ + PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), /* D7 : SRCCLKREQ2# ==> NC */ PAD_NC(GPP_D7, NONE), /* D8 : SRCCLKREQ3# ==> NC */ PAD_NC(GPP_D8, NONE), - /* D9 : ISH_SPI_CS# ==> NC */ - PAD_NC(GPP_D9, NONE), /* D18 : UART1_TXD ==> NC */ PAD_NC(GPP_D18, NONE),
@@ -57,8 +55,6 @@
/* F6 : CNV_PA_BLANKING ==> NC */ PAD_NC(GPP_F6, NONE), - /* F20 : EXT_PWR_GATE# ==> NC */ - PAD_NC(GPP_F20, NONE), /* F21 : EXT_PWR_GATE2# ==> NC */ PAD_NC(GPP_F21, NONE),
@@ -70,8 +66,6 @@ PAD_NC(GPP_H12, NONE), /* H13 : I2C7_SCL ==> NC */ PAD_NC(GPP_H13, NONE), - /* H15 : DDPB_CTRLCLK ==> NC */ - PAD_NC(GPP_H15, NONE), /* H19 : SRCCLKREQ4# ==> NC */ PAD_NC(GPP_H19, NONE), /* H20 : IMGCLKOUT1 ==> NC */ @@ -83,6 +77,24 @@ /* H23 : SRCCLKREQ5# ==> NC */ PAD_NC(GPP_H23, NONE),
+ /* R4 : HDA_RST# ==> DMIC_CLK0_R */ + PAD_CFG_NF(GPP_R4, NONE, DEEP, NF3), + /* R5 : HDA_SDI1 ==> DMIC_DATA0_R */ + PAD_CFG_NF(GPP_R5, NONE, DEEP, NF3), + /* R6 : I2S2_TXD ==> DMIC_CLK1_R */ + PAD_CFG_NF(GPP_R6, NONE, DEEP, NF3), + /* R7 : I2S2_RXD ==> DMIC_DATA1_R */ + PAD_CFG_NF(GPP_R7, NONE, DEEP, NF3), + + /* S0 : SNDW0_CLK ==> I2S1_SPKR_SCLK_R */ + PAD_CFG_NF(GPP_S0, NONE, DEEP, NF2), + /* S1 : SNDW0_DATA ==> I2S1_SPKR_SFRM_R */ + PAD_CFG_NF(GPP_S1, NONE, DEEP, NF2), + /* S2 : SNDW1_CLK ==> I2S1_PCH_TX_SPKR_RX_R */ + PAD_CFG_NF(GPP_S2, NONE, DEEP, NF3), + /* S3 : SNDW1_DATA ==> I2S1_PCH_RX_SPKR_TX */ + PAD_CFG_NF(GPP_S3, NONE, DEEP, NF3), + /* GPD11: LANPHYC ==> NC */ PAD_NC(GPD11, NONE), };