Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/31036 )
Change subject: nb/intel/i945: Remove 2nd write on SLOTCAP (R/WO) ......................................................................
nb/intel/i945: Remove 2nd write on SLOTCAP (R/WO)
SLOTCAP is R/WO, it becomes RO after the first write. Write already done on line #583.
Tested using kprint before and after on 945G-M4 board.
Change-Id: I27579bc634e357490defabb041457aaa010fb1c8 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr Reviewed-on: https://review.coreboot.org/c/coreboot/+/31036 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Patrick Georgi pgeorgi@google.com --- M src/northbridge/intel/i945/early_init.c 1 file changed, 0 insertions(+), 5 deletions(-)
Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved
diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index 7ab2525..e8cacf6 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -552,8 +552,6 @@ u32 reg32; u16 reg16;
- u8 reg8; - printk(BIOS_DEBUG, "Enabling PCI Express x16 Link\n");
reg16 = pci_read_config16(PCI_DEV(0, 0x00, 0), DEVEN); @@ -733,9 +731,6 @@ reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x328); pci_write_config32(PCI_DEV(0, 0x01, 0), 0x328, reg32);
- reg8 = pci_read_config8(PCI_DEV(0, 0x01, 0), SLOTCAP); - pci_write_config8(PCI_DEV(0, 0x01, 0), SLOTCAP, reg8); - /* Additional PCIe graphics setup */ reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0xf0); reg32 |= (3 << 26);