Attention is currently required from: Jérémy Compostella.
Martin L Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80012?usp=email )
Change subject: arch/x86: Reformat C files with clang-format v16 ......................................................................
arch/x86: Reformat C files with clang-format v16
Reformat only - No functional changes.
Change-Id: Ibbc17201e6e964083259d0e48bfab8f4c857e677 Signed-off-by: Martin Roth gaumless@gmail.com --- M src/arch/x86/acpi.c M src/arch/x86/acpi_bert_storage.c M src/arch/x86/boot.c M src/arch/x86/breakpoint.c M src/arch/x86/cpu.c M src/arch/x86/cpu_common.c M src/arch/x86/ebda.c M src/arch/x86/exception.c M src/arch/x86/ioapic.c M src/arch/x86/memcpy.c M src/arch/x86/memmove_32.c M src/arch/x86/memset.c M src/arch/x86/mmap_boot.c M src/arch/x86/mpspec.c M src/arch/x86/null_breakpoint.c M src/arch/x86/pirq_routing.c M src/arch/x86/postcar.c M src/arch/x86/postcar_loader.c M src/arch/x86/rdrand.c M src/arch/x86/smbios.c M src/arch/x86/tables.c M src/arch/x86/thread.c 22 files changed, 581 insertions(+), 712 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/80012/1
diff --git a/src/arch/x86/acpi.c b/src/arch/x86/acpi.c index 2497143..67ebba1 100644 --- a/src/arch/x86/acpi.c +++ b/src/arch/x86/acpi.c @@ -20,7 +20,6 @@ return irq; }
- void arch_fill_fadt(acpi_fadt_t *fadt) { fadt->sci_int = acpi_sci_int(); diff --git a/src/arch/x86/acpi_bert_storage.c b/src/arch/x86/acpi_bert_storage.c index 62c0441..edcbd44 100644 --- a/src/arch/x86/acpi_bert_storage.c +++ b/src/arch/x86/acpi_bert_storage.c @@ -73,8 +73,7 @@ */
/* Find the nth (1-based) Generic Data Structure attached to an Error Status */ -static void *acpi_hest_generic_data_nth( - acpi_generic_error_status_t *status, int num) +static void *acpi_hest_generic_data_nth(acpi_generic_error_status_t *status, int num) { acpi_hest_generic_data_v300_t *ptr; size_t struct_size; @@ -88,10 +87,8 @@ struct_size = sizeof(acpi_hest_generic_data_v300_t); else struct_size = sizeof(acpi_hest_generic_data_t); - ptr = (acpi_hest_generic_data_v300_t *)( - (u8 *)ptr - + ptr->data_length - + struct_size); + ptr = (acpi_hest_generic_data_v300_t *)((u8 *)ptr + ptr->data_length + + struct_size); } return ptr; } @@ -154,8 +151,8 @@ * should update the error severity, and may optionally add FRU information * or override any existing information. */ -static acpi_hest_generic_data_v300_t *new_generic_error_entry( - acpi_generic_error_status_t *status) +static acpi_hest_generic_data_v300_t * +new_generic_error_entry(acpi_generic_error_status_t *status) { acpi_hest_generic_data_v300_t *entry;
@@ -201,7 +198,7 @@ void *cl_data = bert_allocate_storage(cl_size); if (!cl_data) { printk(BIOS_ERR, "Crashlog entry (size %zu) would exceed available region\n", - cl_size); + cl_size); return NULL; }
@@ -239,8 +236,8 @@ * the setting the status and entry severity, as well as populating all fields * of the error section. */ -acpi_hest_generic_data_v300_t *bert_append_error_datasection( - acpi_generic_error_status_t *status, guid_t *guid) +acpi_hest_generic_data_v300_t * +bert_append_error_datasection(acpi_generic_error_status_t *status, guid_t *guid) { acpi_hest_generic_data_v300_t *entry; void *sect; @@ -272,14 +269,12 @@ * Generic Error Section. As many fields are populated as possible for the * caller. */ -acpi_hest_generic_data_v300_t *bert_append_genproc( - acpi_generic_error_status_t *status) +acpi_hest_generic_data_v300_t *bert_append_genproc(acpi_generic_error_status_t *status) { acpi_hest_generic_data_v300_t *entry; cper_proc_generic_error_section_t *ges;
- entry = bert_append_error_datasection(status, - &CPER_SEC_PROC_GENERIC_GUID); + entry = bert_append_error_datasection(status, &CPER_SEC_PROC_GENERIC_GUID); if (!entry) return NULL;
@@ -328,29 +323,24 @@ * * status and entry data_length values are updated. */ -cper_ia32x64_context_t *new_cper_ia32x64_ctx( - acpi_generic_error_status_t *status, - cper_ia32x64_proc_error_section_t *x86err, int type, int num) +cper_ia32x64_context_t *new_cper_ia32x64_ctx(acpi_generic_error_status_t *status, + cper_ia32x64_proc_error_section_t *x86err, + int type, int num) { size_t size; cper_ia32x64_context_t *ctx; - static const char * const ctx_names[] = { - "Unclassified Data", - "MSR Registers", - "32-bit Mode Execution", - "64-bit Mode Execution", - "FXSAVE", - "32-bit Mode Debug", - "64-bit Mode Debug", - "Memory Mapped" - }; + static const char *const ctx_names[] = { + "Unclassified Data", "MSR Registers", "32-bit Mode Execution", + "64-bit Mode Execution", "FXSAVE", "32-bit Mode Debug", + "64-bit Mode Debug", "Memory Mapped"};
if (type > CPER_IA32X64_CTX_MEMMAPPED) return NULL;
if (cper_ia32x64_proc_num_ctxs(x86err) == I32X64SEC_VALID_CTXNUM_MAX) { - printk(BIOS_ERR, "New IA32X64 %s context entry would exceed max allowable contexts\n", - ctx_names[type]); + printk(BIOS_ERR, + "New IA32X64 %s context entry would exceed max allowable contexts\n", + ctx_names[type]); return NULL; }
@@ -358,7 +348,7 @@ ctx = bert_allocate_storage(size); if (!ctx) { printk(BIOS_ERR, "New IA32X64 %s context entry would exceed available region\n", - ctx_names[type]); + ctx_names[type]); return NULL; }
@@ -380,38 +370,31 @@ * or step through the errors. The type is filled and PROC_ERR_INFO_NUM is * updated. */ -cper_ia32x64_proc_error_info_t *new_cper_ia32x64_check( - acpi_generic_error_status_t *status, - cper_ia32x64_proc_error_section_t *x86err, - enum cper_x86_check_type type) +cper_ia32x64_proc_error_info_t * +new_cper_ia32x64_check(acpi_generic_error_status_t *status, + cper_ia32x64_proc_error_section_t *x86err, enum cper_x86_check_type type) { cper_ia32x64_proc_error_info_t *check; - static const char * const check_names[] = { - "cache", - "TLB", - "bus", - "MS" - }; - const guid_t check_guids[] = { - X86_PROCESSOR_CACHE_CHK_ERROR_GUID, - X86_PROCESSOR_TLB_CHK_ERROR_GUID, - X86_PROCESSOR_BUS_CHK_ERROR_GUID, - X86_PROCESSOR_MS_CHK_ERROR_GUID - }; + static const char *const check_names[] = {"cache", "TLB", "bus", "MS"}; + const guid_t check_guids[] = {X86_PROCESSOR_CACHE_CHK_ERROR_GUID, + X86_PROCESSOR_TLB_CHK_ERROR_GUID, + X86_PROCESSOR_BUS_CHK_ERROR_GUID, + X86_PROCESSOR_MS_CHK_ERROR_GUID};
if (type > X86_PROCESSOR_CHK_MAX) return NULL;
if (cper_ia32x64_proc_num_chks(x86err) == I32X64SEC_VALID_ERRNUM_MAX) { - printk(BIOS_ERR, "New IA32X64 %s check entry would exceed max allowable errors\n", - check_names[type]); + printk(BIOS_ERR, + "New IA32X64 %s check entry would exceed max allowable errors\n", + check_names[type]); return NULL; }
check = bert_allocate_storage(sizeof(*check)); if (!check) { printk(BIOS_ERR, "New IA32X64 %s check entry would exceed available region\n", - check_names[type]); + check_names[type]); return NULL; }
@@ -427,15 +410,13 @@ * Processor Error Section. As many fields are populated as possible for the * caller. */ -acpi_hest_generic_data_v300_t *bert_append_ia32x64( - acpi_generic_error_status_t *status) +acpi_hest_generic_data_v300_t *bert_append_ia32x64(acpi_generic_error_status_t *status) { acpi_hest_generic_data_v300_t *entry; cper_ia32x64_proc_error_section_t *ipe; struct cpuid_result id;
- entry = bert_append_error_datasection(status, - &CPER_SEC_PROC_IA32X64_GUID); + entry = bert_append_error_datasection(status, &CPER_SEC_PROC_IA32X64_GUID); if (!entry) return NULL;
@@ -459,21 +440,12 @@ return entry; }
-static const char * const generic_error_types[] = { - "PROCESSOR_GENERIC", - "PROCESSOR_SPECIFIC_X86", - "PROCESSOR_SPECIFIC_ARM", - "PLATFORM_MEMORY", - "PLATFORM_MEMORY2", - "PCIE", - "FW_ERROR_RECORD", - "PCI_PCIX_BUS", - "PCI_DEVICE", - "DMAR_GENERIC", - "DIRECTED_IO_DMAR", - "IOMMU_DMAR", - "UNRECOGNIZED" -}; +static const char *const generic_error_types[] = { + "PROCESSOR_GENERIC", "PROCESSOR_SPECIFIC_X86", "PROCESSOR_SPECIFIC_ARM", + "PLATFORM_MEMORY", "PLATFORM_MEMORY2", "PCIE", + "FW_ERROR_RECORD", "PCI_PCIX_BUS", "PCI_DEVICE", + "DMAR_GENERIC", "DIRECTED_IO_DMAR", "IOMMU_DMAR", + "UNRECOGNIZED"};
static const char *generic_error_name(guid_t *guid) { @@ -520,7 +492,7 @@
if (size > bert_storage_remaining()) { printk(BIOS_ERR, "Not enough BERT region space to add event for type %s\n", - generic_error_name(guid)); + generic_error_name(guid)); return NULL; }
@@ -544,9 +516,9 @@ }
/* Helper to add an MSR context to an existing IA32/X64-type error entry */ -cper_ia32x64_context_t *cper_new_ia32x64_context_msr( - acpi_generic_error_status_t *status, - cper_ia32x64_proc_error_section_t *x86err, u32 addr, int num) +cper_ia32x64_context_t *cper_new_ia32x64_context_msr(acpi_generic_error_status_t *status, + cper_ia32x64_proc_error_section_t *x86err, + u32 addr, int num) { cper_ia32x64_context_t *ctx; int i; @@ -562,7 +534,7 @@
dest = (msr_t *)((u8 *)(ctx + 1)); /* point to the Register Array */
- for (i = 0 ; i < num ; i++) + for (i = 0; i < num; i++) *(dest + i) = rdmsr(addr + i); return ctx; } diff --git a/src/arch/x86/boot.c b/src/arch/x86/boot.c index c50ec0e..1fe1a3b 100644 --- a/src/arch/x86/boot.c +++ b/src/arch/x86/boot.c @@ -13,7 +13,7 @@ { if (start < 1 * MiB && (start + size) <= 1 * MiB) { printk(BIOS_DEBUG, - "Payload being loaded at below 1MiB without region being marked as RAM usable.\n"); + "Payload being loaded at below 1MiB without region being marked as RAM usable.\n"); return 1; }
diff --git a/src/arch/x86/breakpoint.c b/src/arch/x86/breakpoint.c index d3ba783..2d7d7db 100644 --- a/src/arch/x86/breakpoint.c +++ b/src/arch/x86/breakpoint.c @@ -7,19 +7,19 @@ #define DEBUG_REGISTER_COUNT 4
/* Each enable field is 2 bits and starts at bit 0 */ -#define DEBUG_CTRL_ENABLE_SHIFT(index) (2 * (index)) -#define DEBUG_CTRL_ENABLE_MASK(index) (0x3 << DEBUG_CTRL_ENABLE_SHIFT(index)) +#define DEBUG_CTRL_ENABLE_SHIFT(index) (2 * (index)) +#define DEBUG_CTRL_ENABLE_MASK(index) (0x3 << DEBUG_CTRL_ENABLE_SHIFT(index)) #define DEBUG_CTRL_ENABLE(index, enable) ((enable) << DEBUG_CTRL_ENABLE_SHIFT(index))
/* Each breakpoint has a length and type, each is two bits and start at bit 16 */ -#define DEBUG_CTRL_LT_SHIFT(index) (4 * (index) + 16) -#define DEBUG_CTRL_LT_MASK(index) (0xf << DEBUG_CTRL_LT_SHIFT(index)) +#define DEBUG_CTRL_LT_SHIFT(index) (4 * (index) + 16) +#define DEBUG_CTRL_LT_MASK(index) (0xf << DEBUG_CTRL_LT_SHIFT(index)) #define DEBUG_CTRL_LT(index, len, type) ((((len) << 2 | (type))) << DEBUG_CTRL_LT_SHIFT(index))
/* Each field is one bit, starting at bit 0 */ #define DEBUG_STATUS_BP_HIT_MASK(index) (1 << (index)) #define DEBUG_STATUS_GET_BP_HIT(index, value) \ - (((value) & DEBUG_STATUS_BP_HIT_MASK(index)) >> (index)) + (((value)&DEBUG_STATUS_BP_HIT_MASK(index)) >> (index))
/* Breakpoint lengths values */ #define DEBUG_CTRL_LEN_1 0x0 @@ -28,7 +28,7 @@ #define DEBUG_CTRL_LEN_4 0x3
/* Breakpoint enable values */ -#define DEBUG_CTRL_ENABLE_LOCAL 0x1 +#define DEBUG_CTRL_ENABLE_LOCAL 0x1 #define DEBUG_CTRL_ENABLE_GLOBAL 0x2
/* eflags/rflags bit to continue execution after hitting an instruction breakpoint */ @@ -170,8 +170,8 @@ return BREAKPOINT_RES_INVALID_LENGTH; }
- enum breakpoint_type type = - write_only ? BREAKPOINT_TYPE_DATA_WRITE : BREAKPOINT_TYPE_DATA_RW; + enum breakpoint_type type = write_only ? BREAKPOINT_TYPE_DATA_WRITE : + BREAKPOINT_TYPE_DATA_RW; enum breakpoint_result res = allocate_breakpoint(out_handle, type); if (res != BREAKPOINT_RES_OK) return res; @@ -258,7 +258,7 @@ bool instr_bp_hit = 0;
for (int i = 0; i < DEBUG_REGISTER_COUNT; i++) { - struct breakpoint_handle handle = { i }; + struct breakpoint_handle handle = {i}; bool hit = false; enum breakpoint_type type;
diff --git a/src/arch/x86/cpu.c b/src/arch/x86/cpu.c index f4c18c2..9fe2376 100644 --- a/src/arch/x86/cpu.c +++ b/src/arch/x86/cpu.c @@ -20,20 +20,19 @@ { uint32_t f1, f2;
- asm( - "pushfl\n\t" - "pushfl\n\t" - "popl %0\n\t" - "movl %0,%1\n\t" - "xorl %2,%0\n\t" - "pushl %0\n\t" - "popfl\n\t" - "pushfl\n\t" - "popl %0\n\t" - "popfl\n\t" - : "=&r" (f1), "=&r" (f2) - : "ir" (flag)); - return ((f1^f2) & flag) != 0; + asm("pushfl\n\t" + "pushfl\n\t" + "popl %0\n\t" + "movl %0,%1\n\t" + "xorl %2,%0\n\t" + "pushl %0\n\t" + "popfl\n\t" + "pushfl\n\t" + "popl %0\n\t" + "popfl\n\t" + : "=&r"(f1), "=&r"(f2) + : "ir"(flag)); + return ((f1 ^ f2) & flag) != 0; }
/* @@ -50,13 +49,12 @@ { unsigned int test;
- __asm__ __volatile__( - "sahf\n\t" /* clear flags (%eax = 0x0005) */ - "div %b2\n\t" /* divide 5 by 2 */ - "lahf" /* store flags into %ah */ - : "=a" (test) - : "0" (5), "q" (2) - : "cc"); + __asm__ __volatile__("sahf\n\t" /* clear flags (%eax = 0x0005) */ + "div %b2\n\t" /* divide 5 by 2 */ + "lahf" /* store flags into %ah */ + : "=a"(test) + : "0"(5), "q"(2) + : "cc");
/* AH is 0x02 on Cyrix after the divide.. */ return (unsigned char)(test >> 8) == 0x02; @@ -71,17 +69,18 @@ { int ret;
- __asm__ __volatile__ ( - " movw $0x5555, %%ax\n" - " xorw %%dx,%%dx\n" - " movw $2, %%cx\n" - " divw %%cx\n" - " movl $0, %%eax\n" - " jnz 1f\n" - " movl $1, %%eax\n" - "1:\n" - : "=a" (ret) : : "cx", "dx"); - return ret; + __asm__ __volatile__(" movw $0x5555, %%ax\n" + " xorw %%dx,%%dx\n" + " movw $2, %%cx\n" + " divw %%cx\n" + " movl $0, %%eax\n" + " jnz 1f\n" + " movl $1, %%eax\n" + "1:\n" + : "=a"(ret) + : + : "cx", "dx"); + return ret; } #endif
@@ -92,40 +91,34 @@ int vendor; const char *name; } x86_vendors[] = { - { X86_VENDOR_INTEL, "GenuineIntel", }, - { X86_VENDOR_CYRIX, "CyrixInstead", }, - { X86_VENDOR_AMD, "AuthenticAMD", }, - { X86_VENDOR_UMC, "UMC UMC UMC ", }, - { X86_VENDOR_NEXGEN, "NexGenDriven", }, - { X86_VENDOR_CENTAUR, "CentaurHauls", }, - { X86_VENDOR_RISE, "RiseRiseRise", }, - { X86_VENDOR_TRANSMETA, "GenuineTMx86", }, - { X86_VENDOR_TRANSMETA, "TransmetaCPU", }, - { X86_VENDOR_NSC, "Geode by NSC", }, - { X86_VENDOR_SIS, "SiS SiS SiS ", }, - { X86_VENDOR_HYGON, "HygonGenuine", }, + {X86_VENDOR_INTEL, "GenuineIntel"}, + {X86_VENDOR_CYRIX, "CyrixInstead"}, + {X86_VENDOR_AMD, "AuthenticAMD"}, + {X86_VENDOR_UMC, "UMC UMC UMC "}, + {X86_VENDOR_NEXGEN, "NexGenDriven"}, + {X86_VENDOR_CENTAUR, "CentaurHauls"}, + {X86_VENDOR_RISE, "RiseRiseRise"}, + {X86_VENDOR_TRANSMETA, "GenuineTMx86"}, + {X86_VENDOR_TRANSMETA, "TransmetaCPU"}, + {X86_VENDOR_NSC, "Geode by NSC"}, + {X86_VENDOR_SIS, "SiS SiS SiS "}, + {X86_VENDOR_HYGON, "HygonGenuine"}, };
static const char *const x86_vendor_name[] = { - [X86_VENDOR_INTEL] = "Intel", - [X86_VENDOR_CYRIX] = "Cyrix", - [X86_VENDOR_AMD] = "AMD", - [X86_VENDOR_UMC] = "UMC", - [X86_VENDOR_NEXGEN] = "NexGen", - [X86_VENDOR_CENTAUR] = "Centaur", - [X86_VENDOR_RISE] = "Rise", - [X86_VENDOR_TRANSMETA] = "Transmeta", - [X86_VENDOR_NSC] = "NSC", - [X86_VENDOR_SIS] = "SiS", - [X86_VENDOR_HYGON] = "Hygon", + [X86_VENDOR_INTEL] = "Intel", [X86_VENDOR_CYRIX] = "Cyrix", + [X86_VENDOR_AMD] = "AMD", [X86_VENDOR_UMC] = "UMC", + [X86_VENDOR_NEXGEN] = "NexGen", [X86_VENDOR_CENTAUR] = "Centaur", + [X86_VENDOR_RISE] = "Rise", [X86_VENDOR_TRANSMETA] = "Transmeta", + [X86_VENDOR_NSC] = "NSC", [X86_VENDOR_SIS] = "SiS", + [X86_VENDOR_HYGON] = "Hygon", };
static const char *cpu_vendor_name(int vendor) { const char *name; name = "<invalid CPU vendor>"; - if (vendor < ARRAY_SIZE(x86_vendor_name) && - x86_vendor_name[vendor] != 0) + if (vendor < ARRAY_SIZE(x86_vendor_name) && x86_vendor_name[vendor] != 0) name = x86_vendor_name[vendor]; return name; } @@ -147,27 +140,27 @@ cpu->device = 0x00000300; /* 386 */ if (cpu->device == 0x00000400 && test_cyrix_52div()) memcpy(vendor_name, "CyrixInstead", 13); - /* If we ever care we can enable cpuid here */ + /* If we ever care we can enable cpuid here */ /* Detect NexGen with old hypercode */ else if (deep_magic_nexgen_probe()) memcpy(vendor_name, "NexGenDriven", 13); } #endif if (cpu_have_cpuid()) { - int cpuid_level; + int cpuid_level; struct cpuid_result result; result = cpuid(0x00000000); - cpuid_level = result.eax; - vendor_name[0] = (result.ebx >> 0) & 0xff; - vendor_name[1] = (result.ebx >> 8) & 0xff; - vendor_name[2] = (result.ebx >> 16) & 0xff; - vendor_name[3] = (result.ebx >> 24) & 0xff; - vendor_name[4] = (result.edx >> 0) & 0xff; - vendor_name[5] = (result.edx >> 8) & 0xff; - vendor_name[6] = (result.edx >> 16) & 0xff; - vendor_name[7] = (result.edx >> 24) & 0xff; - vendor_name[8] = (result.ecx >> 0) & 0xff; - vendor_name[9] = (result.ecx >> 8) & 0xff; + cpuid_level = result.eax; + vendor_name[0] = (result.ebx >> 0) & 0xff; + vendor_name[1] = (result.ebx >> 8) & 0xff; + vendor_name[2] = (result.ebx >> 16) & 0xff; + vendor_name[3] = (result.ebx >> 24) & 0xff; + vendor_name[4] = (result.edx >> 0) & 0xff; + vendor_name[5] = (result.edx >> 8) & 0xff; + vendor_name[6] = (result.edx >> 16) & 0xff; + vendor_name[7] = (result.edx >> 24) & 0xff; + vendor_name[8] = (result.ecx >> 0) & 0xff; + vendor_name[9] = (result.ecx >> 8) & 0xff; vendor_name[10] = (result.ecx >> 16) & 0xff; vendor_name[11] = (result.ecx >> 24) & 0xff; vendor_name[12] = '\0'; @@ -193,8 +186,7 @@ struct cpu_driver *driver; for (driver = _cpu_drivers; driver < _ecpu_drivers; driver++) { const struct cpu_device_id *id; - for (id = driver->id_table; - id->vendor != X86_VENDOR_INVALID; id++) { + for (id = driver->id_table; id->vendor != X86_VENDOR_INVALID; id++) { if (cpu->vendor == id->vendor && cpuid_match(cpu->device, id->device, id->device_match_mask)) return driver; @@ -237,13 +229,13 @@
/* Find what type of CPU we are dealing with */ identify_cpu(cpu); - printk(BIOS_DEBUG, "CPU: vendor %s device %x\n", - cpu_vendor_name(cpu->vendor), cpu->device); + printk(BIOS_DEBUG, "CPU: vendor %s device %x\n", cpu_vendor_name(cpu->vendor), + cpu->device);
get_fms(&c, cpu->device);
- printk(BIOS_DEBUG, "CPU: family %02x, model %02x, stepping %02x\n", - c.x86, c.x86_model, c.x86_mask); + printk(BIOS_DEBUG, "CPU: family %02x, model %02x, stepping %02x\n", c.x86, c.x86_model, + c.x86_mask);
/* Lookup the cpu's operations */ set_cpu_ops(cpu); @@ -312,7 +304,7 @@ if (!cpu) return CB_ERR;
- const struct cpu_info info = { .cpu = cpu, .index = index}; + const struct cpu_info info = {.cpu = cpu, .index = index}; cpu_infos[index] = info; segment_data[index].cpu_info = &cpu_infos[index];
@@ -325,15 +317,14 @@ } *segment_descriptor = (void *)&per_cpu_segment_descriptors;
segment_descriptor[index].base_address_0_15 = (uintptr_t)&segment_data[index] & 0xffff; - segment_descriptor[index].base_address_16_23 = ((uintptr_t)&segment_data[index] >> 16) & 0xff; - segment_descriptor[index].base_address_24_31 = ((uintptr_t)&segment_data[index] >> 24) & 0xff; + segment_descriptor[index].base_address_16_23 = ((uintptr_t)&segment_data[index] >> 16) & + 0xff; + segment_descriptor[index].base_address_24_31 = ((uintptr_t)&segment_data[index] >> 24) & + 0xff;
const unsigned int cpu_segment = per_cpu_segment_selector + (index << 3);
- __asm__ __volatile__ ("mov %0, %%gs\n" - : - : "r" (cpu_segment) - : ); + __asm__ __volatile__("mov %0, %%gs\n" : : "r"(cpu_segment) :);
return CB_SUCCESS; } diff --git a/src/arch/x86/cpu_common.c b/src/arch/x86/cpu_common.c index c4d30a2..4e854f0 100644 --- a/src/arch/x86/cpu_common.c +++ b/src/arch/x86/cpu_common.c @@ -9,20 +9,19 @@ { uint32_t f1, f2;
- asm( - "pushfl\n\t" - "pushfl\n\t" - "popl %0\n\t" - "movl %0,%1\n\t" - "xorl %2,%0\n\t" - "pushl %0\n\t" - "popfl\n\t" - "pushfl\n\t" - "popl %0\n\t" - "popfl\n\t" - : "=&r" (f1), "=&r" (f2) - : "ir" (flag)); - return ((f1^f2) & flag) != 0; + asm("pushfl\n\t" + "pushfl\n\t" + "popl %0\n\t" + "movl %0,%1\n\t" + "xorl %2,%0\n\t" + "pushl %0\n\t" + "popfl\n\t" + "pushfl\n\t" + "popl %0\n\t" + "popfl\n\t" + : "=&r"(f1), "=&r"(f2) + : "ir"(flag)); + return ((f1 ^ f2) & flag) != 0; }
/* Probe for the CPUID instruction */ @@ -204,8 +203,8 @@ */ uint8_t cpu_get_c_substate_support(const int state) { - if ((cpuid_get_max_func() < 5) || - !(cpuid_ecx(5) & CPUID_FEATURE_MONITOR_MWAIT) || (state > 4)) + if ((cpuid_get_max_func() < 5) || !(cpuid_ecx(5) & CPUID_FEATURE_MONITOR_MWAIT) || + (state > 4)) return 0;
return (cpuid_edx(5) >> (state * 4)) & 0xf; diff --git a/src/arch/x86/ebda.c b/src/arch/x86/ebda.c index e835fce..1fd1faa 100644 --- a/src/arch/x86/ebda.c +++ b/src/arch/x86/ebda.c @@ -5,15 +5,14 @@ #include <commonlib/endian.h> #include <types.h>
-#define X86_BDA_SIZE 0x200 -#define X86_BDA_BASE ((void *)0x400) -#define X86_EBDA_SEGMENT ((void *)0x40e) -#define X86_EBDA_LOWMEM ((void *)0x413) +#define X86_BDA_SIZE 0x200 +#define X86_BDA_BASE ((void *)0x400) +#define X86_EBDA_SEGMENT ((void *)0x40e) +#define X86_EBDA_LOWMEM ((void *)0x413)
-#define DEFAULT_EBDA_LOWMEM (1024 << 10) -#define DEFAULT_EBDA_SEGMENT 0xF600 -#define DEFAULT_EBDA_SIZE 0x400 - +#define DEFAULT_EBDA_LOWMEM (1024 << 10) +#define DEFAULT_EBDA_SEGMENT 0xF600 +#define DEFAULT_EBDA_SIZE 0x400
static void *get_ebda_start(void) { @@ -55,9 +54,7 @@ if (acpi_is_wakeup_s3()) return;
- setup_ebda(DEFAULT_EBDA_LOWMEM, - DEFAULT_EBDA_SEGMENT, - DEFAULT_EBDA_SIZE); + setup_ebda(DEFAULT_EBDA_LOWMEM, DEFAULT_EBDA_SEGMENT, DEFAULT_EBDA_SIZE); }
/* Ensure EBDA is prepared before Option ROMs. */ diff --git a/src/arch/x86/exception.c b/src/arch/x86/exception.c index e2d585f..656bfa1 100644 --- a/src/arch/x86/exception.c +++ b/src/arch/x86/exception.c @@ -19,161 +19,173 @@ */ #define BUFMAX 400 enum regnames { - EAX = 0, ECX, EDX, EBX, ESP, EBP, ESI, EDI, + EAX = 0, + ECX, + EDX, + EBX, + ESP, + EBP, + ESI, + EDI, PC /* also known as eip */, PS /* also known as eflags */, - CS, SS, DS, ES, FS, GS, + CS, + SS, + DS, + ES, + FS, + GS, NUM_REGS /* Number of registers. */ };
static uint32_t gdb_stub_registers[NUM_REGS];
-#define GDB_SIG0 0 /* Signal 0 */ -#define GDB_SIGHUP 1 /* Hangup */ -#define GDB_SIGINT 2 /* Interrupt */ -#define GDB_SIGQUIT 3 /* Quit */ -#define GDB_SIGILL 4 /* Illegal instruction */ -#define GDB_SIGTRAP 5 /* Trace/breakpoint trap */ -#define GDB_SIGABRT 6 /* Aborted */ -#define GDB_SIGEMT 7 /* Emulation trap */ -#define GDB_SIGFPE 8 /* Arithmetic exception */ -#define GDB_SIGKILL 9 /* Killed */ -#define GDB_SIGBUS 10 /* Bus error */ -#define GDB_SIGSEGV 11 /* Segmentation fault */ -#define GDB_SIGSYS 12 /* Bad system call */ -#define GDB_SIGPIPE 13 /* Broken pipe */ -#define GDB_SIGALRM 14 /* Alarm clock */ -#define GDB_SIGTERM 15 /* Terminated */ -#define GDB_SIGURG 16 /* Urgent I/O condition */ -#define GDB_SIGSTOP 17 /* Stopped (signal) */ -#define GDB_SIGTSTP 18 /* Stopped (user) */ -#define GDB_SIGCONT 19 /* Continued */ -#define GDB_SIGCHLD 20 /* Child status changed */ -#define GDB_SIGTTIN 21 /* Stopped (tty input) */ -#define GDB_SIGTTOU 22 /* Stopped (tty output) */ -#define GDB_SIGIO 23 /* I/O possible */ -#define GDB_SIGXCPU 24 /* CPU time limit exceeded */ -#define GDB_SIGXFSZ 25 /* File size limit exceeded */ -#define GDB_SIGVTALRM 26 /* Virtual timer expired */ -#define GDB_SIGPROF 27 /* Profiling timer expired */ -#define GDB_SIGWINCH 28 /* Window size changed */ -#define GDB_SIGLOST 29 /* Resource lost */ -#define GDB_SIGUSR1 30 /* User defined signal 1 */ -#define GDB_SUGUSR2 31 /* User defined signal 2 */ -#define GDB_SIGPWR 32 /* Power fail/restart */ -#define GDB_SIGPOLL 33 /* Pollable event occurred */ -#define GDB_SIGWIND 34 /* SIGWIND */ -#define GDB_SIGPHONE 35 /* SIGPHONE */ -#define GDB_SIGWAITING 36 /* Process's LWPs are blocked */ -#define GDB_SIGLWP 37 /* Signal LWP */ -#define GDB_SIGDANGER 38 /* Swap space dangerously low */ -#define GDB_SIGGRANT 39 /* Monitor mode granted */ -#define GDB_SIGRETRACT 40 /* Need to relinquish monitor mode */ -#define GDB_SIGMSG 41 /* Monitor mode data available */ -#define GDB_SIGSOUND 42 /* Sound completed */ -#define GDB_SIGSAK 43 /* Secure attention */ -#define GDB_SIGPRIO 44 /* SIGPRIO */ +#define GDB_SIG0 0 /* Signal 0 */ +#define GDB_SIGHUP 1 /* Hangup */ +#define GDB_SIGINT 2 /* Interrupt */ +#define GDB_SIGQUIT 3 /* Quit */ +#define GDB_SIGILL 4 /* Illegal instruction */ +#define GDB_SIGTRAP 5 /* Trace/breakpoint trap */ +#define GDB_SIGABRT 6 /* Aborted */ +#define GDB_SIGEMT 7 /* Emulation trap */ +#define GDB_SIGFPE 8 /* Arithmetic exception */ +#define GDB_SIGKILL 9 /* Killed */ +#define GDB_SIGBUS 10 /* Bus error */ +#define GDB_SIGSEGV 11 /* Segmentation fault */ +#define GDB_SIGSYS 12 /* Bad system call */ +#define GDB_SIGPIPE 13 /* Broken pipe */ +#define GDB_SIGALRM 14 /* Alarm clock */ +#define GDB_SIGTERM 15 /* Terminated */ +#define GDB_SIGURG 16 /* Urgent I/O condition */ +#define GDB_SIGSTOP 17 /* Stopped (signal) */ +#define GDB_SIGTSTP 18 /* Stopped (user) */ +#define GDB_SIGCONT 19 /* Continued */ +#define GDB_SIGCHLD 20 /* Child status changed */ +#define GDB_SIGTTIN 21 /* Stopped (tty input) */ +#define GDB_SIGTTOU 22 /* Stopped (tty output) */ +#define GDB_SIGIO 23 /* I/O possible */ +#define GDB_SIGXCPU 24 /* CPU time limit exceeded */ +#define GDB_SIGXFSZ 25 /* File size limit exceeded */ +#define GDB_SIGVTALRM 26 /* Virtual timer expired */ +#define GDB_SIGPROF 27 /* Profiling timer expired */ +#define GDB_SIGWINCH 28 /* Window size changed */ +#define GDB_SIGLOST 29 /* Resource lost */ +#define GDB_SIGUSR1 30 /* User defined signal 1 */ +#define GDB_SUGUSR2 31 /* User defined signal 2 */ +#define GDB_SIGPWR 32 /* Power fail/restart */ +#define GDB_SIGPOLL 33 /* Pollable event occurred */ +#define GDB_SIGWIND 34 /* SIGWIND */ +#define GDB_SIGPHONE 35 /* SIGPHONE */ +#define GDB_SIGWAITING 36 /* Process's LWPs are blocked */ +#define GDB_SIGLWP 37 /* Signal LWP */ +#define GDB_SIGDANGER 38 /* Swap space dangerously low */ +#define GDB_SIGGRANT 39 /* Monitor mode granted */ +#define GDB_SIGRETRACT 40 /* Need to relinquish monitor mode */ +#define GDB_SIGMSG 41 /* Monitor mode data available */ +#define GDB_SIGSOUND 42 /* Sound completed */ +#define GDB_SIGSAK 43 /* Secure attention */ +#define GDB_SIGPRIO 44 /* SIGPRIO */
-#define GDB_SIG33 45 /* Real-time event 33 */ -#define GDB_SIG34 46 /* Real-time event 34 */ -#define GDB_SIG35 47 /* Real-time event 35 */ -#define GDB_SIG36 48 /* Real-time event 36 */ -#define GDB_SIG37 49 /* Real-time event 37 */ -#define GDB_SIG38 50 /* Real-time event 38 */ -#define GDB_SIG39 51 /* Real-time event 39 */ -#define GDB_SIG40 52 /* Real-time event 40 */ -#define GDB_SIG41 53 /* Real-time event 41 */ -#define GDB_SIG42 54 /* Real-time event 42 */ -#define GDB_SIG43 55 /* Real-time event 43 */ -#define GDB_SIG44 56 /* Real-time event 44 */ -#define GDB_SIG45 57 /* Real-time event 45 */ -#define GDB_SIG46 58 /* Real-time event 46 */ -#define GDB_SIG47 59 /* Real-time event 47 */ -#define GDB_SIG48 60 /* Real-time event 48 */ -#define GDB_SIG49 61 /* Real-time event 49 */ -#define GDB_SIG50 62 /* Real-time event 50 */ -#define GDB_SIG51 63 /* Real-time event 51 */ -#define GDB_SIG52 64 /* Real-time event 52 */ -#define GDB_SIG53 65 /* Real-time event 53 */ -#define GDB_SIG54 66 /* Real-time event 54 */ -#define GDB_SIG55 67 /* Real-time event 55 */ -#define GDB_SIG56 68 /* Real-time event 56 */ -#define GDB_SIG57 69 /* Real-time event 57 */ -#define GDB_SIG58 70 /* Real-time event 58 */ -#define GDB_SIG59 71 /* Real-time event 59 */ -#define GDB_SIG60 72 /* Real-time event 60 */ -#define GDB_SIG61 73 /* Real-time event 61 */ -#define GDB_SIG62 74 /* Real-time event 62 */ -#define GDB_SIG63 75 /* Real-time event 63 */ -#define GDB_SIGCANCEL 76 /* LWP internal signal */ -#define GDB_SIG32 77 /* Real-time event 32 */ -#define GDB_SIG64 78 /* Real-time event 64 */ -#define GDB_SIG65 79 /* Real-time event 65 */ -#define GDB_SIG66 80 /* Real-time event 66 */ -#define GDB_SIG67 81 /* Real-time event 67 */ -#define GDB_SIG68 82 /* Real-time event 68 */ -#define GDB_SIG69 83 /* Real-time event 69 */ -#define GDB_SIG70 84 /* Real-time event 70 */ -#define GDB_SIG71 85 /* Real-time event 71 */ -#define GDB_SIG72 86 /* Real-time event 72 */ -#define GDB_SIG73 87 /* Real-time event 73 */ -#define GDB_SIG74 88 /* Real-time event 74 */ -#define GDB_SIG75 89 /* Real-time event 75 */ -#define GDB_SIG76 90 /* Real-time event 76 */ -#define GDB_SIG77 91 /* Real-time event 77 */ -#define GDB_SIG78 92 /* Real-time event 78 */ -#define GDB_SIG79 93 /* Real-time event 79 */ -#define GDB_SIG80 94 /* Real-time event 80 */ -#define GDB_SIG81 95 /* Real-time event 81 */ -#define GDB_SIG82 96 /* Real-time event 82 */ -#define GDB_SIG83 97 /* Real-time event 83 */ -#define GDB_SIG84 98 /* Real-time event 84 */ -#define GDB_SIG85 99 /* Real-time event 85 */ -#define GDB_SIG86 100 /* Real-time event 86 */ -#define GDB_SIG87 101 /* Real-time event 87 */ -#define GDB_SIG88 102 /* Real-time event 88 */ -#define GDB_SIG89 103 /* Real-time event 89 */ -#define GDB_SIG90 104 /* Real-time event 90 */ -#define GDB_SIG91 105 /* Real-time event 91 */ -#define GDB_SIG92 106 /* Real-time event 92 */ -#define GDB_SIG93 107 /* Real-time event 93 */ -#define GDB_SIG94 108 /* Real-time event 94 */ -#define GDB_SIG95 109 /* Real-time event 95 */ -#define GDB_SIG96 110 /* Real-time event 96 */ -#define GDB_SIG97 111 /* Real-time event 97 */ -#define GDB_SIG98 112 /* Real-time event 98 */ -#define GDB_SIG99 113 /* Real-time event 99 */ -#define GDB_SIG100 114 /* Real-time event 100 */ -#define GDB_SIG101 115 /* Real-time event 101 */ -#define GDB_SIG102 116 /* Real-time event 102 */ -#define GDB_SIG103 117 /* Real-time event 103 */ -#define GDB_SIG104 118 /* Real-time event 104 */ -#define GDB_SIG105 119 /* Real-time event 105 */ -#define GDB_SIG106 120 /* Real-time event 106 */ -#define GDB_SIG107 121 /* Real-time event 107 */ -#define GDB_SIG108 122 /* Real-time event 108 */ -#define GDB_SIG109 123 /* Real-time event 109 */ -#define GDB_SIG110 124 /* Real-time event 110 */ -#define GDB_SIG111 125 /* Real-time event 111 */ -#define GDB_SIG112 126 /* Real-time event 112 */ -#define GDB_SIG113 127 /* Real-time event 113 */ -#define GDB_SIG114 128 /* Real-time event 114 */ -#define GDB_SIG115 129 /* Real-time event 115 */ -#define GDB_SIG116 130 /* Real-time event 116 */ -#define GDB_SIG117 131 /* Real-time event 117 */ -#define GDB_SIG118 132 /* Real-time event 118 */ -#define GDB_SIG119 133 /* Real-time event 119 */ -#define GDB_SIG120 134 /* Real-time event 120 */ -#define GDB_SIG121 135 /* Real-time event 121 */ -#define GDB_SIG122 136 /* Real-time event 122 */ -#define GDB_SIG123 137 /* Real-time event 123 */ -#define GDB_SIG124 138 /* Real-time event 124 */ -#define GDB_SIG125 139 /* Real-time event 125 */ -#define GDB_SIG126 140 /* Real-time event 126 */ -#define GDB_SIG127 141 /* Real-time event 127 */ -#define GDB_SIGINFO 142 /* Information request */ -#define GDB_UNKNOWN 143 /* Unknown signal */ -#define GDB_DEFAULT 144 /* error: default signal */ +#define GDB_SIG33 45 /* Real-time event 33 */ +#define GDB_SIG34 46 /* Real-time event 34 */ +#define GDB_SIG35 47 /* Real-time event 35 */ +#define GDB_SIG36 48 /* Real-time event 36 */ +#define GDB_SIG37 49 /* Real-time event 37 */ +#define GDB_SIG38 50 /* Real-time event 38 */ +#define GDB_SIG39 51 /* Real-time event 39 */ +#define GDB_SIG40 52 /* Real-time event 40 */ +#define GDB_SIG41 53 /* Real-time event 41 */ +#define GDB_SIG42 54 /* Real-time event 42 */ +#define GDB_SIG43 55 /* Real-time event 43 */ +#define GDB_SIG44 56 /* Real-time event 44 */ +#define GDB_SIG45 57 /* Real-time event 45 */ +#define GDB_SIG46 58 /* Real-time event 46 */ +#define GDB_SIG47 59 /* Real-time event 47 */ +#define GDB_SIG48 60 /* Real-time event 48 */ +#define GDB_SIG49 61 /* Real-time event 49 */ +#define GDB_SIG50 62 /* Real-time event 50 */ +#define GDB_SIG51 63 /* Real-time event 51 */ +#define GDB_SIG52 64 /* Real-time event 52 */ +#define GDB_SIG53 65 /* Real-time event 53 */ +#define GDB_SIG54 66 /* Real-time event 54 */ +#define GDB_SIG55 67 /* Real-time event 55 */ +#define GDB_SIG56 68 /* Real-time event 56 */ +#define GDB_SIG57 69 /* Real-time event 57 */ +#define GDB_SIG58 70 /* Real-time event 58 */ +#define GDB_SIG59 71 /* Real-time event 59 */ +#define GDB_SIG60 72 /* Real-time event 60 */ +#define GDB_SIG61 73 /* Real-time event 61 */ +#define GDB_SIG62 74 /* Real-time event 62 */ +#define GDB_SIG63 75 /* Real-time event 63 */ +#define GDB_SIGCANCEL 76 /* LWP internal signal */ +#define GDB_SIG32 77 /* Real-time event 32 */ +#define GDB_SIG64 78 /* Real-time event 64 */ +#define GDB_SIG65 79 /* Real-time event 65 */ +#define GDB_SIG66 80 /* Real-time event 66 */ +#define GDB_SIG67 81 /* Real-time event 67 */ +#define GDB_SIG68 82 /* Real-time event 68 */ +#define GDB_SIG69 83 /* Real-time event 69 */ +#define GDB_SIG70 84 /* Real-time event 70 */ +#define GDB_SIG71 85 /* Real-time event 71 */ +#define GDB_SIG72 86 /* Real-time event 72 */ +#define GDB_SIG73 87 /* Real-time event 73 */ +#define GDB_SIG74 88 /* Real-time event 74 */ +#define GDB_SIG75 89 /* Real-time event 75 */ +#define GDB_SIG76 90 /* Real-time event 76 */ +#define GDB_SIG77 91 /* Real-time event 77 */ +#define GDB_SIG78 92 /* Real-time event 78 */ +#define GDB_SIG79 93 /* Real-time event 79 */ +#define GDB_SIG80 94 /* Real-time event 80 */ +#define GDB_SIG81 95 /* Real-time event 81 */ +#define GDB_SIG82 96 /* Real-time event 82 */ +#define GDB_SIG83 97 /* Real-time event 83 */ +#define GDB_SIG84 98 /* Real-time event 84 */ +#define GDB_SIG85 99 /* Real-time event 85 */ +#define GDB_SIG86 100 /* Real-time event 86 */ +#define GDB_SIG87 101 /* Real-time event 87 */ +#define GDB_SIG88 102 /* Real-time event 88 */ +#define GDB_SIG89 103 /* Real-time event 89 */ +#define GDB_SIG90 104 /* Real-time event 90 */ +#define GDB_SIG91 105 /* Real-time event 91 */ +#define GDB_SIG92 106 /* Real-time event 92 */ +#define GDB_SIG93 107 /* Real-time event 93 */ +#define GDB_SIG94 108 /* Real-time event 94 */ +#define GDB_SIG95 109 /* Real-time event 95 */ +#define GDB_SIG96 110 /* Real-time event 96 */ +#define GDB_SIG97 111 /* Real-time event 97 */ +#define GDB_SIG98 112 /* Real-time event 98 */ +#define GDB_SIG99 113 /* Real-time event 99 */ +#define GDB_SIG100 114 /* Real-time event 100 */ +#define GDB_SIG101 115 /* Real-time event 101 */ +#define GDB_SIG102 116 /* Real-time event 102 */ +#define GDB_SIG103 117 /* Real-time event 103 */ +#define GDB_SIG104 118 /* Real-time event 104 */ +#define GDB_SIG105 119 /* Real-time event 105 */ +#define GDB_SIG106 120 /* Real-time event 106 */ +#define GDB_SIG107 121 /* Real-time event 107 */ +#define GDB_SIG108 122 /* Real-time event 108 */ +#define GDB_SIG109 123 /* Real-time event 109 */ +#define GDB_SIG110 124 /* Real-time event 110 */ +#define GDB_SIG111 125 /* Real-time event 111 */ +#define GDB_SIG112 126 /* Real-time event 112 */ +#define GDB_SIG113 127 /* Real-time event 113 */ +#define GDB_SIG114 128 /* Real-time event 114 */ +#define GDB_SIG115 129 /* Real-time event 115 */ +#define GDB_SIG116 130 /* Real-time event 116 */ +#define GDB_SIG117 131 /* Real-time event 117 */ +#define GDB_SIG118 132 /* Real-time event 118 */ +#define GDB_SIG119 133 /* Real-time event 119 */ +#define GDB_SIG120 134 /* Real-time event 120 */ +#define GDB_SIG121 135 /* Real-time event 121 */ +#define GDB_SIG122 136 /* Real-time event 122 */ +#define GDB_SIG123 137 /* Real-time event 123 */ +#define GDB_SIG124 138 /* Real-time event 124 */ +#define GDB_SIG125 139 /* Real-time event 125 */ +#define GDB_SIG126 140 /* Real-time event 126 */ +#define GDB_SIG127 141 /* Real-time event 127 */ +#define GDB_SIGINFO 142 /* Information request */ +#define GDB_UNKNOWN 143 /* Unknown signal */ +#define GDB_DEFAULT 144 /* error: default signal */ /* Mach exceptions */ #define GDB_EXC_BAD_ACCESS 145 /* Could not access memory */ #define GDB_EXC_BAD_INSTRCTION 146 /* Illegal instruction/operand */ @@ -183,16 +195,16 @@ #define GDB_EXC_BREAKPOINT 150 /* Breakpoint */
static unsigned char exception_to_signal[] = { - [0] = GDB_SIGFPE, /* divide by zero */ - [1] = GDB_SIGTRAP, /* debug exception */ - [2] = GDB_SIGSEGV, /* NMI Interrupt */ - [3] = GDB_SIGTRAP, /* Breakpoint */ - [4] = GDB_SIGSEGV, /* into instruction (overflow) */ - [5] = GDB_SIGSEGV, /* bound instruction */ - [6] = GDB_SIGILL, /* Invalid opcode */ - [7] = GDB_SIGSEGV, /* coprocessor not available */ - [8] = GDB_SIGSEGV, /* double fault */ - [9] = GDB_SIGFPE, /* coprocessor segment overrun */ + [0] = GDB_SIGFPE, /* divide by zero */ + [1] = GDB_SIGTRAP, /* debug exception */ + [2] = GDB_SIGSEGV, /* NMI Interrupt */ + [3] = GDB_SIGTRAP, /* Breakpoint */ + [4] = GDB_SIGSEGV, /* into instruction (overflow) */ + [5] = GDB_SIGSEGV, /* bound instruction */ + [6] = GDB_SIGILL, /* Invalid opcode */ + [7] = GDB_SIGSEGV, /* coprocessor not available */ + [8] = GDB_SIGSEGV, /* double fault */ + [9] = GDB_SIGFPE, /* coprocessor segment overrun */ [10] = GDB_SIGSEGV, /* Invalid TSS */ [11] = GDB_SIGBUS, /* Segment not present */ [12] = GDB_SIGBUS, /* stack exception */ @@ -203,19 +215,10 @@ [17] = GDB_SIGBUS, /* alignment check */ [18] = GDB_SIGSEGV, /* machine check */ [19] = GDB_SIGFPE, /* simd floating point exception */ - [20] = GDB_UNKNOWN, - [21] = GDB_UNKNOWN, - [22] = GDB_UNKNOWN, - [23] = GDB_UNKNOWN, - [24] = GDB_UNKNOWN, - [25] = GDB_UNKNOWN, - [26] = GDB_UNKNOWN, - [27] = GDB_UNKNOWN, - [28] = GDB_UNKNOWN, - [29] = GDB_UNKNOWN, - [30] = GDB_UNKNOWN, - [31] = GDB_UNKNOWN, - [32] = GDB_SIGINT, /* User interrupt */ + [20] = GDB_UNKNOWN, [21] = GDB_UNKNOWN, [22] = GDB_UNKNOWN, [23] = GDB_UNKNOWN, + [24] = GDB_UNKNOWN, [25] = GDB_UNKNOWN, [26] = GDB_UNKNOWN, [27] = GDB_UNKNOWN, + [28] = GDB_UNKNOWN, [29] = GDB_UNKNOWN, [30] = GDB_UNKNOWN, [31] = GDB_UNKNOWN, + [32] = GDB_SIGINT, /* User interrupt */ };
static const char hexchars[] = "0123456789abcdef"; @@ -333,10 +336,10 @@ xmitcsum += hex(stub_getc() & 0x7f);
if (checksum != xmitcsum) { - stub_putc('-'); /* failed checksum */ + stub_putc('-'); /* failed checksum */ stub_flush(); } else { - stub_putc('+'); /* successful transfer */ + stub_putc('+'); /* successful transfer */ stub_flush(); } } @@ -369,7 +372,6 @@ stub_flush();
} while ((stub_getc() & 0x7f) != '+'); - } #endif /* CONFIG_GDB_STUB */
@@ -381,7 +383,7 @@ { #if CONFIG(GDB_STUB) int signo; - memcpy(gdb_stub_registers, info, 8*sizeof(uint32_t)); + memcpy(gdb_stub_registers, info, 8 * sizeof(uint32_t)); gdb_stub_registers[PC] = info->eip; gdb_stub_registers[CS] = info->cs; gdb_stub_registers[PS] = info->eflags; @@ -391,7 +393,7 @@
/* reply to the host that an exception has occurred */ out_buffer[0] = 'S'; - out_buffer[1] = hexchars[(signo>>4) & 0xf]; + out_buffer[1] = hexchars[(signo >> 4) & 0xf]; out_buffer[2] = hexchars[signo & 0xf]; out_buffer[3] = '\0'; put_packet(out_buffer); @@ -412,23 +414,22 @@ break; case 'g': /* return the value of the CPU registers */ copy_to_hex(out_buffer, &gdb_stub_registers, - sizeof(gdb_stub_registers)); + sizeof(gdb_stub_registers)); break; case 'G': /* set the value of the CPU registers - return OK */ copy_from_hex(&gdb_stub_registers, in_buffer + 1, - sizeof(gdb_stub_registers)); - memcpy(info, gdb_stub_registers, 8*sizeof(uint32_t)); - info->eip = gdb_stub_registers[PC]; - info->cs = gdb_stub_registers[CS]; + sizeof(gdb_stub_registers)); + memcpy(info, gdb_stub_registers, 8 * sizeof(uint32_t)); + info->eip = gdb_stub_registers[PC]; + info->cs = gdb_stub_registers[CS]; info->eflags = gdb_stub_registers[PS]; memcpy(out_buffer, "OK", 3); break; case 'm': /* mAA..AA,LLLL Read LLLL bytes at address AA..AA */ ptr = &in_buffer[1]; - if (parse_ulong(&ptr, &addr) && - (*ptr++ == ',') && - parse_ulong(&ptr, &length)) { + if (parse_ulong(&ptr, &addr) && (*ptr++ == ',') && + parse_ulong(&ptr, &length)) { copy_to_hex(out_buffer, (void *)addr, length); } else memcpy(out_buffer, "E01", 4); @@ -438,10 +439,8 @@ * return OK */ ptr = &in_buffer[1]; - if (parse_ulong(&ptr, &addr) && - (*(ptr++) == ',') && - parse_ulong(&ptr, &length) && - (*(ptr++) == ':')) { + if (parse_ulong(&ptr, &addr) && (*(ptr++) == ',') && + parse_ulong(&ptr, &length) && (*(ptr++) == ':')) { copy_from_hex((void *)addr, ptr, length); memcpy(out_buffer, "OK", 3); } else @@ -465,20 +464,20 @@ case 'D': memcpy(out_buffer, "OK", 3); break; - case 'k': /* kill request? */ + case 'k': /* kill request? */ break; - case 'q': /* query */ + case 'q': /* query */ break; - case 'z': /* z0AAAA,LLLL remove memory breakpoint */ - /* z1AAAA,LLLL remove hardware breakpoint */ - /* z2AAAA,LLLL remove write watchpoint */ - /* z3AAAA,LLLL remove read watchpoint */ - /* z4AAAA,LLLL remove access watchpoint */ - case 'Z': /* Z0AAAA,LLLL insert memory breakpoint */ - /* Z1AAAA,LLLL insert hardware breakpoint */ - /* Z2AAAA,LLLL insert write watchpoint */ - /* Z3AAAA,LLLL insert read watchpoint */ - /* Z4AAAA,LLLL insert access watchpoint */ + case 'z': /* z0AAAA,LLLL remove memory breakpoint */ + /* z1AAAA,LLLL remove hardware breakpoint */ + /* z2AAAA,LLLL remove write watchpoint */ + /* z3AAAA,LLLL remove read watchpoint */ + /* z4AAAA,LLLL remove access watchpoint */ + case 'Z': /* Z0AAAA,LLLL insert memory breakpoint */ + /* Z1AAAA,LLLL insert hardware breakpoint */ + /* Z2AAAA,LLLL insert write watchpoint */ + /* Z3AAAA,LLLL insert read watchpoint */ + /* Z4AAAA,LLLL insert access watchpoint */ break; default: break; @@ -501,39 +500,34 @@ #if ENV_X86_64 #define MDUMP_SIZE 0x100 printk(BIOS_EMERG, - "CPU Index %d - APIC %d Unexpected Exception:\n" - "%lld @ %02llx:%016llx - Halting\n" - "Code: %lld rflags: %016llx cr2: %016llx\n" - "rax: %016llx rbx: %016llx\n" - "rcx: %016llx rdx: %016llx\n" - "rdi: %016llx rsi: %016llx\n" - "rbp: %016llx rsp: %016llx\n" - "r08: %016llx r09: %016llx\n" - "r10: %016llx r11: %016llx\n" - "r12: %016llx r13: %016llx\n" - "r14: %016llx r15: %016llx\n", - logical_processor, early_lapicid(), - info->vector, info->cs, info->rip, - info->error_code, info->rflags, read_cr2(), - info->rax, info->rbx, info->rcx, info->rdx, - info->rdi, info->rsi, info->rbp, info->rsp, - info->r8, info->r9, info->r10, info->r11, - info->r12, info->r13, info->r14, info->r15); + "CPU Index %d - APIC %d Unexpected Exception:\n" + "%lld @ %02llx:%016llx - Halting\n" + "Code: %lld rflags: %016llx cr2: %016llx\n" + "rax: %016llx rbx: %016llx\n" + "rcx: %016llx rdx: %016llx\n" + "rdi: %016llx rsi: %016llx\n" + "rbp: %016llx rsp: %016llx\n" + "r08: %016llx r09: %016llx\n" + "r10: %016llx r11: %016llx\n" + "r12: %016llx r13: %016llx\n" + "r14: %016llx r15: %016llx\n", + logical_processor, early_lapicid(), info->vector, info->cs, info->rip, + info->error_code, info->rflags, read_cr2(), info->rax, info->rbx, info->rcx, + info->rdx, info->rdi, info->rsi, info->rbp, info->rsp, info->r8, info->r9, + info->r10, info->r11, info->r12, info->r13, info->r14, info->r15); code = (u8 *)((uintptr_t)info->rip - (MDUMP_SIZE >> 2)); #else #define MDUMP_SIZE 0x80
printk(BIOS_EMERG, - "CPU Index %d - APIC %d Unexpected Exception:" - "%d @ %02x:%08x - Halting\n" - "Code: %d eflags: %08x cr2: %08x\n" - "eax: %08x ebx: %08x ecx: %08x edx: %08x\n" - "edi: %08x esi: %08x ebp: %08x esp: %08x\n", - logical_processor, early_lapicid(), - info->vector, info->cs, info->eip, - info->error_code, info->eflags, read_cr2(), - info->eax, info->ebx, info->ecx, info->edx, - info->edi, info->esi, info->ebp, info->esp); + "CPU Index %d - APIC %d Unexpected Exception:" + "%d @ %02x:%08x - Halting\n" + "Code: %d eflags: %08x cr2: %08x\n" + "eax: %08x ebx: %08x ecx: %08x edx: %08x\n" + "edi: %08x esi: %08x ebp: %08x esp: %08x\n", + logical_processor, early_lapicid(), info->vector, info->cs, info->eip, + info->error_code, info->eflags, read_cr2(), info->eax, info->ebx, info->ecx, + info->edx, info->edi, info->esi, info->ebp, info->esp); code = (u8 *)((uintptr_t)info->eip - (MDUMP_SIZE >> 1)); #endif /* Align to 8-byte boundary please, and print eight bytes per row. @@ -561,10 +555,10 @@ #endif }
-#define GATE_P (1 << 15) -#define GATE_DPL(x) (((x) & 0x3) << 13) -#define GATE_SIZE_16 (0 << 11) -#define GATE_SIZE_32 (1 << 11) +#define GATE_P (1 << 15) +#define GATE_DPL(x) (((x)&0x3) << 13) +#define GATE_SIZE_16 (0 << 11) +#define GATE_SIZE_32 (1 << 11)
#define IGATE_FLAGS (GATE_P | GATE_DPL(0) | GATE_SIZE_32 | (0x6 << 8))
@@ -590,9 +584,9 @@ extern u8 vec16[], vec17[], vec18[], vec19[];
static const uintptr_t intr_entries[] = { - (uintptr_t)vec0, (uintptr_t)vec1, (uintptr_t)vec2, (uintptr_t)vec3, - (uintptr_t)vec4, (uintptr_t)vec5, (uintptr_t)vec6, (uintptr_t)vec7, - (uintptr_t)vec8, (uintptr_t)vec9, (uintptr_t)vec10, (uintptr_t)vec11, + (uintptr_t)vec0, (uintptr_t)vec1, (uintptr_t)vec2, (uintptr_t)vec3, + (uintptr_t)vec4, (uintptr_t)vec5, (uintptr_t)vec6, (uintptr_t)vec7, + (uintptr_t)vec8, (uintptr_t)vec9, (uintptr_t)vec10, (uintptr_t)vec11, (uintptr_t)vec12, (uintptr_t)vec13, (uintptr_t)vec14, (uintptr_t)vec15, (uintptr_t)vec16, (uintptr_t)vec17, (uintptr_t)vec18, (uintptr_t)vec19, }; @@ -603,12 +597,7 @@ { uint16_t segment;
- asm volatile ( - "mov %%cs, %0\n" - : "=r" (segment) - : - : "memory" - ); + asm volatile("mov %%cs, %0\n" : "=r"(segment) : : "memory");
return segment; } @@ -633,12 +622,7 @@ .base = (uintptr_t)table, };
- asm volatile ( - "lidt %0" - : - : "m" (lidtarg) - : "memory" - ); + asm volatile("lidt %0" : : "m"(lidtarg) : "memory");
if (ENV_RAMSTAGE) memcpy(&idtarg, &lidtarg, sizeof(idtarg)); diff --git a/src/arch/x86/ioapic.c b/src/arch/x86/ioapic.c index 04c852b..33d188a 100644 --- a/src/arch/x86/ioapic.c +++ b/src/arch/x86/ioapic.c @@ -6,20 +6,20 @@ #include <console/console.h> #include <cpu/x86/lapic.h>
-#define ALL (0xff << 24) -#define NONE (0) -#define INT_DISABLED (1 << 16) -#define INT_ENABLED (0 << 16) -#define TRIGGER_EDGE (0 << 15) -#define TRIGGER_LEVEL (1 << 15) -#define POLARITY_HIGH (0 << 13) -#define POLARITY_LOW (1 << 13) -#define PHYSICAL_DEST (0 << 11) -#define LOGICAL_DEST (1 << 11) -#define ExtINT (7 << 8) -#define NMI (4 << 8) -#define SMI (2 << 8) -#define INT (1 << 8) +#define ALL (0xff << 24) +#define NONE (0) +#define INT_DISABLED (1 << 16) +#define INT_ENABLED (0 << 16) +#define TRIGGER_EDGE (0 << 15) +#define TRIGGER_LEVEL (1 << 15) +#define POLARITY_HIGH (0 << 13) +#define POLARITY_LOW (1 << 13) +#define PHYSICAL_DEST (0 << 11) +#define LOGICAL_DEST (1 << 11) +#define ExtINT (7 << 8) +#define NMI (4 << 8) +#define SMI (2 << 8) +#define INT (1 << 8)
static u32 io_apic_read(void *ioapic_base, u32 reg) { @@ -38,8 +38,7 @@ io_apic_write(ioapic_base, vector * 2 + 0x10, low); io_apic_write(ioapic_base, vector * 2 + 0x11, high);
- printk(BIOS_SPEW, "IOAPIC: vector 0x%02x value 0x%08x 0x%08x\n", - vector, high, low); + printk(BIOS_SPEW, "IOAPIC: vector 0x%02x value 0x%08x 0x%08x\n", vector, high, low); }
/* Bits 23-16 of register 0x01 specify the maximum redirection entry, which @@ -108,8 +107,7 @@
ASSERT(bsp_lapicid < 255);
- printk(BIOS_DEBUG, "IOAPIC: Bootstrap Processor Local APIC = 0x%02x\n", - bsp_lapicid); + printk(BIOS_DEBUG, "IOAPIC: Bootstrap Processor Local APIC = 0x%02x\n", bsp_lapicid);
/* Enable Virtual Wire Mode. Should this be LOGICAL_DEST instead? */ low = INT_ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST | ExtINT; @@ -127,22 +125,19 @@ { int i;
- printk(BIOS_DEBUG, "IOAPIC: Initializing IOAPIC at %p\n", - ioapic_base); + printk(BIOS_DEBUG, "IOAPIC: Initializing IOAPIC at %p\n", ioapic_base); printk(BIOS_DEBUG, "IOAPIC: ID = 0x%02x\n", ioapic_id);
if (ioapic_id) { /* Set IOAPIC ID if it has been specified. */ io_apic_write(ioapic_base, 0x00, - (io_apic_read(ioapic_base, 0x00) & 0xf0ffffff) | - (ioapic_id << 24)); + (io_apic_read(ioapic_base, 0x00) & 0xf0ffffff) | + (ioapic_id << 24)); }
printk(BIOS_SPEW, "IOAPIC: Dumping registers\n"); for (i = 0; i < 3; i++) - printk(BIOS_SPEW, " reg 0x%04x: 0x%08x\n", i, - io_apic_read(ioapic_base, i)); - + printk(BIOS_SPEW, " reg 0x%04x: 0x%08x\n", i, io_apic_read(ioapic_base, i)); }
u8 get_ioapic_id(void *ioapic_base) @@ -168,11 +163,9 @@ * on the front side bus, enable that. */ printk(BIOS_DEBUG, "IOAPIC: Enabling interrupts on FSB\n"); - io_apic_write(ioapic_base, 0x03, - io_apic_read(ioapic_base, 0x03) | (1 << 0)); + io_apic_write(ioapic_base, 0x03, io_apic_read(ioapic_base, 0x03) | (1 << 0)); } else { - printk(BIOS_DEBUG, - "IOAPIC: Enabling interrupts on APIC serial bus\n"); + printk(BIOS_DEBUG, "IOAPIC: Enabling interrupts on APIC serial bus\n"); io_apic_write(ioapic_base, 0x03, 0); } } diff --git a/src/arch/x86/memcpy.c b/src/arch/x86/memcpy.c index 9da2a75..8b2a406 100644 --- a/src/arch/x86/memcpy.c +++ b/src/arch/x86/memcpy.c @@ -9,31 +9,26 @@ unsigned long d0, d1, d2;
#if (ENV_SEPARATE_ROMSTAGE && CONFIG(ASAN_IN_ROMSTAGE)) || \ - (ENV_RAMSTAGE && CONFIG(ASAN_IN_RAMSTAGE)) + (ENV_RAMSTAGE && CONFIG(ASAN_IN_RAMSTAGE)) check_memory_region((unsigned long)src, n, false, _RET_IP_); check_memory_region((unsigned long)dest, n, true, _RET_IP_); #endif
#if ENV_X86_64 - asm volatile( - "rep ; movsq\n\t" - "mov %4,%%rcx\n\t" - "rep ; movsb\n\t" - : "=&c" (d0), "=&D" (d1), "=&S" (d2) - : "0" (n >> 3), "g" (n & 7), "1" (dest), "2" (src) - : "memory" - ); + asm volatile("rep ; movsq\n\t" + "mov %4,%%rcx\n\t" + "rep ; movsb\n\t" + : "=&c"(d0), "=&D"(d1), "=&S"(d2) + : "0"(n >> 3), "g"(n & 7), "1"(dest), "2"(src) + : "memory"); #else - asm volatile( - "rep ; movsl\n\t" - "movl %4,%%ecx\n\t" - "rep ; movsb\n\t" - : "=&c" (d0), "=&D" (d1), "=&S" (d2) - : "0" (n >> 2), "g" (n & 3), "1" (dest), "2" (src) - : "memory" - ); + asm volatile("rep ; movsl\n\t" + "movl %4,%%ecx\n\t" + "rep ; movsb\n\t" + : "=&c"(d0), "=&D"(d1), "=&S"(d2) + : "0"(n >> 2), "g"(n & 3), "1"(dest), "2"(src) + : "memory"); #endif
- return dest; } diff --git a/src/arch/x86/memmove_32.c b/src/arch/x86/memmove_32.c index 387a77e..858db65 100644 --- a/src/arch/x86/memmove_32.c +++ b/src/arch/x86/memmove_32.c @@ -13,7 +13,7 @@ char *ret = dest;
#if (ENV_SEPARATE_ROMSTAGE && CONFIG(ASAN_IN_ROMSTAGE)) || \ - (ENV_RAMSTAGE && CONFIG(ASAN_IN_RAMSTAGE)) + (ENV_RAMSTAGE && CONFIG(ASAN_IN_RAMSTAGE)) check_memory_region((unsigned long)src, n, false, _RET_IP_); check_memory_region((unsigned long)dest, n, true, _RET_IP_); #endif @@ -188,13 +188,9 @@ "movb %%cl, (%2)\n\t" ".p2align 4\n\t" "11:" - : "=&c" (d0), "=&S" (d1), "=&D" (d2), - "=r" (d3), "=r" (d4), "=r"(d5) - : "0" (n), - "1" (src), - "2" (dest) + : "=&c"(d0), "=&S"(d1), "=&D"(d2), "=r"(d3), "=r"(d4), "=r"(d5) + : "0"(n), "1"(src), "2"(dest) : "memory");
return ret; - } diff --git a/src/arch/x86/memset.c b/src/arch/x86/memset.c index 142dda3..dd2fb9f 100644 --- a/src/arch/x86/memset.c +++ b/src/arch/x86/memset.c @@ -15,7 +15,7 @@ unsigned long int dstp = (unsigned long int)dstpp;
#if (ENV_SEPARATE_ROMSTAGE && CONFIG(ASAN_IN_ROMSTAGE)) || \ - (ENV_RAMSTAGE && CONFIG(ASAN_IN_RAMSTAGE)) + (ENV_RAMSTAGE && CONFIG(ASAN_IN_RAMSTAGE)) check_memory_region((unsigned long)dstpp, len, true, _RET_IP_); #endif
@@ -42,30 +42,27 @@ */
/* Fill bytes until DSTP is aligned on a longword boundary. */ - asm volatile( - "rep\n" - "stosb" /* %0, %2, %3 */ : - "=D" (dstp), "=c" (d0) : - "0" (dstp), "1" ((-dstp) % sizeof(op_t)), "a" (x) : - "memory"); + asm volatile("rep\n" + "stosb" /* %0, %2, %3 */ + : "=D"(dstp), "=c"(d0) + : "0"(dstp), "1"((-dstp) % sizeof(op_t)), "a"(x) + : "memory");
/* Fill longwords. */ - asm volatile( - "rep\n" - "stosl" /* %0, %2, %3 */ : - "=D" (dstp), "=c" (d0) : - "0" (dstp), "1" (len / sizeof(op_t)), "a" (x) : - "memory"); + asm volatile("rep\n" + "stosl" /* %0, %2, %3 */ + : "=D"(dstp), "=c"(d0) + : "0"(dstp), "1"(len / sizeof(op_t)), "a"(x) + : "memory"); len %= sizeof(op_t); }
/* Write the last few bytes. */ - asm volatile( - "rep\n" - "stosb" /* %0, %2, %3 */ : - "=D" (dstp), "=c" (d0) : - "0" (dstp), "1" (len), "a" (x) : - "memory"); + asm volatile("rep\n" + "stosb" /* %0, %2, %3 */ + : "=D"(dstp), "=c"(d0) + : "0"(dstp), "1"(len), "a"(x) + : "memory");
return dstpp; } diff --git a/src/arch/x86/mmap_boot.c b/src/arch/x86/mmap_boot.c index 0e9812f..23a5434 100644 --- a/src/arch/x86/mmap_boot.c +++ b/src/arch/x86/mmap_boot.c @@ -5,7 +5,7 @@ #include <stdint.h>
/* The ROM is memory mapped just below 4GiB. Form a pointer for the base. */ -#define rom_base ((void *)(uintptr_t)(0x100000000ULL-CONFIG_ROM_SIZE)) +#define rom_base ((void *)(uintptr_t)(0x100000000ULL - CONFIG_ROM_SIZE))
static const struct mem_region_device boot_dev = MEM_REGION_DEV_RO_INIT(rom_base, CONFIG_ROM_SIZE); diff --git a/src/arch/x86/mpspec.c b/src/arch/x86/mpspec.c index 64712c7..0757e51 100644 --- a/src/arch/x86/mpspec.c +++ b/src/arch/x86/mpspec.c @@ -23,12 +23,12 @@
memcpy(mc->mpc_signature, MPC_SIGNATURE, 4);
- mc->mpc_length = sizeof(*mc); /* Initially just the header size. */ - mc->mpc_spec = 0x04; /* MultiProcessor specification 1.4 */ - mc->mpc_checksum = 0; /* Not yet computed. */ + mc->mpc_length = sizeof(*mc); /* Initially just the header size. */ + mc->mpc_spec = 0x04; /* MultiProcessor specification 1.4 */ + mc->mpc_checksum = 0; /* Not yet computed. */ mc->mpc_oemptr = 0; mc->mpc_oemsize = 0; - mc->mpc_entry_count = 0; /* No entries yet... */ + mc->mpc_entry_count = 0; /* No entries yet... */ mc->mpc_lapic = lapic_addr; mc->mpe_length = 0; mc->mpe_checksum = 0; @@ -59,8 +59,8 @@ return checksum; }
-static void *smp_write_floating_table_physaddr(uintptr_t addr, - uintptr_t mpf_physptr, unsigned int virtualwire) +static void *smp_write_floating_table_physaddr(uintptr_t addr, uintptr_t mpf_physptr, + unsigned int virtualwire) { struct intel_mp_floating *mf; void *v; @@ -76,11 +76,11 @@ mf->mpf_specification = 4; mf->mpf_checksum = 0; mf->mpf_feature1 = 0; - mf->mpf_feature2 = virtualwire?MP_FEATURE_PIC:MP_FEATURE_VIRTUALWIRE; + mf->mpf_feature2 = virtualwire ? MP_FEATURE_PIC : MP_FEATURE_VIRTUALWIRE; mf->mpf_feature3 = 0; mf->mpf_feature4 = 0; mf->mpf_feature5 = 0; - mf->mpf_checksum = smp_compute_checksum(mf, mf->mpf_length*16); + mf->mpf_checksum = smp_compute_checksum(mf, mf->mpf_length * 16); return v; }
@@ -88,8 +88,8 @@ { /* 16 byte align the table address */ addr = (addr + 0xf) & (~0xf); - return smp_write_floating_table_physaddr(addr, addr - + SMP_FLOATING_TABLE_LEN, virtualwire); + return smp_write_floating_table_physaddr(addr, addr + SMP_FLOATING_TABLE_LEN, + virtualwire); }
void *smp_next_mpc_entry(struct mp_config_table *mc) @@ -122,9 +122,8 @@ * Entry Type, LAPIC ID, LAPIC Version, CPU Flags EN/BP, * CPU Signature (Stepping, Model, Family), Feature Flags */ -void smp_write_processor(struct mp_config_table *mc, - u8 apicid, u8 apicver, u8 cpuflag, - u32 cpufeature, u32 featureflag) +void smp_write_processor(struct mp_config_table *mc, u8 apicid, u8 apicver, u8 cpuflag, + u32 cpufeature, u32 featureflag) { struct mpc_config_processor *mpc; mpc = smp_next_mpc_entry(mc); @@ -169,15 +168,11 @@ cpu_flag = MPC_CPU_ENABLED;
if (boot_apic_id == cpu->path.apic.apic_id) - cpu_flag = MPC_CPU_ENABLED - | MPC_CPU_BOOTPROCESSOR; + cpu_flag = MPC_CPU_ENABLED | MPC_CPU_BOOTPROCESSOR;
if (cpu->path.apic.apic_id == order_id) { - smp_write_processor(mc, - cpu->path.apic.apic_id, apic_version, - cpu_flag, cpu_features, - cpu_feature_flags - ); + smp_write_processor(mc, cpu->path.apic.apic_id, apic_version, + cpu_flag, cpu_features, cpu_feature_flags); break; } } @@ -188,8 +183,7 @@ * Type 1: Bus Entries: * Entry Type, Bus ID, Bus Type */ -static void smp_write_bus(struct mp_config_table *mc, - u8 id, const char *bustype) +static void smp_write_bus(struct mp_config_table *mc, u8 id, const char *bustype) { struct mpc_config_bus *mpc; mpc = smp_next_mpc_entry(mc); @@ -205,8 +199,7 @@ * Entry Type, APIC ID, Version, * APIC Flags:EN, Address */ -void smp_write_ioapic(struct mp_config_table *mc, - u8 id, u8 ver, void *apicaddr) +void smp_write_ioapic(struct mp_config_table *mc, u8 id, u8 ver, void *apicaddr) { struct mpc_config_ioapic *mpc; mpc = smp_next_mpc_entry(mc); @@ -232,10 +225,8 @@ * Entry Type, Int Type, Int Polarity, Int Level, * Source Bus ID, Source Bus IRQ, Dest APIC ID, Dest PIN# */ -void smp_write_intsrc(struct mp_config_table *mc, - u8 irqtype, u16 irqflag, - u8 srcbus, u8 srcbusirq, - u8 dstapic, u8 dstirq) +void smp_write_intsrc(struct mp_config_table *mc, u8 irqtype, u16 irqflag, u8 srcbus, + u8 srcbusirq, u8 dstapic, u8 dstirq) { struct mpc_config_intsrc *mpc; mpc = smp_next_mpc_entry(mc); @@ -259,21 +250,19 @@ * Bits 2-6: Originating PCI Device Number (Not its parent bridge device number) * Bit 7: Reserved */ -void smp_write_pci_intsrc(struct mp_config_table *mc, - u8 irqtype, u8 srcbus, u8 dev, u8 pirq, - u8 dstapic, u8 dstirq) +void smp_write_pci_intsrc(struct mp_config_table *mc, u8 irqtype, u8 srcbus, u8 dev, u8 pirq, + u8 dstapic, u8 dstirq) { u8 srcbusirq = (dev << 2) | pirq; - printk(BIOS_SPEW, - "\tPCI srcbusirq = 0x%x from dev = 0x%x and pirq = %x\n", - srcbusirq, dev, pirq); - smp_write_intsrc(mc, irqtype, MP_IRQ_TRIGGER_LEVEL - | MP_IRQ_POLARITY_LOW, srcbus, srcbusirq, dstapic, dstirq); + printk(BIOS_SPEW, "\tPCI srcbusirq = 0x%x from dev = 0x%x and pirq = %x\n", srcbusirq, + dev, pirq); + smp_write_intsrc(mc, irqtype, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, srcbus, + srcbusirq, dstapic, dstirq); }
-void smp_write_intsrc_pci_bridge(struct mp_config_table *mc, - u8 irqtype, u16 irqflag, struct device *dev, - unsigned char dstapic, unsigned char *dstirq) +void smp_write_intsrc_pci_bridge(struct mp_config_table *mc, u8 irqtype, u16 irqflag, + struct device *dev, unsigned char dstapic, + unsigned char *dstirq) { struct device *child;
@@ -285,7 +274,6 @@ unsigned char dstirq_x[4];
for (link = dev->link_list; link; link = link->next) { - child = link->children; srcbus = link->secondary;
@@ -300,29 +288,25 @@
if ((child->class >> 16) != PCI_BASE_CLASS_BRIDGE) { /* pci device */ - printk(BIOS_DEBUG, "route irq: %s\n", - dev_path(child)); + printk(BIOS_DEBUG, "route irq: %s\n", dev_path(child)); for (i = 0; i < 4; i++) - smp_write_intsrc(mc, irqtype, irqflag, - srcbus, (slot<<2)|i, dstapic, - dstirq_x[i]); + smp_write_intsrc(mc, irqtype, irqflag, srcbus, + (slot << 2) | i, dstapic, dstirq_x[i]); goto next; }
- switch (child->class>>8) { + switch (child->class >> 8) { case PCI_CLASS_BRIDGE_PCI: case PCI_CLASS_BRIDGE_PCMCIA: case PCI_CLASS_BRIDGE_CARDBUS: - printk(BIOS_DEBUG, "route irq bridge: %s\n", - dev_path(child)); - smp_write_intsrc_pci_bridge(mc, irqtype, - irqflag, child, dstapic, dstirq_x); + printk(BIOS_DEBUG, "route irq bridge: %s\n", dev_path(child)); + smp_write_intsrc_pci_bridge(mc, irqtype, irqflag, child, + dstapic, dstirq_x); }
next: child = child->sibling; } - } }
@@ -332,10 +316,8 @@ * Source Bus ID, Source Bus IRQ, Dest LAPIC ID, * Dest LAPIC LINTIN# */ -void smp_write_lintsrc(struct mp_config_table *mc, - u8 irqtype, u16 irqflag, - u8 srcbusid, u8 srcbusirq, - u8 destapic, u8 destapiclint) +void smp_write_lintsrc(struct mp_config_table *mc, u8 irqtype, u16 irqflag, u8 srcbusid, + u8 srcbusirq, u8 destapic, u8 destapiclint) { struct mpc_config_lintsrc *mpc; mpc = smp_next_mpc_entry(mc); @@ -355,10 +337,9 @@ * Entry Type, Entry Length, Bus ID, Address Type, * Address Base Lo/Hi, Address Length Lo/Hi */ -void smp_write_address_space(struct mp_config_table *mc, - u8 busid, u8 address_type, - u32 address_base_low, u32 address_base_high, - u32 address_length_low, u32 address_length_high) +void smp_write_address_space(struct mp_config_table *mc, u8 busid, u8 address_type, + u32 address_base_low, u32 address_base_high, + u32 address_length_low, u32 address_length_high) { struct mp_exten_system_address_space *mpe; mpe = smp_next_mpe_entry(mc); @@ -367,9 +348,9 @@ mpe->mpe_length = sizeof(*mpe); mpe->mpe_busid = busid; mpe->mpe_address_type = address_type; - mpe->mpe_address_base_low = address_base_low; + mpe->mpe_address_base_low = address_base_low; mpe->mpe_address_base_high = address_base_high; - mpe->mpe_address_length_low = address_length_low; + mpe->mpe_address_length_low = address_length_low; mpe->mpe_address_length_high = address_length_high; smp_add_mpe_entry(mc, (mpe_t)mpe); } @@ -379,8 +360,7 @@ * Entry Type, Entry Length, Bus ID, Bus Info, * Parent Bus ID */ -void smp_write_bus_hierarchy(struct mp_config_table *mc, - u8 busid, u8 bus_info, u8 parent_busid) +void smp_write_bus_hierarchy(struct mp_config_table *mc, u8 busid, u8 bus_info, u8 parent_busid) { struct mp_exten_bus_hierarchy *mpe; mpe = smp_next_mpe_entry(mc); @@ -398,9 +378,8 @@ * Entry Type, Entry Length, Bus ID, Address Modifier * Predefined Range List */ -void smp_write_compatibility_address_space(struct mp_config_table *mc, - u8 busid, u8 address_modifier, - u32 range_list) +void smp_write_compatibility_address_space(struct mp_config_table *mc, u8 busid, + u8 address_modifier, u32 range_list) { struct mp_exten_compatibility_address_space *mpe; mpe = smp_next_mpe_entry(mc); @@ -415,53 +394,50 @@
void mptable_lintsrc(struct mp_config_table *mc, unsigned long bus_isa) { - smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE - | MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0); - smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE - | MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1); + smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, + 0x0, MP_APIC_ALL, 0x0); + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, + MP_APIC_ALL, 0x1); }
-void mptable_add_isa_interrupts(struct mp_config_table *mc, - unsigned long bus_isa, unsigned long apicid, int external_int2) +void mptable_add_isa_interrupts(struct mp_config_table *mc, unsigned long bus_isa, + unsigned long apicid, int external_int2) { -/*I/O Ints: Type Trigger Polarity + /*I/O Ints: Type Trigger Polarity * Bus ID IRQ APIC ID PIN# */ - smp_write_intsrc(mc, external_int2?mp_INT:mp_ExtINT, - MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, - bus_isa, 0x0, apicid, 0x0); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, - bus_isa, 0x1, apicid, 0x1); - smp_write_intsrc(mc, external_int2?mp_ExtINT:mp_INT, - MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, - bus_isa, 0x0, apicid, 0x2); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, - bus_isa, 0x3, apicid, 0x3); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, - bus_isa, 0x4, apicid, 0x4); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, - bus_isa, 0x6, apicid, 0x6); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, - bus_isa, 0x7, apicid, 0x7); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, - bus_isa, 0x8, apicid, 0x8); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, - bus_isa, 0x9, apicid, 0x9); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, - bus_isa, 0xa, apicid, 0xa); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, - bus_isa, 0xb, apicid, 0xb); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, - bus_isa, 0xc, apicid, 0xc); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, - bus_isa, 0xd, apicid, 0xd); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, - bus_isa, 0xe, apicid, 0xe); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, - bus_isa, 0xf, apicid, 0xf); + smp_write_intsrc(mc, external_int2 ? mp_INT : mp_ExtINT, + MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid, 0x0); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, 0x1, + apicid, 0x1); + smp_write_intsrc(mc, external_int2 ? mp_ExtINT : mp_INT, + MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid, 0x2); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, 0x3, + apicid, 0x3); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, 0x4, + apicid, 0x4); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, 0x6, + apicid, 0x6); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, 0x7, + apicid, 0x7); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, 0x8, + apicid, 0x8); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, 0x9, + apicid, 0x9); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, 0xa, + apicid, 0xa); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, 0xb, + apicid, 0xb); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, 0xc, + apicid, 0xc); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, 0xd, + apicid, 0xd); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, 0xe, + apicid, 0xe); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, 0xf, + apicid, 0xf); }
-void mptable_write_buses(struct mp_config_table *mc, int *max_pci_bus, - int *isa_bus) +void mptable_write_buses(struct mp_config_table *mc, int *max_pci_bus, int *isa_bus) { int dummy, i, highest; char buses[256]; @@ -481,7 +457,7 @@ for (bus = dev->link_list; bus; bus = bus->next) { if (bus->secondary > 255) { printk(BIOS_ERR, - "A bus claims to have a bus ID > 255?!? Aborting"); + "A bus claims to have a bus ID > 255?!? Aborting"); return; } buses[bus->secondary] = 1; @@ -501,10 +477,8 @@
void *mptable_finalize(struct mp_config_table *mc) { - mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), - mc->mpe_length); + mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length); - printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n", - mc, smp_next_mpe_entry(mc)); + printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n", mc, smp_next_mpe_entry(mc)); return smp_next_mpe_entry(mc); } diff --git a/src/arch/x86/null_breakpoint.c b/src/arch/x86/null_breakpoint.c index 43e3727..bb2029d 100644 --- a/src/arch/x86/null_breakpoint.c +++ b/src/arch/x86/null_breakpoint.c @@ -44,7 +44,8 @@ enum breakpoint_result res = breakpoint_create_instruction(&null_fetch_bp, NULL);
if (res != BREAKPOINT_RES_OK) { - printk(BIOS_ERR, "Failed to create address zero instruction fetch breakpoint\n"); + printk(BIOS_ERR, + "Failed to create address zero instruction fetch breakpoint\n"); return; }
diff --git a/src/arch/x86/pirq_routing.c b/src/arch/x86/pirq_routing.c index 7244536..6aa6b23 100644 --- a/src/arch/x86/pirq_routing.c +++ b/src/arch/x86/pirq_routing.c @@ -16,30 +16,26 @@ printk(BIOS_INFO, "Checking Interrupt Routing Table consistency...\n");
if (sizeof(struct irq_routing_table) != rt->size) { - printk(BIOS_WARNING, - "Inconsistent Interrupt Routing Table size (0x%x/0x%x).\n", - (unsigned int)sizeof(struct irq_routing_table), - rt->size); + printk(BIOS_WARNING, "Inconsistent Interrupt Routing Table size (0x%x/0x%x).\n", + (unsigned int)sizeof(struct irq_routing_table), rt->size); rt->size = sizeof(struct irq_routing_table); }
for (i = 0; i < rt->size; i++) sum += addr[i];
- printk(BIOS_DEBUG, "%s(): Interrupt Routing Table located at %p.\n", - __func__, addr); + printk(BIOS_DEBUG, "%s(): Interrupt Routing Table located at %p.\n", __func__, addr);
sum = rt->checksum - sum;
if (sum != rt->checksum) { printk(BIOS_WARNING, - "Interrupt Routing Table checksum is: 0x%02x but should be: 0x%02x.\n", - rt->checksum, sum); + "Interrupt Routing Table checksum is: 0x%02x but should be: 0x%02x.\n", + rt->checksum, sum); rt->checksum = sum; }
- if (rt->signature != PIRQ_SIGNATURE || rt->version != PIRQ_VERSION || - rt->size % 16) { + if (rt->signature != PIRQ_SIGNATURE || rt->version != PIRQ_VERSION || rt->size % 16) { printk(BIOS_WARNING, "Interrupt Routing Table not valid.\n"); return; } @@ -54,23 +50,21 @@ */ if (sum) { printk(BIOS_WARNING, "Checksum error in Interrupt Routing Table " - "could not be fixed.\n"); + "could not be fixed.\n"); }
printk(BIOS_INFO, "done.\n"); }
static enum cb_err verify_copy_pirq_routing_table(unsigned long addr, - const struct irq_routing_table *routing_table) + const struct irq_routing_table *routing_table) { int i; uint8_t *rt_orig, *rt_curr;
rt_curr = (uint8_t *)addr; rt_orig = (uint8_t *)routing_table; - printk(BIOS_INFO, - "Verifying copy of Interrupt Routing Table at 0x%08lx... ", - addr); + printk(BIOS_INFO, "Verifying copy of Interrupt Routing Table at 0x%08lx... ", addr); for (i = 0; i < routing_table->size; i++) { if (*(rt_curr + i) != *(rt_orig + i)) { printk(BIOS_INFO, "failed\n"); @@ -125,24 +119,21 @@
/* Set PCI IRQs. */ for (i = 0; i < num_entries; i++) { - u8 bus = pirq_tbl->slots[i].bus; u8 devfn = pirq_tbl->slots[i].devfn;
- printk(BIOS_DEBUG, "PIRQ Entry %d Dev/Fn: %X Slot: %d\n", i, - devfn >> 3, pirq_tbl->slots[i].slot); + printk(BIOS_DEBUG, "PIRQ Entry %d Dev/Fn: %X Slot: %d\n", i, devfn >> 3, + pirq_tbl->slots[i].slot);
for (intx = 0; intx < MAX_INTX_ENTRIES; intx++) { - int link = pirq_tbl->slots[i].irq[intx].link; int bitmap = pirq_tbl->slots[i].irq[intx].bitmap; int irq = 0;
- printk(BIOS_DEBUG, "INT: %c link: %x bitmap: %x ", - 'A' + intx, link, bitmap); + printk(BIOS_DEBUG, "INT: %c link: %x bitmap: %x ", 'A' + intx, link, + bitmap);
if (!bitmap || !link || link > CONFIG_MAX_PIRQ_LINKS) { - printk(BIOS_DEBUG, "not routed\n"); irq_slot[intx] = irq; continue; @@ -171,14 +162,13 @@ }
unsigned long copy_pirq_routing_table(unsigned long addr, - const struct irq_routing_table *routing_table) + const struct irq_routing_table *routing_table) { /* Align the table to be 16 byte aligned. */ addr = ALIGN_UP(addr, 16);
/* This table must be between 0xf0000 & 0x100000 */ - printk(BIOS_INFO, "Copying Interrupt Routing Table to 0x%08lx... ", - addr); + printk(BIOS_INFO, "Copying Interrupt Routing Table to 0x%08lx... ", addr); memcpy((void *)addr, routing_table, routing_table->size); printk(BIOS_INFO, "done.\n"); if (CONFIG(DEBUG_PIRQ)) diff --git a/src/arch/x86/postcar.c b/src/arch/x86/postcar.c index b07b512..6727430 100644 --- a/src/arch/x86/postcar.c +++ b/src/arch/x86/postcar.c @@ -12,7 +12,9 @@ * Systems without a native coreboot cache-as-ram teardown may implement * this to use an alternate method. */ -__weak void late_car_teardown(void) { /* do nothing */ } +__weak void late_car_teardown(void) +{ /* do nothing */ +}
void main(void) { diff --git a/src/arch/x86/postcar_loader.c b/src/arch/x86/postcar_loader.c index 5528e37..cd98f17 100644 --- a/src/arch/x86/postcar_loader.c +++ b/src/arch/x86/postcar_loader.c @@ -39,8 +39,7 @@ return CB_SUCCESS; }
-void postcar_frame_add_mtrr(struct postcar_frame *pcf, - uintptr_t addr, size_t size, int type) +void postcar_frame_add_mtrr(struct postcar_frame *pcf, uintptr_t addr, size_t size, int type) { var_mtrr_set(pcf->mtrr, addr, size, type); } @@ -100,8 +99,7 @@ };
if (rmodule_stage_load(&rsl)) - die_with_post_code(POSTCODE_INVALID_ROM, - "Failed to load after CAR program.\n"); + die_with_post_code(POSTCODE_INVALID_ROM, "Failed to load after CAR program.\n");
/* Set the stack pointer within parameters of the program loaded. */ if (rsl.params == NULL) @@ -126,8 +124,7 @@ size_t smm_size;
smm_region(&smm_base, &smm_size); - postcar_frame_add_mtrr(pcf, smm_base, smm_size, - MTRR_TYPE_WRBACK); + postcar_frame_add_mtrr(pcf, smm_base, smm_size, MTRR_TYPE_WRBACK); }
static void postcar_cache_invalid(void) @@ -157,8 +154,7 @@
static void run_postcar_phase(struct postcar_frame *pcf) { - struct prog prog = - PROG_INIT(PROG_POSTCAR, CONFIG_CBFS_PREFIX "/postcar"); + struct prog prog = PROG_INIT(PROG_POSTCAR, CONFIG_CBFS_PREFIX "/postcar");
vboot_run_logic();
diff --git a/src/arch/x86/rdrand.c b/src/arch/x86/rdrand.c index 31958db..d5a1c04 100644 --- a/src/arch/x86/rdrand.c +++ b/src/arch/x86/rdrand.c @@ -19,9 +19,8 @@ { uint8_t carry;
- __asm__ __volatile__( - ".byte 0x0f; .byte 0xc7; .byte 0xf0; setc %1" - : "=a" (*rand), "=qm" (carry)); + __asm__ __volatile__(".byte 0x0f; .byte 0xc7; .byte 0xf0; setc %1" + : "=a"(*rand), "=qm"(carry)); return carry; }
@@ -34,9 +33,8 @@ { uint8_t carry;
- __asm__ __volatile__( - ".byte 0x48; .byte 0x0f; .byte 0xc7; .byte 0xf0; setc %1" - : "=a" (*rand), "=qm" (carry)); + __asm__ __volatile__(".byte 0x48; .byte 0x0f; .byte 0xc7; .byte 0xf0; setc %1" + : "=a"(*rand), "=qm"(carry)); return carry; } #endif @@ -65,8 +63,7 @@ return CB_SUCCESS; #endif if (rdrand_32(&rand_high) && rdrand_32(&rand_low)) { - *rand = ((uint64_t)rand_high << 32) | - (uint64_t)rand_low; + *rand = ((uint64_t)rand_high << 32) | (uint64_t)rand_low; return CB_SUCCESS; } } diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index a2038b6..8e0e85d 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -115,8 +115,8 @@ if (cpu_have_cpuid()) res = cpuid(1);
- struct smbios_type4 *t = smbios_carve_table(*current, SMBIOS_PROCESSOR_INFORMATION, - sizeof(*t), handle); + struct smbios_type4 *t = + smbios_carve_table(*current, SMBIOS_PROCESSOR_INFORMATION, sizeof(*t), handle);
snprintf(buf, sizeof(buf), "CPU%d", cnt++); t->socket_designation = smbios_add_string(t->eos, buf); @@ -208,10 +208,8 @@ * @param max_struct_size Pointer to maximum struct size * @param type4 Pointer to SMBIOS type 4 structure */ -int smbios_write_type7_cache_parameters(unsigned long *current, - int *handle, - int *max_struct_size, - struct smbios_type4 *type4) +int smbios_write_type7_cache_parameters(unsigned long *current, int *handle, + int *max_struct_size, struct smbios_type4 *type4) { unsigned int cnt = CACHE_L1D; int len = 0; @@ -222,7 +220,7 @@ enum cpu_type dcache_cpuid = cpu_check_deterministic_cache_cpuid_supported(); if (dcache_cpuid == CPUID_TYPE_INVALID || dcache_cpuid == CPUID_COMMAND_UNSUPPORTED) { printk(BIOS_DEBUG, "SMBIOS: Unknown CPU or CPU doesn't support Deterministic " - "Cache CPUID leaf\n"); + "Cache CPUID leaf\n"); return len; }
@@ -265,9 +263,9 @@
const int h = (*handle)++;
- update_max(len, *max_struct_size, smbios_write_type7(current, h, - level, smbios_cache_sram_type(), associativity, - type, cache_size, cache_size)); + update_max(len, *max_struct_size, + smbios_write_type7(current, h, level, smbios_cache_sram_type(), + associativity, type, cache_size, cache_size));
if (type4) { switch (level) { diff --git a/src/arch/x86/tables.c b/src/arch/x86/tables.c index 2732638..e38901a 100644 --- a/src/arch/x86/tables.c +++ b/src/arch/x86/tables.c @@ -26,19 +26,16 @@ /* And add a high table version for those payloads that * want to live in the F segment */ - high_table_pointer = (unsigned long)cbmem_add(CBMEM_ID_PIRQ, - MAX_PIRQ_TABLE_SIZE); + high_table_pointer = (unsigned long)cbmem_add(CBMEM_ID_PIRQ, MAX_PIRQ_TABLE_SIZE); if (high_table_pointer) { unsigned long new_high_table_pointer; - new_high_table_pointer = - write_pirq_routing_table(high_table_pointer); + new_high_table_pointer = write_pirq_routing_table(high_table_pointer); // FIXME make pirq table code intelligent enough to know how // much space it's going to need. - if (new_high_table_pointer > (high_table_pointer - + MAX_PIRQ_TABLE_SIZE)) + if (new_high_table_pointer > (high_table_pointer + MAX_PIRQ_TABLE_SIZE)) printk(BIOS_ERR, "Increase PIRQ size.\n"); printk(BIOS_DEBUG, "PIRQ table: %ld bytes.\n", - new_high_table_pointer - high_table_pointer); + new_high_table_pointer - high_table_pointer); }
return rom_table_end; @@ -55,19 +52,17 @@ rom_table_end = write_smp_table(rom_table_end); rom_table_end = ALIGN_UP(rom_table_end, 1024);
- high_table_pointer = (unsigned long)cbmem_add(CBMEM_ID_MPTABLE, - MAX_MP_TABLE_SIZE); + high_table_pointer = (unsigned long)cbmem_add(CBMEM_ID_MPTABLE, MAX_MP_TABLE_SIZE); if (high_table_pointer) { unsigned long new_high_table_pointer; new_high_table_pointer = write_smp_table(high_table_pointer); // FIXME make mp table code intelligent enough to know how // much space it's going to need. - if (new_high_table_pointer > (high_table_pointer - + MAX_MP_TABLE_SIZE)) + if (new_high_table_pointer > (high_table_pointer + MAX_MP_TABLE_SIZE)) printk(BIOS_ERR, "Increase MP table size.\n");
printk(BIOS_DEBUG, "MP table: %ld bytes.\n", - new_high_table_pointer - high_table_pointer); + new_high_table_pointer - high_table_pointer); }
return rom_table_end; @@ -92,28 +87,25 @@ * coreboot table. This leaves us with 47KB for all of ACPI. Let's see * how far we get. */ - high_table_pointer = (unsigned long)cbmem_add(CBMEM_ID_ACPI, - max_acpi_size); + high_table_pointer = (unsigned long)cbmem_add(CBMEM_ID_ACPI, max_acpi_size); if (high_table_pointer) { unsigned long acpi_start = high_table_pointer; unsigned long new_high_table_pointer;
rom_table_end = ALIGN_UP(rom_table_end, 16); new_high_table_pointer = write_acpi_tables(high_table_pointer); - if (new_high_table_pointer > (high_table_pointer - + max_acpi_size)) { + if (new_high_table_pointer > (high_table_pointer + max_acpi_size)) { printk(BIOS_CRIT, "ACPI tables overflowed and corrupted CBMEM!\n"); printk(BIOS_ERR, "Increase config MAX_ACPI_TABLE_SIZE_KB!\n"); } printk(BIOS_DEBUG, "ACPI tables: %ld bytes.\n", - new_high_table_pointer - high_table_pointer); + new_high_table_pointer - high_table_pointer);
/* Now we need to create a low table copy of the RSDP. */
/* First we look for the high table RSDP */ while (acpi_start < new_high_table_pointer) { - if (memcmp(((acpi_rsdp_t *)acpi_start)->signature, - RSDP_SIG, 8) == 0) + if (memcmp(((acpi_rsdp_t *)acpi_start)->signature, RSDP_SIG, 8) == 0) break; acpi_start++; } @@ -146,8 +138,7 @@
#define MAX_SMBIOS_SIZE (32 * KiB)
- high_table_pointer = (unsigned long)cbmem_add(CBMEM_ID_SMBIOS, - MAX_SMBIOS_SIZE); + high_table_pointer = (unsigned long)cbmem_add(CBMEM_ID_SMBIOS, MAX_SMBIOS_SIZE); if (high_table_pointer) { unsigned long new_high_table_pointer;
@@ -158,24 +149,22 @@ */ memset((void *)high_table_pointer, 0, MAX_SMBIOS_SIZE);
- new_high_table_pointer = - smbios_write_tables(high_table_pointer); + new_high_table_pointer = smbios_write_tables(high_table_pointer); rom_table_end = ALIGN_UP(rom_table_end, 16); memcpy((void *)rom_table_end, (void *)high_table_pointer, - sizeof(struct smbios_entry)); + sizeof(struct smbios_entry)); rom_table_end += sizeof(struct smbios_entry);
- if (new_high_table_pointer > (high_table_pointer - + MAX_SMBIOS_SIZE)) + if (new_high_table_pointer > (high_table_pointer + MAX_SMBIOS_SIZE)) printk(BIOS_ERR, "Increase SMBIOS size\n"); printk(BIOS_DEBUG, "SMBIOS tables: %ld bytes.\n", - new_high_table_pointer - high_table_pointer); + new_high_table_pointer - high_table_pointer); } else { unsigned long new_rom_table_end;
new_rom_table_end = smbios_write_tables(rom_table_end); - printk(BIOS_DEBUG, "SMBIOS size %ld bytes\n", new_rom_table_end - - rom_table_end); + printk(BIOS_DEBUG, "SMBIOS size %ld bytes\n", + new_rom_table_end - rom_table_end); rom_table_end = ALIGN_UP(new_rom_table_end, 16); }
@@ -212,7 +201,7 @@
forwarding_table += sz; /* Align up to page boundary for historical consistency. */ - forwarding_table = ALIGN_UP(forwarding_table, 4*KiB); + forwarding_table = ALIGN_UP(forwarding_table, 4 * KiB);
/* Tell static analysis we know value is left unused. */ (void)rom_table_end; diff --git a/src/arch/x86/thread.c b/src/arch/x86/thread.c index fa60961..d062667 100644 --- a/src/arch/x86/thread.c +++ b/src/arch/x86/thread.c @@ -28,8 +28,7 @@ return cur_stack; }
-void arch_prepare_thread(struct thread *t, - asmlinkage void (*thread_entry)(void *), void *arg) +void arch_prepare_thread(struct thread *t, asmlinkage void (*thread_entry)(void *), void *arg) { uintptr_t stack = t->stack_current;