Leroy P Leahy (leroy.p.leahy@intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13445
-gerrit
commit f9f90d3527d12f8af59f994ab2f63581a0c3a049 Author: Lee Leahy leroy.p.leahy@intel.com Date: Sun Jan 24 18:51:58 2016 -0800
Quark/Galileo: Enable Serial Port
Add the code to enable debug serial output using HSUART1:
* Enable the code using Kconfig value ENABLE_BUILTIN_HSUART1 * Specify the portion of ESRAM to be used by romstage * Initialize the debug serial port * Note that the BIST value is always zero as validated in esram_init.inc * The initial TSC value is currently not saved! * Serial output indicates a successful test
BRANCH=none BUG=None TEST=None
Change-Id: I7e6181e8b9bc901c3ab236f0b56534850bb6bfd0 Signed-off-by: Lee Leahy leroy.p.leahy@intel.com --- src/mainboard/intel/galileo/Kconfig | 9 ++++ src/mainboard/intel/galileo/Makefile.inc | 4 ++ src/mainboard/intel/galileo/com_init.c | 32 +++++++++++++ src/soc/intel/quark/Kconfig | 30 ++++++++++++ src/soc/intel/quark/Makefile.inc | 4 ++ src/soc/intel/quark/include/soc/iomap.h | 31 +++++++++++++ src/soc/intel/quark/include/soc/pci_devs.h | 30 ++++++++++++ src/soc/intel/quark/include/soc/romstage.h | 33 +++++++++++++ src/soc/intel/quark/romstage/cache_as_ram.inc | 54 ++++++++++++++++++++- src/soc/intel/quark/tsc_freq.c | 40 ++++++++++++++++ src/soc/intel/quark/uart.c | 67 +++++++++++++++++++++++++++ 11 files changed, 332 insertions(+), 2 deletions(-)
diff --git a/src/mainboard/intel/galileo/Kconfig b/src/mainboard/intel/galileo/Kconfig index eeb7ab4..b21df00 100755 --- a/src/mainboard/intel/galileo/Kconfig +++ b/src/mainboard/intel/galileo/Kconfig @@ -3,10 +3,19 @@ if BOARD_INTEL_GALILEO config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_8192 + select ENABLE_BUILTIN_HSUART1 select HAVE_FSP_RAW_BIN select PLATFORM_USES_FSP1_1 select SOC_INTEL_QUARK
+config DCACHE_RAM_BASE + hex + default 0x80070000 + +config DCACHE_RAM_SIZE + hex + default 0x00008000 + config HAVE_FSP_RAW_BIN bool "Should the Intel FSP binary be added to the flash image" help diff --git a/src/mainboard/intel/galileo/Makefile.inc b/src/mainboard/intel/galileo/Makefile.inc index 7a1603e..d6c5e52 100755 --- a/src/mainboard/intel/galileo/Makefile.inc +++ b/src/mainboard/intel/galileo/Makefile.inc @@ -18,6 +18,10 @@ ## Foundation, Inc. ##
+romstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += com_init.c + +ramstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += com_init.c + # Add the FSP binary to the cbfs image ifeq ($(CONFIG_HAVE_FSP_RAW_BIN),y) cbfs-files-y += fsp.bin diff --git a/src/mainboard/intel/galileo/com_init.c b/src/mainboard/intel/galileo/com_init.c new file mode 100644 index 0000000..da50cfd --- /dev/null +++ b/src/mainboard/intel/galileo/com_init.c @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015-2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <fsp/car.h> +#include <device/pci.h> +#include <soc/iomap.h> +#include <soc/pci_devs.h> + +#if ENV_ROMSTAGE + +void car_mainboard_pre_console_init(void) +{ + pci_early_device_probe(0, HSUART1_DEV, UART_BASE_ADDRESS); +} +#endif /* ENV_ROMSTAGE */ diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig index 197eb59..7b0cde1 100644 --- a/src/soc/intel/quark/Kconfig +++ b/src/soc/intel/quark/Kconfig @@ -11,6 +11,9 @@ config CPU_SPECIFIC_OPTIONS select ARCH_RAMSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_VERSTAGE_X86_32 + select SOC_INTEL_COMMON + select TSC_CONSTANT_RATE + select UDELAY_TSC
config CBFS_SIZE hex @@ -56,6 +59,14 @@ config ENABLE_DEBUG_LED_TEMPRAMINIT help Indicate that TempRamInit was successful.
+config ENABLE_BUILTIN_HSUART1 + bool "Enable built-in HSUART1" + default n + help + The Quark SoC has two HSUART. Choose this option to + configure the pads and enable HSUART1, which can be used for + the debug console. + config RMU_FILE string default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/rmu.bin" @@ -69,4 +80,23 @@ config RMU_LOC The location in CBFS that the RMU is located. It must match the strap-determined base address.
+if ENABLE_BUILTIN_HSUART1 +config INTEL_UART_SPECIFIC_OPTIONS + def_bool y + select NO_UART_ON_SUPERIO + select DRIVERS_UART_8250MEM_32 + +config TTYS0_BASE + hex "HSUART1 Base Address" + depends on ENABLE_BUILTIN_HSUART1 + default 0xA0019000 + help + Memory mapped MMIO of HSUART1. + +config TTYS0_LCS + int + depends on ENABLE_BUILTIN_HSUART1 + default 3 + +endif # ENABLE_BUILTIN_HSUART1 endif # SOC_INTEL_QUARK diff --git a/src/soc/intel/quark/Makefile.inc b/src/soc/intel/quark/Makefile.inc index 39ad8af..bec1595 100644 --- a/src/soc/intel/quark/Makefile.inc +++ b/src/soc/intel/quark/Makefile.inc @@ -21,8 +21,12 @@ subdirs-y += romstage subdirs-y += ../../../cpu/x86/tsc
romstage-y += memmap.c +romstage-y += tsc_freq.c +romstage-y += uart.c
ramstage-y += memmap.c +ramstage-y += tsc_freq.c +ramstage-y += uart.c
CPPFLAGS_common += -I$(src)/soc/intel/quark/include CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp1_1/quark diff --git a/src/soc/intel/quark/include/soc/iomap.h b/src/soc/intel/quark/include/soc/iomap.h new file mode 100644 index 0000000..b6a7392 --- /dev/null +++ b/src/soc/intel/quark/include/soc/iomap.h @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015-2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _QUARK_IOMAP_H_ +#define _QUARK_IOMAP_H_ + +/* + * Memory Mapped IO base addresses. + */ + +/* UART MMIO */ +#define UART_BASE_ADDRESS CONFIG_TTYS0_BASE + +#endif /* _QUARK_IOMAP_H_ */ diff --git a/src/soc/intel/quark/include/soc/pci_devs.h b/src/soc/intel/quark/include/soc/pci_devs.h new file mode 100644 index 0000000..d022c66 --- /dev/null +++ b/src/soc/intel/quark/include/soc/pci_devs.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2013 Sage Electronic Engineering, LLC. + * Copyright (C) 2015-2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _QUARK_PCI_DEVS_H_ +#define _QUARK_PCI_DEVS_H_ + +/* IO Fabric 1 */ +#define SIO1_DEV 0x14 +# define HSUART1_DEV SIO1_DEV +# define HSUART1_FUNC 5 + +#endif /* _QUARK_PCI_DEVS_H_ */ diff --git a/src/soc/intel/quark/include/soc/romstage.h b/src/soc/intel/quark/include/soc/romstage.h new file mode 100644 index 0000000..8a80cd9 --- /dev/null +++ b/src/soc/intel/quark/include/soc/romstage.h @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2014 Sage Electronic Engineering, LLC. + * Copyright (C) 2015-2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _QUARK_ROMSTAGE_H_ +#define _QUARK_ROMSTAGE_H_ + +#if !defined(__PRE_RAM__) +#error "Don't include romstage.h from a ramstage compilation unit!" +#endif + +#include <fsp/util.h> + +int pci_early_device_func_probe(u8 bus, u8 dev, u8 func, u32 mmio_base); + +#endif /* _QUARK_ROMSTAGE_H_ */ diff --git a/src/soc/intel/quark/romstage/cache_as_ram.inc b/src/soc/intel/quark/romstage/cache_as_ram.inc index 80ac64d..89e6f88 100644 --- a/src/soc/intel/quark/romstage/cache_as_ram.inc +++ b/src/soc/intel/quark/romstage/cache_as_ram.inc @@ -112,8 +112,58 @@ CAR_init_done: movl %esi, %edx #endif /* CONFIG_ENABLE_DEBUG_LED_TEMPRAMINIT */
- clrl %eax - jmp halt2 + /* Setup bootloader stack */ + movl %edx, %esp + + /* + * eax: 0 + * ebp: FSP_INFO_HEADER address + * ecx: Temp RAM base + * edx: Temp RAM top + * edi: BIST value + * esp: Top of stack in temp RAM + */ + + /* Create cache_as_ram_params on stack */ + pushl %edx /* bootloader CAR end */ + pushl %ecx /* bootloader CAR begin */ + pushl %ebp /* FSP_INFO_HEADER */ + pushl %edi /* bist */ +// movd %mm1, %eax + pushl %eax /* tsc[63:32] */ +// movd %mm0, %eax + pushl %eax /* tsc[31:0] */ + pushl %esp /* pointer to cache_as_ram_params */ + + /* Save FSP_INFO_HEADER location in ebx */ + mov %ebp, %ebx + + /* Coreboot assumes stack/heap region will be zero */ + cld + movl %ecx, %edi + neg %ecx + /* Only clear up to current stack value. */ + add %esp, %ecx + shrl $2, %ecx + xorl %eax, %eax + rep stosl + +before_romstage: + post_code(0x23) + + /* Call cache_as_ram_main(struct cache_as_ram_params *) */ + call cache_as_ram_main + movb $0xB8, %ah + jmp .Lhlt + +/* One will never return from cache_as_ram_main() in verstage so there's + * no such thing as after ram init. */ +#if !ENV_VERSTAGE +#include "src/drivers/intel/fsp1_1/after_raminit.S" +#endif + + movb $0x69, %ah + jmp .Lhlt
halt1: /* diff --git a/src/soc/intel/quark/tsc_freq.c b/src/soc/intel/quark/tsc_freq.c new file mode 100644 index 0000000..eef682a --- /dev/null +++ b/src/soc/intel/quark/tsc_freq.c @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/tsc.h> + +static unsigned long bus_freq_khz(void) +{ + /* cpu freq = 400 MHz */ + return 400 * 1000; +} + +unsigned long tsc_freq_mhz(void) +{ + /* assume ratio=1 */ + unsigned bclk_khz = bus_freq_khz(); + + if (!bclk_khz) + return 0; + + return (bclk_khz * 1) / 1000; +} diff --git a/src/soc/intel/quark/uart.c b/src/soc/intel/quark/uart.c new file mode 100644 index 0000000..2d39d1b --- /dev/null +++ b/src/soc/intel/quark/uart.c @@ -0,0 +1,67 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2003 Eric Biederman + * Copyright (C) 2006-2010 coresystems GmbH + * Copyright (C) 2015-2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +// Use simple device model for this file even in ramstage +#define __SIMPLE_DEVICE__ + +#include <console/uart.h> +#include <device/pci.h> +#include <device/pci_def.h> +#include <soc/pci_devs.h> + +#ifdef __PRE_RAM__ +int pci_early_device_probe(u8 bus, u8 dev, u32 mmio_base) +{ + uint16_t reg16; + + /* HSUART controller #1 (B0:D20:F5). */ + device_t uart_dev = PCI_DEV(bus, dev, HSUART1_FUNC); + + /* Decode BAR0(offset 0x10). */ + pci_write_config32(uart_dev, PCI_BASE_ADDRESS_0, mmio_base); + + /* Enable MEMBASE at CMD(offset 0x04). */ + reg16 = pci_read_config16(uart_dev, PCI_COMMAND); + reg16 |= PCI_COMMAND_MEMORY; + pci_write_config16(uart_dev, PCI_COMMAND, reg16); + + return 0; +} +#endif + +unsigned int uart_platform_refclk(void) +{ + return 44236800; +} + +uintptr_t uart_platform_base(int idx) +{ + if (idx < 6) { + /* HSUART controller #1 (B0:D20:F5). */ + device_t dev = PCI_DEV(0, HSUART1_DEV, HSUART1_FUNC); + + /* UART base address at BAR0(offset 0x10). */ + return (unsigned int) (pci_read_config32(dev, PCI_BASE_ADDRESS_0) & ~0xfff); + } + else { + return 0; + } +}