Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37303 )
Change subject: soc/intel/broadwell_de: Re-read SPD on CRC error ......................................................................
Patch Set 2:
(3 comments)
https://review.coreboot.org/c/coreboot/+/37303/2/src/soc/intel/fsp_broadwell... File src/soc/intel/fsp_broadwell_de/romstage/memory.c:
https://review.coreboot.org/c/coreboot/+/37303/2/src/soc/intel/fsp_broadwell... PS2, Line 68: "SPD CRC error, channel %u slot %u\n", Please add the iteration.
https://review.coreboot.org/c/coreboot/+/37303/2/src/soc/intel/fsp_broadwell... PS2, Line 72: } while (tries-- && res == SPD_STATUS_CRC_ERROR); How much time does each try add to the boot time? Could you time it using the stopwatch frame work and add that, if it’s more than 1 ms?
https://review.coreboot.org/c/coreboot/+/37303/2/src/soc/intel/fsp_broadwell... PS2, Line 76: } Please print an error with error string, stating that the SMBIOS data is not added, but it should still work.