Jamie Ryu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43790 )
Change subject: mb/google/volteer: fmd update for CSE Lite Firmware Update ......................................................................
mb/google/volteer: fmd update for CSE Lite Firmware Update
Updated fmd to include CSE Lite RW partition binary to FW_MAIN_A and FW_MAIN_B for CSE Lite firmware update.
BUG=b:140448618 TEST=build with me_rw binary blob for volteer and boot to kernel.
Signed-off-by: Jamie Ryu jamie.m.ryu@intel.com Change-Id: Ie3c2b657f0426d206dfe3729829ec34ff57812c7 --- M src/mainboard/google/volteer/chromeos.fmd 1 file changed, 7 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/43790/1
diff --git a/src/mainboard/google/volteer/chromeos.fmd b/src/mainboard/google/volteer/chromeos.fmd index 60ea3de..07a5464 100644 --- a/src/mainboard/google/volteer/chromeos.fmd +++ b/src/mainboard/google/volteer/chromeos.fmd @@ -7,16 +7,16 @@ # Place RW_LEGACY at the start of BIOS region such that the rest # of BIOS regions start at 16MiB boundary. Since this is a 32MiB # SPI flash only the top 16MiB actually gets memory mapped. - RW_LEGACY(CBFS)@0x0 0xf00000 - RW_SECTION_A@0xf00000 0x3e0000 { + RW_LEGACY(CBFS)@0x0 0xb00000 + RW_SECTION_A@0xb00000 0x5e0000 { VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x3cffc0 - RW_FWID_A@0x3dffc0 0x40 + FW_MAIN_A(CBFS)@0x10000 0x5cffc0 + RW_FWID_A@0x5dffc0 0x40 } - RW_SECTION_B@0x12e0000 0x3e0000 { + RW_SECTION_B@0x10e0000 0x5e0000 { VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x3cffc0 - RW_FWID_B@0x3dffc0 0x40 + FW_MAIN_B(CBFS)@0x10000 0x5cffc0 + RW_FWID_B@0x5dffc0 0x40 } RW_MISC@0x16c0000 0x40000 { UNIFIED_MRC_CACHE(PRESERVE)@0x0 0x30000 {