Attention is currently required from: Dinesh Gehlot, Eric Lai, Kapil Porwal, Nick Vaccaro, Paul Menzel, Shou-Chieh Hsu, Subrata Banik.
Roger Wang has posted comments on this change by Roger Wang. ( https://review.coreboot.org/c/coreboot/+/82602?usp=email )
Change subject: mb/google/nissa/var/sundance: Tune eMMC DLL delays to support more devices ......................................................................
Patch Set 18:
(7 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/82602/comment/5d641057_1a0656fa?usp... : PS12, Line 2: Author: roger2.wang roger2.wang@lcfc.corp-partner.google.com
Same comment as in https://review.coreboot.org/c/coreboot/+/82427.
Done
https://review.coreboot.org/c/coreboot/+/82602/comment/e996a5cf_590413af?usp... : PS12, Line 7: Adjust the eMMC DLL delay setting according to Intel's suggestion
That’s quite long. Maybe: […]
Done
https://review.coreboot.org/c/coreboot/+/82602/comment/e36cc4e6_fad31ae6?usp... : PS12, Line 9: Use the Intel provides eMMC DLL delay patch to modify some system can't boot to OS problem
Please add a dot/period at the end of sentences. […]
Done
https://review.coreboot.org/c/coreboot/+/82602/comment/d4b5c732_8093f82e?usp... : PS12, Line 9: Currently some eMMC can't power on to OS nomally.
Please list the problematic eMMC models.
Done
File src/mainboard/google/brya/variants/sundance/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/82602/comment/a55bbdf4_6b798219?usp... : PS12, Line 10: register "sagv" = "SaGv_Enabled"
Please remove the leading space.
Done
https://review.coreboot.org/c/coreboot/+/82602/comment/47341b6a_bec527ea?usp... : PS12, Line 53: 1(HS400 Mode)
Add add space before the (.
Done
https://review.coreboot.org/c/coreboot/+/82602/comment/038468e3_9436fd12?usp... : PS12, Line 12: # EMMC Tx CMD Delay : # Refer to EDS-Vol2-42.3.7. : # [14:8] steps of delay for DDR mode, each 125ps, range: 0 - 39. : # [6:0] steps of delay for SDR mode, each 125ps, range: 0 - 39. : register "common_soc_config.emmc_dll.emmc_tx_cmd_cntl" = "0x505" : : # EMMC TX DATA Delay 1 : # Refer to EDS-Vol2-42.3.8. : # [14:8] steps of delay for HS400, each 125ps, range: 0 - 78. : # [6:0] steps of delay for SDR104/HS200, each 125ps, range: 0 - 79. : register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x909" : : # EMMC TX DATA Delay 2 : # Refer to EDS-Vol2-42.3.9. : # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 79. : # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. : # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 -79. : # [6:0] steps of delay for SDR12, each 125ps. Range: 0 - 79. : register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C2A2828" : : # EMMC RX CMD/DATA Delay 1 : # Refer to EDS-Vol2-42.3.10. : # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 119. : # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. : # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119. : # [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119. : register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C1B1A1B" : : # EMMC RX CMD/DATA Delay 2 : # Refer to EDS-Vol2-42.3.12. : # [17:16] stands for Rx Clock before Output Buffer, : # 00: Rx clock after output buffer, : # 01: Rx clock before output buffer, : # 10: Automatic selection based on working mode. : # 11: Reserved : # [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39. : # [6:0] steps of delay for HS200, each 125ps, range: 0 - 79. : register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x10028" : : # EMMC Rx Strobe Delay : # Refer to EDS-Vol2-42.3.11. : # [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps, range: 0 - 39. : # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39. : register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x11515"
Please remove the leading space before the tab. […]
Done