Hello Chris Wang,
I'd like you to do a code review. Please visit
https://review.coreboot.org/22613
to review the following change.
Change subject: google/Nauilus: add synaptics touch screen support ......................................................................
google/Nauilus: add synaptics touch screen support
1.change the GPP_C22 GPIO setting to enable touchscreen.
2.add synaptics touchscreen in the device tree so that the correct ACPI device is created.
BUG=b:66462881 BRANCH=master TEST=compiled/verified.
Change-Id: I6e89a5db0e9f8ae777eed661f3bf89d653a937e6 Signed-off-by: Chris Wang chriswang@ami.corp-partner.google.com --- M src/mainboard/google/poppy/variants/nautilus/devicetree.cb M src/mainboard/google/poppy/variants/nautilus/gpio.c 2 files changed, 11 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/22613/1
diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb index efaea3f..5e3db21 100644 --- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb @@ -231,7 +231,16 @@ device pci 14.0 on end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) device pci 14.2 on end # Thermal Subsystem - device pci 15.0 on end # I2C #0 + device pci 15.0 on + chip drivers/i2c/hid + register "generic.hid" = ""SYTS7813"" + register "generic.desc" = ""Synaptics Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 20 on end + end + end # I2C #0 device pci 15.1 on chip drivers/i2c/tpm register "hid" = ""GOOG0005"" diff --git a/src/mainboard/google/poppy/variants/nautilus/gpio.c b/src/mainboard/google/poppy/variants/nautilus/gpio.c index 51d3b77..cd384ec 100644 --- a/src/mainboard/google/poppy/variants/nautilus/gpio.c +++ b/src/mainboard/google/poppy/variants/nautilus/gpio.c @@ -156,7 +156,7 @@ /* C21 : UART2_TXD ==> CHP3_TX_SERVO_RX_UART */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* C22 : UART2_RTS# ==> CHP3_P3.3V_DX_TSP_EN */ - PAD_CFG_GPO(GPP_C22, 0, DEEP), + PAD_CFG_GPO(GPP_C22, 1, DEEP), /* C23 : UART2_CTS# ==> CHP3_PCH_WP*/ PAD_CFG_GPI(GPP_C23, 20K_PU, DEEP),