Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/33941
to look at the new patch set (#2).
Change subject: src/soc/intel/cannonlake: Fix PMC and GPIO block values for PCH-H ......................................................................
src/soc/intel/cannonlake: Fix PMC and GPIO block values for PCH-H
In order for GPEs to work properly, a number of the values used for GPIO_CFG and MISCCFG were not correct. This adjusts them in order to have GPE_EN set correctly, and thus enable GPEs, on the following GPIO blocks of PCH-H:
GPP_E GPP_F GPP_H GPP_I GPP_J GPP_K GPD
This was tested on a System76 Gazelle (gaze14). The EC uses GPP_K3 for its GPE and GPP_K6 is used for the lid switch GPE. Both function correctly after applying this change.
Change-Id: I4ecc9552468037598ef5d4e10122d660dcbfe71d Signed-off-by: Jeremy Soller jeremy@system76.com --- M src/soc/intel/cannonlake/include/soc/gpio_soc_defs_cnp_h.h M src/soc/intel/cannonlake/include/soc/pmc.h 2 files changed, 14 insertions(+), 14 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/33941/2