[coreboot-gerrit] [S] Change in coreboot[main]: intelblocks/acpi/notrhbridge.asl: Reserve SBREG BAR

[Michał Żygowski (Code Review)]

Attention is currently required from: Arthur Heymans, Christian Walter, CoolStar, Eran Mitrani, Jakub Czapiga, Jeremy Soller, Johnny Lin, Kapil Porwal, Lean Sheng Tan, Martin L Roth, Matt DeVillier, Nick Vaccaro, Paul Menzel, Subrata Banik, Tarun, Tim Chu.

Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77445?usp=email )

Change subject: intelblocks/acpi/notrhbridge.asl: Reserve SBREG BAR
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Patch Set 15:

(1 comment)

File src/soc/intel/alderlake/include/soc/iomap.h:

https://review.coreboot.org/c/coreboot/+/77445/comment/c542eead_fd1cbc69 :
PS15, Line 127: (256 * MiB)
> Shouldn’t it be substituded by the preoprocessor?

The header containing MiB definition isn't probably included anywhere in the ASL.