Attention is currently required from: Kapil Porwal, Paul Menzel, Pranava Y N, Subrata Banik.
Sowmya Aralguppe has posted comments on this change by Sowmya Aralguppe. ( https://review.coreboot.org/c/coreboot/+/85531?usp=email )
Change subject: soc/intel/pantherlake: Decrease CRASHLOG_NODES_COUNT to 1 ......................................................................
Patch Set 7:
(1 comment)
Patchset:
PS6:
if I remember correctly then you were trying to enable crashlog for all notes (total 5) but now you […]
There are only 3 dielets in LNL/PTL on base Die 1) GT die - self contained has its own storage - collected by PUNIT. 2) Compute Die 3) PCD die Hence we only have Compute Die in LNL/PTL unlike MTL which had different SRAM's for different Dielets. If we iterate more than what is programmed in the header by BIOS - crashlog decoding will have error .hence wanted to limit it to 1
More Details - taken from LNL FAS 15.3.2 LNL Dis-aggregation CrashLog
LNL is considered as a "self-contained" compared to MTL's disaggregated Crashlog dielets architecture. The fundamental difference is that MTL's Crashlog as a disaggregated package where the CPU and PCH are combined is full system from system perspective that is implemented on a different dielets. Each die controls its SRAM without impacting SOC die as well as PM Support. LNL is unified and only the Graphics part i.e. GCD-die considered as a "self-contained" disaggregated element. In general CCF and Atom modules on the Compute die and the uncore and PCH on the SOC die. Given the long term direction of dielets changing and potentially the SOC die to be re-used, crashlog storage will also be disaggregated per dielet. The PUnit will be the master Crashlog unit for the SOC-North and dielets and PMC will continue to be the SOC-south (PCH) crashlog unit.
15.3.3 Crashlog Storage For LNL 24KB needed for Crashlog in SRAM on the Punit. GCD uses its own storage on the Compute die. To recall, in MTL the Telemetry and Crashlog contents being split on a separate SRAMs to allow the crashlog SRAM to survive global reset. That was wired by Crashlog SRAM being on the VNNAON rail. However, for LNL they are expected to be in the same memory space.