Richard Spiegel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34561 )
Change subject: Documentation/soc/amd: Add Family 15h ......................................................................
Patch Set 6:
(5 comments)
https://review.coreboot.org/c/coreboot/+/34561/5//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/34561/5//COMMIT_MSG@7 PS5, Line 7: f
Will do.
Done
https://review.coreboot.org/c/coreboot/+/34561/5//COMMIT_MSG@9 PS5, Line 9: Create documentation for AMD family 15h, and in particular to models for
It is incorrect to imply there is no coreboot code for the models I mentioned above, which is what " […]
Done
https://review.coreboot.org/c/coreboot/+/34561/5/Documentation/soc/amd/famil... File Documentation/soc/amd/family15h.md:
https://review.coreboot.org/c/coreboot/+/34561/5/Documentation/soc/amd/famil... PS5, Line 29: the binary PI release
If you expect them to understand you, then yes.
Done
https://review.coreboot.org/c/coreboot/+/34561/5/Documentation/soc/amd/famil... PS5, Line 34: >In particular,
I don't see much value in discussing what was migrated from AGESA to coreboot.
Ack
https://review.coreboot.org/c/coreboot/+/34561/6/Documentation/soc/amd/famil... File Documentation/soc/amd/family15h.md:
https://review.coreboot.org/c/coreboot/+/34561/6/Documentation/soc/amd/famil... PS6, Line 40: ## Introduction : : Family 15h [SOC|Processors] products are x86-based designs. : : AMD has historically required an NDA for access to the PSP specification. : coreboot relies on util/amdfwtool to build the structures and add various : other firmware to the final image. : : Support in coreboot for modern AMD products is based on AMD’s : reference code: AMD Generic Encapsulated Software Architecture : (_AGESA ™_). _AGESA_ contains the technology for enabling DRAM, : configuring proprietary core logic, assistance with generating ACPI : tables, and other features. : : In the binary PI release used by coreboo, some functionality, such as the : setting of MTRRS and GPIO configurations along with setting of D0/D3 of : some devices (such as I2C and UART) were removed from _AGESA_ and converted : to coreboot code for granularity, speed and easy of use. : : >In particular, coreboot's approach to GPIO achieved a greater control : >over what is being programmed through the use of a table that is easily : >created using well defined macros. : Should have been removed! Will be on next patch.