5 comments:
Will do.
Done
Patch Set #5, Line 9: Create documentation for AMD family 15h, and in particular to models for
It is incorrect to imply there is no coreboot code for the models I mentioned above, which is what " […]
Done
File Documentation/soc/amd/family15h.md:
Patch Set #5, Line 29: the binary PI release
If you expect them to understand you, then yes.
Done
Patch Set #5, Line 34: >In particular,
I don't see much value in discussing what was migrated from AGESA to coreboot.
Ack
File Documentation/soc/amd/family15h.md:
## Introduction
Family 15h [SOC|Processors] products are x86-based designs.
AMD has historically required an NDA for access to the PSP specification.
coreboot relies on util/amdfwtool to build the structures and add various
other firmware to the final image.
Support in coreboot for modern AMD products is based on AMD’s
reference code: AMD Generic Encapsulated Software Architecture
(_AGESA ™_). _AGESA_ contains the technology for enabling DRAM,
configuring proprietary core logic, assistance with generating ACPI
tables, and other features.
In the binary PI release used by coreboo, some functionality, such as the
setting of MTRRS and GPIO configurations along with setting of D0/D3 of
some devices (such as I2C and UART) were removed from _AGESA_ and converted
to coreboot code for granularity, speed and easy of use.
>In particular, coreboot's approach to GPIO achieved a greater control
>over what is being programmed through the use of a table that is easily
>created using well defined macros.
Should have been removed! Will be on next patch.
To view, visit change 34561. To unsubscribe, or for help writing mail filters, visit settings.