Kyösti Mälkki (kyosti.malkki@gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7164
-gerrit
commit 1b71f3d76cd948c6e5aadf1417c7c4f75980a649 Author: Kyösti Mälkki kyosti.malkki@gmail.com Date: Sat Oct 18 08:51:01 2014 +0300
AGESA boards: Drop excessive boot_cpu() use
With AGESA, AP CPUs do not enter cache_as_ram_main().
Change-Id: If2a755f62ed6c3ab03eb0852d1ce2fe36b9951ce Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- src/mainboard/amd/dinar/romstage.c | 10 +++------- src/mainboard/amd/inagua/romstage.c | 4 +--- src/mainboard/amd/olivehill/romstage.c | 4 +--- src/mainboard/amd/parmer/romstage.c | 4 +--- src/mainboard/amd/persimmon/romstage.c | 4 +--- src/mainboard/amd/south_station/romstage.c | 4 +--- src/mainboard/amd/thatcher/romstage.c | 4 +--- src/mainboard/amd/torpedo/romstage.c | 4 +--- src/mainboard/amd/union_station/romstage.c | 4 +--- src/mainboard/asrock/e350m1/romstage.c | 4 +--- src/mainboard/asrock/imb-a180/romstage.c | 4 +--- src/mainboard/asus/f2a85-m/romstage.c | 3 +-- src/mainboard/gizmosphere/gizmo/romstage.c | 3 +-- src/mainboard/hp/pavilion_m6_1035dx/romstage.c | 3 +-- src/mainboard/jetway/nf81-t56n-lf/romstage.c | 3 +-- src/mainboard/lippert/frontrunner-af/romstage.c | 4 +--- src/mainboard/lippert/toucan-af/romstage.c | 4 +--- src/mainboard/supermicro/h8qgi/romstage.c | 3 +-- src/mainboard/supermicro/h8scm/romstage.c | 3 +-- src/mainboard/tyan/s8226/romstage.c | 3 +-- 20 files changed, 22 insertions(+), 57 deletions(-)
diff --git a/src/mainboard/amd/dinar/romstage.c b/src/mainboard/amd/dinar/romstage.c index 7fc8b60..804d72e 100644 --- a/src/mainboard/amd/dinar/romstage.c +++ b/src/mainboard/amd/dinar/romstage.c @@ -25,7 +25,6 @@ #include <arch/cpu.h> #include <arch/stages.h> #include <device/pnp_def.h> -#include <cpu/x86/lapic.h> #include <console/console.h> #include <console/loglevel.h> #include "cpu/amd/car.h" @@ -34,7 +33,6 @@ #include "cpu/x86/bist.h" #include <superio/smsc/sch4037/sch4037.h> #include <superio/smsc/sio1036/sio1036.h> -#include "cpu/x86/lapic.h" #include "nb_cimx.h" #include <sb_cimx.h>
@@ -46,7 +44,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
AGESAWRAPPER_PRE_CONSOLE(amdinitmmio);
- if (!cpu_init_detectedx && boot_cpu()) { + if (!cpu_init_detectedx) {
post_code(0x30);
@@ -74,10 +72,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
- if(boot_cpu()) { - post_code(0x34); - sb_Poweron_Init(); - } + post_code(0x34); + sb_Poweron_Init();
post_code(0x35); AGESAWRAPPER(amdinitreset); diff --git a/src/mainboard/amd/inagua/romstage.c b/src/mainboard/amd/inagua/romstage.c index 7e15036..a576a5e 100644 --- a/src/mainboard/amd/inagua/romstage.c +++ b/src/mainboard/amd/inagua/romstage.c @@ -26,7 +26,6 @@ #include <arch/stages.h> #include <device/pnp_def.h> #include <arch/cpu.h> -#include <cpu/x86/lapic.h> #include <console/console.h> #include <console/loglevel.h> #include <cpu/x86/mtrr.h> @@ -35,7 +34,6 @@ #include <northbridge/amd/agesa/agesawrapper_call.h> #include "cpu/x86/bist.h" #include <superio/smsc/kbc1100/kbc1100.h> -#include "cpu/x86/lapic.h" #include <sb_cimx.h> #include "SBPLATFORM.h"
@@ -57,7 +55,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
AGESAWRAPPER_PRE_CONSOLE(amdinitmmio);
- if (!cpu_init_detectedx && boot_cpu()) { + if (!cpu_init_detectedx) { post_code(0x30); sb_Poweron_Init();
diff --git a/src/mainboard/amd/olivehill/romstage.c b/src/mainboard/amd/olivehill/romstage.c index c1d0c13..9f02261 100644 --- a/src/mainboard/amd/olivehill/romstage.c +++ b/src/mainboard/amd/olivehill/romstage.c @@ -26,14 +26,12 @@ #include <arch/stages.h> #include <device/pnp_def.h> #include <arch/cpu.h> -#include <cpu/x86/lapic.h> #include <console/console.h> #include <console/loglevel.h> #include "cpu/amd/car.h" #include <northbridge/amd/agesa/agesawrapper.h> #include <northbridge/amd/agesa/agesawrapper_call.h> #include "cpu/x86/bist.h" -#include "cpu/x86/lapic.h" #include "southbridge/amd/agesa/hudson/hudson.h" #include "cpu/amd/agesa/s3_resume.h" #include "cbmem.h" @@ -55,7 +53,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
hudson_lpc_port80();
- if (!cpu_init_detectedx && boot_cpu()) { + if (!cpu_init_detectedx) { post_code(0x30);
post_code(0x31); diff --git a/src/mainboard/amd/parmer/romstage.c b/src/mainboard/amd/parmer/romstage.c index 71f07ea..b94f08c 100644 --- a/src/mainboard/amd/parmer/romstage.c +++ b/src/mainboard/amd/parmer/romstage.c @@ -26,14 +26,12 @@ #include <arch/stages.h> #include <device/pnp_def.h> #include <arch/cpu.h> -#include <cpu/x86/lapic.h> #include <console/console.h> #include <console/loglevel.h> #include "cpu/amd/car.h" #include <northbridge/amd/agesa/agesawrapper.h> #include <northbridge/amd/agesa/agesawrapper_call.h> #include "cpu/x86/bist.h" -#include "cpu/x86/lapic.h" #include "southbridge/amd/agesa/hudson/hudson.h" #include "cpu/amd/agesa/s3_resume.h" #include "cbmem.h" @@ -47,7 +45,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
hudson_lpc_port80();
- if (!cpu_init_detectedx && boot_cpu()) { + if (!cpu_init_detectedx) { post_code(0x30);
post_code(0x31); diff --git a/src/mainboard/amd/persimmon/romstage.c b/src/mainboard/amd/persimmon/romstage.c index 360ff8a..e0758ff 100644 --- a/src/mainboard/amd/persimmon/romstage.c +++ b/src/mainboard/amd/persimmon/romstage.c @@ -26,7 +26,6 @@ #include <arch/stages.h> #include <device/pnp_def.h> #include <arch/cpu.h> -#include <cpu/x86/lapic.h> #include <console/console.h> #include <console/loglevel.h> #include <cpu/x86/mtrr.h> @@ -36,7 +35,6 @@ #include "cpu/x86/bist.h" #include <superio/fintek/common/fintek.h> #include <superio/fintek/f81865f/f81865f.h> -#include "cpu/x86/lapic.h" #include <cpu/x86/cache.h> #include <sb_cimx.h> #include "SBPLATFORM.h" @@ -63,7 +61,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
AGESAWRAPPER_PRE_CONSOLE(amdinitmmio);
- if (!cpu_init_detectedx && boot_cpu()) { + if (!cpu_init_detectedx) { post_code(0x30); sb_Poweron_Init();
diff --git a/src/mainboard/amd/south_station/romstage.c b/src/mainboard/amd/south_station/romstage.c index 27c48eb..0eec780 100644 --- a/src/mainboard/amd/south_station/romstage.c +++ b/src/mainboard/amd/south_station/romstage.c @@ -26,7 +26,6 @@ #include <arch/stages.h> #include <device/pnp_def.h> #include <arch/cpu.h> -#include <cpu/x86/lapic.h> #include <console/console.h> #include <console/loglevel.h> #include <cpu/x86/mtrr.h> @@ -36,7 +35,6 @@ #include "cpu/x86/bist.h" #include <superio/fintek/common/fintek.h> #include <superio/fintek/f81865f/f81865f.h> -#include "cpu/x86/lapic.h" #include <sb_cimx.h> #include "SBPLATFORM.h"
@@ -58,7 +56,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
AGESAWRAPPER_PRE_CONSOLE(amdinitmmio);
- if (!cpu_init_detectedx && boot_cpu()) { + if (!cpu_init_detectedx) { post_code(0x30); sb_Poweron_Init();
diff --git a/src/mainboard/amd/thatcher/romstage.c b/src/mainboard/amd/thatcher/romstage.c index 11d5d14..5977140 100644 --- a/src/mainboard/amd/thatcher/romstage.c +++ b/src/mainboard/amd/thatcher/romstage.c @@ -26,14 +26,12 @@ #include <arch/stages.h> #include <device/pnp_def.h> #include <arch/cpu.h> -#include <cpu/x86/lapic.h> #include <console/console.h> #include <console/loglevel.h> #include "cpu/amd/car.h" #include <northbridge/amd/agesa/agesawrapper.h> #include <northbridge/amd/agesa/agesawrapper_call.h> #include "cpu/x86/bist.h" -#include "cpu/x86/lapic.h" #include "southbridge/amd/agesa/hudson/hudson.h" #include "src/superio/smsc/lpc47n217/early_serial.c" #include "cpu/amd/agesa/s3_resume.h" @@ -57,7 +55,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) byte |= 3; /* 2e, 2f */ pci_write_config8(dev, 0x48, byte);
- if (!cpu_init_detectedx && boot_cpu()) { + if (!cpu_init_detectedx) { post_code(0x30);
post_code(0x31); diff --git a/src/mainboard/amd/torpedo/romstage.c b/src/mainboard/amd/torpedo/romstage.c index 10d5fcf..6f8e7d4 100644 --- a/src/mainboard/amd/torpedo/romstage.c +++ b/src/mainboard/amd/torpedo/romstage.c @@ -24,7 +24,6 @@ #include <arch/io.h> #include <arch/stages.h> #include <device/pnp_def.h> -#include <cpu/x86/lapic.h> #include <console/console.h> #include <console/loglevel.h> #include "cpu/amd/car.h" @@ -32,7 +31,6 @@ #include <northbridge/amd/agesa/agesawrapper_call.h> #include "cpu/x86/bist.h" #include <superio/smsc/kbc1100/kbc1100.h> -#include "cpu/x86/lapic.h" #include "sb_cimx.h" #include "SbPlatform.h" #include <arch/cpu.h> @@ -47,7 +45,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x35); AGESAWRAPPER_PRE_CONSOLE(amdinitmmio);
- if (!cpu_init_detectedx && boot_cpu()) { + if (!cpu_init_detectedx) { post_code(0x30); gpioEarlyInit(); sb_poweron_init(); diff --git a/src/mainboard/amd/union_station/romstage.c b/src/mainboard/amd/union_station/romstage.c index 8618142..837face 100644 --- a/src/mainboard/amd/union_station/romstage.c +++ b/src/mainboard/amd/union_station/romstage.c @@ -26,7 +26,6 @@ #include <arch/stages.h> #include <device/pnp_def.h> #include <arch/cpu.h> -#include <cpu/x86/lapic.h> #include <console/console.h> #include <console/loglevel.h> #include <cpu/x86/mtrr.h> @@ -34,7 +33,6 @@ #include <northbridge/amd/agesa/agesawrapper.h> #include <northbridge/amd/agesa/agesawrapper_call.h> #include "cpu/x86/bist.h" -#include "cpu/x86/lapic.h" #include <sb_cimx.h> #include "SBPLATFORM.h"
@@ -53,7 +51,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
AGESAWRAPPER_PRE_CONSOLE(amdinitmmio);
- if (!cpu_init_detectedx && boot_cpu()) { + if (!cpu_init_detectedx) { post_code(0x30); sb_Poweron_Init();
diff --git a/src/mainboard/asrock/e350m1/romstage.c b/src/mainboard/asrock/e350m1/romstage.c index 4f6fd7f..b2c5cb9 100644 --- a/src/mainboard/asrock/e350m1/romstage.c +++ b/src/mainboard/asrock/e350m1/romstage.c @@ -25,7 +25,6 @@ #include <arch/stages.h> #include <device/pnp_def.h> #include <arch/cpu.h> -#include <cpu/x86/lapic.h> #include <console/console.h> #include <console/loglevel.h> #include <cpu/x86/mtrr.h> @@ -35,7 +34,6 @@ #include "cpu/x86/bist.h" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> -#include "cpu/x86/lapic.h" #include <sb_cimx.h> #include "SBPLATFORM.h"
@@ -58,7 +56,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
AGESAWRAPPER_PRE_CONSOLE(amdinitmmio);
- if (!cpu_init_detectedx && boot_cpu()) { + if (!cpu_init_detectedx) { post_code(0x30); sb_Poweron_Init();
diff --git a/src/mainboard/asrock/imb-a180/romstage.c b/src/mainboard/asrock/imb-a180/romstage.c index 2e639b1..f4779d7 100644 --- a/src/mainboard/asrock/imb-a180/romstage.c +++ b/src/mainboard/asrock/imb-a180/romstage.c @@ -26,14 +26,12 @@ #include <arch/stages.h> #include <device/pnp_def.h> #include <arch/cpu.h> -#include <cpu/x86/lapic.h> #include <console/console.h> #include <console/loglevel.h> #include "cpu/amd/car.h" #include <northbridge/amd/agesa/agesawrapper.h> #include <northbridge/amd/agesa/agesawrapper_call.h> #include "cpu/x86/bist.h" -#include "cpu/x86/lapic.h" #include "southbridge/amd/agesa/hudson/hudson.h" #include "cpu/amd/agesa/s3_resume.h" #include "cbmem.h" @@ -76,7 +74,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) t32 &= 0xffffbffb; *addr32 = t32;
- if (!cpu_init_detectedx && boot_cpu()) { + if (!cpu_init_detectedx) { post_code(0x30); post_code(0x31);
diff --git a/src/mainboard/asus/f2a85-m/romstage.c b/src/mainboard/asus/f2a85-m/romstage.c index bbe98f2..7ed5dc6 100644 --- a/src/mainboard/asus/f2a85-m/romstage.c +++ b/src/mainboard/asus/f2a85-m/romstage.c @@ -30,7 +30,6 @@ #include <cpu/amd/agesa/s3_resume.h> #include "cpu/amd/car.h" #include <cpu/x86/bist.h> -#include <cpu/x86/lapic.h> #include <device/pci_def.h> #include <device/pci_ids.h> #include <device/pnp_def.h> @@ -78,7 +77,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
AGESAWRAPPER_PRE_CONSOLE(amdinitmmio);
- if (!cpu_init_detectedx && boot_cpu()) { + if (!cpu_init_detectedx) {
/* enable SIO LPC decode */ dev = PCI_DEV(0, 0x14, 3); diff --git a/src/mainboard/gizmosphere/gizmo/romstage.c b/src/mainboard/gizmosphere/gizmo/romstage.c index ece6abc..9367342 100755 --- a/src/mainboard/gizmosphere/gizmo/romstage.c +++ b/src/mainboard/gizmosphere/gizmo/romstage.c @@ -27,7 +27,6 @@ #include <arch/stages.h> #include <device/pnp_def.h> #include <arch/cpu.h> -#include <cpu/x86/lapic.h> #include <console/console.h> #include <console/loglevel.h> #include <cpu/x86/mtrr.h> @@ -71,7 +70,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
AGESAWRAPPER_PRE_CONSOLE(amdinitmmio);
- if (!cpu_init_detectedx && boot_cpu()) { + if (!cpu_init_detectedx) { post_code(0x30); sb_Poweron_Init();
diff --git a/src/mainboard/hp/pavilion_m6_1035dx/romstage.c b/src/mainboard/hp/pavilion_m6_1035dx/romstage.c index 5ae2c68..492edf7 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/romstage.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/romstage.c @@ -28,7 +28,6 @@ #include <console/console.h> #include <cpu/amd/agesa/s3_resume.h> #include <cpu/x86/bist.h> -#include <cpu/x86/lapic.h> #include <cpu/amd/car.h> #include <device/pci_def.h> #include <device/pci_ids.h> @@ -43,7 +42,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
hudson_lpc_port80();
- if (!cpu_init_detectedx && boot_cpu()) { + if (!cpu_init_detectedx) { post_code(0x30);
post_code(0x31); diff --git a/src/mainboard/jetway/nf81-t56n-lf/romstage.c b/src/mainboard/jetway/nf81-t56n-lf/romstage.c index 2af5c7c..3ca303e 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/romstage.c +++ b/src/mainboard/jetway/nf81-t56n-lf/romstage.c @@ -28,7 +28,6 @@ #include <cbmem.h> #include <console/console.h> #include <cpu/amd/agesa/s3_resume.h> -#include <cpu/x86/lapic.h> #include <cpu/x86/bist.h>
#include <device/pci_def.h> @@ -79,7 +78,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
AGESAWRAPPER_PRE_CONSOLE(amdinitmmio);
- if (!cpu_init_detectedx && boot_cpu()) { + if (!cpu_init_detectedx) { post_code(0x30); sb_Poweron_Init();
diff --git a/src/mainboard/lippert/frontrunner-af/romstage.c b/src/mainboard/lippert/frontrunner-af/romstage.c index cc1edc0..cd5b251 100644 --- a/src/mainboard/lippert/frontrunner-af/romstage.c +++ b/src/mainboard/lippert/frontrunner-af/romstage.c @@ -26,7 +26,6 @@ #include <arch/stages.h> #include <device/pnp_def.h> #include <arch/cpu.h> -#include <cpu/x86/lapic.h> #include <console/console.h> #include <console/loglevel.h> #include <cpu/x86/mtrr.h> @@ -35,7 +34,6 @@ #include <northbridge/amd/agesa/agesawrapper_call.h> #include "cpu/x86/bist.h" #include <superio/smsc/smscsuperio/smscsuperio.h> -#include "cpu/x86/lapic.h" #include <cpu/x86/cache.h> #include <sb_cimx.h> #include "SBPLATFORM.h" @@ -62,7 +60,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
AGESAWRAPPER_PRE_CONSOLE(amdinitmmio);
- if (!cpu_init_detectedx && boot_cpu()) { + if (!cpu_init_detectedx) { post_code(0x30); sb_Poweron_Init();
diff --git a/src/mainboard/lippert/toucan-af/romstage.c b/src/mainboard/lippert/toucan-af/romstage.c index f332660..d6fd7e4 100644 --- a/src/mainboard/lippert/toucan-af/romstage.c +++ b/src/mainboard/lippert/toucan-af/romstage.c @@ -26,7 +26,6 @@ #include <arch/stages.h> #include <device/pnp_def.h> #include <arch/cpu.h> -#include <cpu/x86/lapic.h> #include <console/console.h> #include <console/loglevel.h> #include <cpu/x86/mtrr.h> @@ -36,7 +35,6 @@ #include "cpu/x86/bist.h" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627dhg/w83627dhg.h> -#include "cpu/x86/lapic.h" #include <cpu/x86/cache.h> #include <sb_cimx.h> #include "SBPLATFORM.h" @@ -63,7 +61,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
AGESAWRAPPER_PRE_CONSOLE(amdinitmmio);
- if (!cpu_init_detectedx && boot_cpu()) { + if (!cpu_init_detectedx) { post_code(0x30); sb_Poweron_Init();
diff --git a/src/mainboard/supermicro/h8qgi/romstage.c b/src/mainboard/supermicro/h8qgi/romstage.c index 2e6b1ed..adc8c20 100644 --- a/src/mainboard/supermicro/h8qgi/romstage.c +++ b/src/mainboard/supermicro/h8qgi/romstage.c @@ -25,7 +25,6 @@ #include <console/console.h> #include <arch/stages.h> #include "cpu/x86/bist.h" -#include "cpu/x86/lapic.h" #include "cpu/amd/car.h" #include <northbridge/amd/agesa/agesawrapper.h> #include <northbridge/amd/agesa/agesawrapper_call.h> @@ -68,7 +67,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x37); AGESAWRAPPER(amdinitreset);
- if (!cpu_init_detectedx && boot_cpu()) { + if (!cpu_init_detectedx) { post_code(0x38); /* * SR5650/5670/5690 RD890 chipset, read pci config space hang at POR, diff --git a/src/mainboard/supermicro/h8scm/romstage.c b/src/mainboard/supermicro/h8scm/romstage.c index ea522f7..7691bf9 100644 --- a/src/mainboard/supermicro/h8scm/romstage.c +++ b/src/mainboard/supermicro/h8scm/romstage.c @@ -25,7 +25,6 @@ #include <console/console.h> #include <arch/stages.h> #include "cpu/x86/bist.h" -#include "cpu/x86/lapic.h" #include "cpu/amd/car.h" #include <northbridge/amd/agesa/agesawrapper.h> #include <northbridge/amd/agesa/agesawrapper_call.h> @@ -67,7 +66,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x37); AGESAWRAPPER(amdinitreset);
- if (!cpu_init_detectedx && boot_cpu()) { + if (!cpu_init_detectedx) { post_code(0x38); /* * SR5650/5670/5690 RD890 chipset, read pci config space hang at POR, diff --git a/src/mainboard/tyan/s8226/romstage.c b/src/mainboard/tyan/s8226/romstage.c index 1d982f9..98e56c9 100644 --- a/src/mainboard/tyan/s8226/romstage.c +++ b/src/mainboard/tyan/s8226/romstage.c @@ -25,7 +25,6 @@ #include <console/console.h> #include <arch/stages.h> #include "cpu/x86/bist.h" -#include "cpu/x86/lapic.h" #include "cpu/amd/car.h" #include <northbridge/amd/agesa/agesawrapper.h> #include <northbridge/amd/agesa/agesawrapper_call.h> @@ -67,7 +66,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x37); AGESAWRAPPER(amdinitreset);
- if (!cpu_init_detectedx && boot_cpu()) { + if (!cpu_init_detectedx) { post_code(0x38); /* * SR5650/5670/5690 RD890 chipset, read pci config space hang at POR,