6 Jan
2021
6 Jan
'21
8:41 p.m.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49136 )
Change subject: mb/intel/adlrvp: Fix wrong comments and typo ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/49136/2/src/mainboard/intel/adlrvp/... File src/mainboard/intel/adlrvp/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/49136/2/src/mainboard/intel/adlrvp/... PS2, Line 74: Enable CPU PCIE PEG Slot 1 and 2
But, 0/1/0 and 0/6/2 are never enabled in devicetree or in the CpuPcieRpEnableMask?
We need to enable incrementally, i have to clean up CpuPciRpMask parameter as well.
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I92123450bd7cfb2e70aae8de03053672a7772451
Gerrit-Change-Number: 49136
Gerrit-PatchSet: 3
Gerrit-Owner: Subrata Banik subrata.banik@intel.com
Gerrit-Reviewer: Angel Pons th3fanbus@gmail.com
Gerrit-Reviewer: Furquan Shaikh furquan@google.com
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