[coreboot-gerrit] Change in ...coreboot[master]: coreboot: add post code for invalid FSP

[Keith Short (Code Review)]

Hello Patrick Rudolph, Huang Jin, Philipp Deppenwiese, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/32772

to look at the new patch set (#2).

Change subject: coreboot: add post code for invalid FSP
......................................................................

coreboot: add post code for invalid FSP

Add a new post code POST_INVALID_FSP, used when coreboot fails to locate
or validate Intel FSP.

BUG=b:124401932
BRANCH=sarien
TEST=build coreboot for sarien and arcada platforms

Change-Id: Ib1e359d4e8772c37922b1b779135e58c73bff6b4
Signed-off-by: Keith Short 
---
M src/drivers/intel/fsp2_0/memory_init.c
M src/drivers/intel/fsp2_0/silicon_init.c
M src/include/console/post_codes.h
M src/soc/intel/fsp_baytrail/romstage/romstage.c
M src/soc/intel/fsp_broadwell_de/romstage/romstage.c
5 files changed, 19 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/32772/2