[coreboot-gerrit] Patch set updated for coreboot: nb/i945/early_init.c: Add FSB800 and 1067 to Egress Port Virtual Channel

[HAOUAS Elyes]

HAOUAS Elyes ([e-mail]) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17198

-gerrit

commit a88c75f88190cbcf807ee123bbfb5ce0f88d62fe
Author: Elyes HAOUAS 
Date:   Mon Oct 31 18:55:04 2016 +0100

nb/i945/early_init.c: Add FSB800 and 1067 to Egress Port Virtual Channel

Values based on vendor bios and suggested by Arthur Heymans for FSB1067.
    FSB1067:
    The ratio 1067/800 is proportional to the ratio of EPBAR32(0x2c) bits:
    0x1a / 0x14 ~ 1067/800
    EPVC1IST:
    The ratio is also proportional to FSB ratios: 0x9c / 0xf0 ~ 533/800.

Change-Id: Ib90e8ea1b82f2fcc3b5c199cace32a7f0aff4b5c
    Signed-off-by: Elyes HAOUAS 
---
 src/northbridge/intel/i945/early_init.c | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c
index 377302a..8930cb6 100644
--- a/src/northbridge/intel/i945/early_init.c
+++ b/src/northbridge/intel/i945/early_init.c
@@ -232,8 +232,14 @@ static void i945_setup_egress_port(void)
    /* Egress Port Virtual Channel 1 Configuration */
    reg32 = EPBAR32(0x2c);
    reg32 &= 0xffffff00;
+	if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC)) {
+		if ((MCHBAR32(CLKCFG) & 7) == 0)
+			reg32 |= 0x1a;	/* 1067MHz */
+	}
    if ((MCHBAR32(CLKCFG) & 7) == 1)
    	reg32 |= 0x0d;	/* 533MHz */
+	if ((MCHBAR32(CLKCFG) & 7) == 2)
+		reg32 |= 0x14;	/* 800MHz */
    if ((MCHBAR32(CLKCFG) & 7) == 3)
    	reg32 |= 0x10;	/* 667MHz */
    EPBAR32(0x2c) = reg32;
@@ -245,11 +251,23 @@ static void i945_setup_egress_port(void)
    reg32 |= (0x0a << 16);
    EPBAR32(EPVC1RCAP) = reg32;

+	if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC)) {
+		if ((MCHBAR32(CLKCFG) & 7) == 0){	/* 1067MHz */
+			EPBAR32(EPVC1IST + 0) = 0x01380138;
+			EPBAR32(EPVC1IST + 4) = 0x01380138;
+		}
+	}
+
    if ((MCHBAR32(CLKCFG) & 7) == 1) {	/* 533MHz */
    	EPBAR32(EPVC1IST + 0) = 0x009c009c;
    	EPBAR32(EPVC1IST + 4) = 0x009c009c;
    }

+	if ((MCHBAR32(CLKCFG) & 7) == 2) {	/* 800MHz */
+		EPBAR32(EPVC1IST + 0) = 0x00f000f0;
+		EPBAR32(EPVC1IST + 4) = 0x00f000f0;
+	}
+
    if ((MCHBAR32(CLKCFG) & 7) == 3) {	/* 667MHz */
    	EPBAR32(EPVC1IST + 0) = 0x00c000c0;
    	EPBAR32(EPVC1IST + 4) = 0x00c000c0;