[coreboot-gerrit] Change in coreboot[master]: soc/intel/elkhartlake: Expose In-Band ECC config to mainboard

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55668 )

Change subject: soc/intel/elkhartlake: Expose In-Band ECC config to mainboard
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soc/intel/elkhartlake: Expose In-Band ECC config to mainboard

Elkhart Lake provides a feature called "In-Band ECC" which uses a piece
of system DRAM to store the ECC information in. There are a few
parameters in FSP-M to set this feature up as needed.

This patch adds code to expose these parameters to the devicetree so
that they can be configured on mainboard level as needed.

Change-Id: I7a4953d7b35277de01daff04211450e3d1bd8103
Signed-off-by: Werner Zeh 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55668
Reviewed-by: Lean Sheng Tan 
Tested-by: build bot (Jenkins) 
---
M src/soc/intel/elkhartlake/chip.h
M src/soc/intel/elkhartlake/romstage/fsp_params.c
2 files changed, 36 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Lean Sheng Tan: Looks good to me, approved

diff --git a/src/soc/intel/elkhartlake/chip.h b/src/soc/intel/elkhartlake/chip.h
index c2faddc..e4c8e38 100644
--- a/src/soc/intel/elkhartlake/chip.h
+++ b/src/soc/intel/elkhartlake/chip.h
@@ -24,6 +24,24 @@
 #define MAX_HD_AUDIO_SNDW_LINKS	4
 #define MAX_HD_AUDIO_SSP_LINKS	6

+/* Define config parameters for In-Band ECC (IBECC). */
+#define MAX_IBECC_REGIONS	8
+
+enum ibecc_mode {
+	IBECC_PER_REGION,
+	IBECC_NONE,
+	IBECC_ALL
+};
+
+struct ehl_ibecc_config {
+	bool enable;
+	bool parity_en;
+	enum ibecc_mode mode;
+	bool region_enable[MAX_IBECC_REGIONS];
+	uint16_t region_base[MAX_IBECC_REGIONS];
+	uint16_t region_mask[MAX_IBECC_REGIONS];
+};
+
 struct soc_intel_elkhartlake_config {

/* Common struct containing soc config data required by common code */
@@ -68,6 +86,9 @@
    /* Memory Thermal Throttling: Enable - Default (0) / Disable (1) */
    bool MemoryThermalThrottlingDisable;

+	/* In-Band ECC (IBECC) configuration */
+	struct ehl_ibecc_config ibecc;
+
    /* FuSa (Functional Safety): Disable - Default (0) / Enable (1) */
    bool FuSaEnable;

diff --git a/src/soc/intel/elkhartlake/romstage/fsp_params.c b/src/soc/intel/elkhartlake/romstage/fsp_params.c
index 4f8657a..449d14e 100644
--- a/src/soc/intel/elkhartlake/romstage/fsp_params.c
+++ b/src/soc/intel/elkhartlake/romstage/fsp_params.c
@@ -107,6 +107,21 @@

/* Processor Early Power On Configuration FCLK setting */
    m_cfg->FClkFrequency = 0x1;
+
+	/* Ib-Band ECC configuration */
+	if (config->ibecc.enable) {
+		m_cfg->Ibecc = !!config->ibecc.enable;
+		m_cfg->IbeccParity = !!config->ibecc.parity_en;
+		m_cfg->IbeccOperationMode = config->ibecc.mode;
+		if (m_cfg->IbeccOperationMode == IBECC_PER_REGION) {
+			FSP_ARRAY_LOAD(m_cfg->IbeccProtectedRegionEnable,
+				       config->ibecc.region_enable);
+			FSP_ARRAY_LOAD(m_cfg->IbeccProtectedRegionBase,
+				       config->ibecc.region_base);
+			FSP_ARRAY_LOAD(m_cfg->IbeccProtectedRegionMask,
+				       config->ibecc.region_mask);
+		}
+	}
 }

void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)