[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: Update Kconfig for NEM Enhanced Mode

[Shreesh Chhabbi (Code Review)]

Shreesh Chhabbi has uploaded a new patch set (#15) to the change originally created by Shreesh Chhabbi. ( https://review.coreboot.org/c/coreboot/+/47259 )

Change subject: soc/intel/tigerlake: Update Kconfig for NEM Enhanced Mode
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soc/intel/tigerlake: Update Kconfig for NEM Enhanced Mode

IA32_PQR_ASSOC (0xC8F) MSR's Bits[32:33] are used for mask selection
when Kconfig COS_MAPPED_TO_MSB is selected. In cpu/Kconfig, if
INTEL_CAR_NEM_ENHANCED is selected, in tigerlake/Kconfig, selecting
COS_MAPPED_TO_MSB to ensure Bits[32:33] are used for mask selection.
This enables NEM Enhanced Mode for TGL-U/Y RVPs.

Bug=b:171601324
BRANCH=volteer
Test=Build coreboot for volteer. Boot on SKU that has 4MB L3 cache.

Change-Id: Ib6e041261cb8ca9c6e602935da4962aac0d9ece5
Signed-off-by: Shreesh Chhabbi 
---
M src/mainboard/google/volteer/Kconfig.name
M src/soc/intel/tigerlake/Kconfig
2 files changed, 8 insertions(+), 9 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/47259/15