[coreboot-gerrit] Change in coreboot[master]: coreboot_tables: Add PCIe info to coreboot table

[Veerabhadrarao Badiganti (Code Review)]

Attention is currently required from: Shelley Chen, Ravi Kumar Bokka, Hung-Te Lin, Nico Huber, Tim Wawrzynczak, Paul Menzel, Rex-BC Chen, Julius Werner, Arthur Heymans, Yu-Ping Wu, Jianjun Wang.
Veerabhadrarao Badiganti has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63251 )

Change subject: coreboot_tables: Add PCIe info to coreboot table
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Patch Set 20:

(1 comment)

Patchset:

PS9:
> Hi Yu-ping. […]

Hi,

If we have the ctrl_base, the rest three parameters (atu_base, mmio_base,mmio_size) remain constant on Qualcomm SoC.  I checked different SoCs, on all of them they remain same/constant.

On 1MB size of mmio_size => on a single bus we can have max 32 devices and each device we can have max 8 functions. And each of this function can have 4KB config space. To accommodate config space for max possible devices we are assigning 1MB (4KB * 32 * 8).