[coreboot-gerrit] Change in coreboot[master]: intel/i945: Define peg_plugin for potential add-on PCIe card

[Kyösti Mälkki (Code Review)]

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35677 )

Change subject: intel/i945: Define peg_plugin for potential add-on PCIe card
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intel/i945: Define peg_plugin for potential add-on PCIe card

Change-Id: I06f6a7ed7a1ce935d154b8c7b11dcb81608329b9
Signed-off-by: Kyösti Mälkki 
---
M src/northbridge/intel/i945/early_init.c
1 file changed, 10 insertions(+), 7 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/35677/1

diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c
index c53577b..d6d37d9 100644
--- a/src/northbridge/intel/i945/early_init.c
+++ b/src/northbridge/intel/i945/early_init.c
@@ -531,6 +531,9 @@
    u16 reg16;
    pci_devfn_t p2peg = PCI_DEV(0, 0x01, 0);

+	u8 tmp_secondary = 0x0a;
+	pci_devfn_t peg_plugin = PCI_DEV(tmp_secondary, 0, 0);
+
    printk(BIOS_DEBUG, "Enabling PCI Express x16 Link\n");

reg16 = pci_read_config16(PCI_DEV(0, 0x00, 0), DEVEN);
@@ -562,10 +565,10 @@
    reg16 |= (1 << 4) | (1 << 0);
    pci_write_config16(p2peg, SLOTSTS, reg16);

-	pci_write_config8(p2peg, SBUSN1, 0x00);
-	pci_write_config8(p2peg, SUBUSN1, 0x00);
-	pci_write_config8(p2peg, SBUSN1, 0x0a);
-	pci_write_config8(p2peg, SUBUSN1, 0x0a);
+	pci_write_config8(p2peg, PCI_SECONDARY_BUS, 0x00);
+	pci_write_config8(p2peg, PCI_SUBORDINATE_BUS, 0x00);
+	pci_write_config8(p2peg, PCI_SECONDARY_BUS, tmp_secondary);
+	pci_write_config8(p2peg, PCI_SUBORDINATE_BUS, tmp_secondary);

reg32 = pci_read_config32(p2peg, 0x224);
    reg32 &= ~(1 << 8);
@@ -597,7 +600,7 @@
    	&& --timeout)
    	;

-	reg32 = pci_read_config32(PCI_DEV(0x0a, 0x0, 0), 0);
+	reg32 = pci_read_config32(peg_plugin, PCI_VENDOR_ID);
    if (reg32 != 0x00000000 && reg32 != 0xffffffff) {
    	printk(BIOS_DEBUG, " Detected PCIe device %04x:%04x\n",
    			reg32 & 0xffff, reg32 >> 16);
@@ -623,7 +626,7 @@
    		&& --timeout)
    		;

-		reg32 = pci_read_config32(PCI_DEV(0xa, 0x00, 0), 0);
+		reg32 = pci_read_config32(peg_plugin, PCI_VENDOR_ID);
    	if (reg32 != 0x00000000 && reg32 != 0xffffffff) {
    		printk(BIOS_DEBUG, " Detected PCIe x1 device %04x:%04x\n",
    			reg32 & 0xffff, reg32 >> 16);
@@ -651,7 +654,7 @@
    	// TODO
    	/* pci_write_config32(p2peg, PEGTC, reg32); */

-	reg32 = (pci_read_config32(PCI_DEV(0xa, 0, 0), 0x8) >> 8);
+	reg32 = (pci_read_config32(peg_plugin, 0x8) >> 8);
    printk(BIOS_DEBUG, "PCIe device class: %06x\n", reg32);
    if (reg32 == 0x030000) {
    	printk(BIOS_DEBUG, "PCIe device is VGA. Disabling IGD.\n");