Shreesh Chhabbi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48286 )
Change subject: src/soc/intel: Add support for CAR_HAS_SF_MASKS and select for TGL ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48286/5/src/soc/intel/common/block/... File src/soc/intel/common/block/cpu/car/cache_as_ram.S:
https://review.coreboot.org/c/coreboot/+/48286/5/src/soc/intel/common/block/... PS5, Line 435: /* : * Program MSR 0x1892 IA32_CR_SF_QOS_MASK_2 with : * total number of LLC ways : */ : movl $IA32_CR_SF_QOS_MASK_2, %ecx : xorl %edx, %edx : wrmsr
Do we have a definition for the reset value for that MSR? I know the doc said to program them it as […]
Yes Furquan, I was planning to now address this part now that other bugs were addressed in the patch. IA32_L3_MASK_2 and IA32_CR_SF_QOS_MASK_2 MSRs take effect only if IA32_PQR_ASSOC is programmed with value of 0x2. Currently we program it to 0x1 in the end. So I think that's why CPU team recommended to leave IA32_CR_SF_QOS_MASK_2 to default. I can remove programming of IA32_CR_SF_QOS_MASK_2. Tim from EDS document, reset default for IA32_CR_SF_QOS_MASK_x is 0FFFFFFFh.