Nico Huber has uploaded this change for review. ( https://review.coreboot.org/25145
Change subject: util/inteltool: Report Skylake GPIOs as clumsy coreboot macros ......................................................................
util/inteltool: Report Skylake GPIOs as clumsy coreboot macros
Change-Id: Id8895f5d76ba2984fbda757fc00a42ac0ae852d4 Signed-off-by: Nico Huber nico.h@gmx.de --- M util/inteltool/gpio_groups.c 1 file changed, 149 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/25145/1
diff --git a/util/inteltool/gpio_groups.c b/util/inteltool/gpio_groups.c index 3937507..6d9cd6d 100644 --- a/util/inteltool/gpio_groups.c +++ b/util/inteltool/gpio_groups.c @@ -510,6 +510,148 @@ return "RESERVED"; }
+static const char *decode_table_gpio_term(const size_t term) +{ + switch (term) { + case 0: return "NONE"; + case 2: return "5K_PD"; + case 4: return "20K_PD"; + case 9: return "1K_PU"; + case 10: return "5K_PU"; + case 11: return "2K_PU"; + case 12: return "20K_PU"; + case 13: return "667_PU"; + case 15: return "NATIVE"; + default: return "UNSUPPORTED"; + } +} + +static const char *decode_table_gpio_reset(const size_t reset) +{ + switch (reset) { + case 0: return "DSW_PWROK"; + case 1: return "DEEP"; + case 2: return "PLTRST"; + case 3: return "RSMRST"; + default: return "UNSUPPORTED"; + } +} + +static const char *decode_table_gpio_nf(const size_t pad_mode) +{ + switch (pad_mode) { + case 0: return "GPIO"; + case 1: return "NF1"; + case 2: return "NF2"; + case 3: return "NF3"; + default: return "UNSUPPORTED"; + } +} + +static int print_table_gpio(const struct gpio_group *const group, + const size_t pad, + const uint32_t dw0, const uint32_t dw1) +{ + /* 3032 */ + const size_t tx_state = dw0 >> 0 & 1; + const size_t tx_disable = dw0 >> 8 & 1; + const size_t rx_disable = dw0 >> 9 & 1; + const size_t pad_mode = dw0 >> 10 & 7; + const size_t int_route = dw0 >> 17 & 0x0f; + const size_t rx_invert = dw0 >> 23 & 1; + const size_t rx_evcfg = dw0 >> 25 & 3; + const size_t rx_raw1 = dw0 >> 28 & 1; + const size_t rx_padsel = dw0 >> 29 & 1; + const size_t pad_reset = dw0 >> 30 & 3; + const size_t term = dw1 >> 10 & 0x0f; + const size_t pad_tol = dw1 >> 25 & 0x01; + + const char *const pad_name = group->pad_names[pad * group->func_count]; + + if (rx_padsel || rx_raw1) + return -1; + + if (pad_mode) { + printf("PAD_CFG_NF%s(%s, %s, %s, %s),\n", + pad_tol ? "_1V8" : "", pad_name, + decode_table_gpio_term(term), + decode_table_gpio_reset(pad_reset), + decode_table_gpio_nf(pad_mode)); + } else if (!tx_disable) { + if (!rx_disable) { + fprintf(stderr, "WARNING: %s has both TX and RX enabled" + ", disabling RX!\n", pad_name); + } + if (term) { + printf("PAD_CFG_TERM_GPO(%s, %zu, %s, %s),\n", + pad_name, tx_state, + decode_table_gpio_term(term), + decode_table_gpio_reset(pad_reset)); + } else { + printf("PAD_CFG_GPO(%s, %zu, %s),\n", + pad_name, tx_state, + decode_table_gpio_reset(pad_reset)); + } + } else if (!rx_disable && tx_disable) { + switch (int_route) { + case 0x0: + if (rx_invert || rx_evcfg > 1) + return -1; + printf("PAD_CFG_GPI%s(%s, %s, %s%s),\n", + rx_evcfg ? "_INT" : "", + pad_name, + decode_table_gpio_term(term), + decode_table_gpio_reset(pad_reset), + rx_evcfg ? ", EDGE" : ""); + break; + case 0x1: + return -1; + case 0x2: + if (rx_evcfg == 1) { + printf("PAD_CFG_GPI_ACPI_SMI" + "(%s, %s, %s, %s),\n", + pad_name, + decode_table_gpio_term(term), + decode_table_gpio_reset(pad_reset), + rx_invert ? "YES" : "NO"); + } else { + return -1; + } + break; + case 0x4: + if (rx_evcfg > 1) + return -1; + printf("PAD_CFG_GPI_ACPI_SCI%s(%s, %s, %s, %s),\n", + rx_evcfg ? "" : "_LEVEL", pad_name, + decode_table_gpio_term(term), + decode_table_gpio_reset(pad_reset), + rx_invert ? "YES" : "NO"); + break; + case 0x8: + if (rx_evcfg > 1 || (rx_evcfg == 1 && rx_invert)) + return -1; + printf("PAD_CFG_GPI_APIC%s(%s, %s, %s),\n", + rx_evcfg ? "_EDGE" : rx_invert ? "_INVERT" : "", + pad_name, + decode_table_gpio_term(term), + decode_table_gpio_reset(pad_reset)); + break; + default: + return -1; + } + } else { + if (term) { + printf("_PAD_CFG(%s, %s, %s),\n", pad_name, + decode_table_gpio_term(term), + "_DW0_VALS(DEEP, RAW, NO, LEVEL, NO, NO, " + "NO, NO, NO, NO, GPIO, YES, YES)"); + } else { + printf("PAD_CFG_NC(%s),\n", pad_name); + } + } + return 0; +} + static void print_gpio_group(const uint8_t pid, size_t pad_cfg, const struct gpio_group *const group) { @@ -521,10 +663,13 @@ const uint32_t dw0 = read_pcr32(pid, pad_cfg); const uint32_t dw1 = read_pcr32(pid, pad_cfg + 4);
- printf("0x%04zx: 0x%016"PRIx64" %-8s %-20s\n", pad_cfg, - (uint64_t)dw1 << 32 | dw0, - group->pad_names[p * group->func_count], - decode_pad_mode(group, p, dw0)); + printf("0x%04zx: /* %-8s %-20s 0x%016"PRIx64" */ ", + pad_cfg, group->pad_names[p * group->func_count], + decode_pad_mode(group, p, dw0), + (uint64_t)dw1 << 32 | dw0); + + if (print_table_gpio(group, p, dw0, dw1)) + printf("PAD_CFG_UNSUPPORTED,\n"); } }