[coreboot-gerrit] Change in coreboot[master]: soc/intel/{cnl, icl}: Update the DCACHE_BSP_STACK_SIZE to 129KiB

[Kyösti Mälkki (Code Review)]

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36032 )

Change subject: soc/intel/{cnl, icl}: Update the DCACHE_BSP_STACK_SIZE to 129KiB
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Patch Set 3: Code-Review+1

(1 comment)

https://review.coreboot.org/c/coreboot/+/36032/2/src/soc/intel/cannonlake/Kc... 
File src/soc/intel/cannonlake/Kconfig:

https://review.coreboot.org/c/coreboot/+/36032/2/src/soc/intel/cannonlake/Kc... 
PS2, Line 128: 	  sum of FSP stack requirement (128KiB) and CB stack requirement (1KiB).
> Considering that FSP is the biggest consumer, I believe it should be okay?

The alignment requirement I was thinking was for ramstage and does not apply here.

The comment could be explicit 'CB stack requirement in romstage', vboot/measured boot would not call into FSP.