Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35620 )
Change subject: soc/intel/{skl,icl,cnl}/chip: Unhide P2SB device ......................................................................
soc/intel/{skl,icl,cnl}/chip: Unhide P2SB device
APL unhides the P2SB device in coreboot already. Do it the same on other SoCs. As the coreboot PCI allocator needs to be able to find the device, unhide it after FSP-S.
Fixes "BUG: XXX requests hidden ...." warnings in coreboot log.
Change-Id: I0d14646098c34d3bf5cd49c35dcfcdce2c57431d Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com --- M src/soc/intel/cannonlake/chip.c M src/soc/intel/icelake/chip.c M src/soc/intel/skylake/chip_fsp20.c 3 files changed, 24 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/35620/1
diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c index 4e0dba5..e3962c0 100644 --- a/src/soc/intel/cannonlake/chip.c +++ b/src/soc/intel/cannonlake/chip.c @@ -21,6 +21,7 @@ #include <intelblocks/chip.h> #include <intelblocks/itss.h> #include <intelblocks/xdci.h> +#include <intelblocks/p2sb.h> #include <romstage_handoff.h> #include <soc/intel/common/vbt.h> #include <soc/pci_devs.h> @@ -187,6 +188,13 @@ /* Perform silicon specific init. */ fsp_silicon_init(romstage_handoff_is_resume());
+ /* + * Keep the P2SB device visible so it and the other devices are + * visible in coreboot for driver support and PCI resource allocation. + * There is no UPD setting for this. + */ + p2sb_unhide(); + /* Display FIRMWARE_VERSION_INFO_HOB */ fsp_display_fvi_version_hob();
diff --git a/src/soc/intel/icelake/chip.c b/src/soc/intel/icelake/chip.c index c4abb0c..abaae9f 100644 --- a/src/soc/intel/icelake/chip.c +++ b/src/soc/intel/icelake/chip.c @@ -21,6 +21,7 @@ #include <intelblocks/chip.h> #include <intelblocks/itss.h> #include <intelblocks/xdci.h> +#include <intelblocks/p2sb.h> #include <romstage_handoff.h> #include <soc/intel/common/vbt.h> #include <soc/itss.h> @@ -128,6 +129,13 @@ /* Perform silicon specific init. */ fsp_silicon_init(romstage_handoff_is_resume());
+ /* + * Keep the P2SB device visible so it and the other devices are + * visible in coreboot for driver support and PCI resource allocation. + * There is no UPD setting for this. + */ + p2sb_unhide(); + /* Display FIRMWARE_VERSION_INFO_HOB */ fsp_display_fvi_version_hob();
diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c index d1d7d6f..7fe1601 100644 --- a/src/soc/intel/skylake/chip_fsp20.c +++ b/src/soc/intel/skylake/chip_fsp20.c @@ -28,6 +28,7 @@ #include <intelblocks/lpc_lib.h> #include <intelblocks/mp_init.h> #include <intelblocks/xdci.h> +#include <intelblocks/p2sb.h> #include <intelpch/lockdown.h> #include <romstage_handoff.h> #include <soc/acpi.h> @@ -175,6 +176,13 @@ /* Perform silicon specific init. */ fsp_silicon_init(romstage_handoff_is_resume());
+ /* + * Keep the P2SB device visible so it and the other devices are + * visible in coreboot for driver support and PCI resource allocation. + * There is no UPD setting for this. + */ + p2sb_unhide(); + /* Restore GPIO IRQ polarities back to previous settings. */ itss_restore_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END);