Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37813 )
Change subject: amdblocks/acpimmio: add missing MMIO functions ......................................................................
amdblocks/acpimmio: add missing MMIO functions
Add missing Power Management 2, old and new GPIO functions to modify the contents of these MMIO blocks.
Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com Change-Id: Ie4db6a4d12d9122ea5b87147adbf7b632ac2b311 --- M src/soc/amd/common/block/include/amdblocks/acpimmio.h M src/soc/amd/common/block/include/amdblocks/acpimmio_map.h 2 files changed, 156 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/37813/1
diff --git a/src/soc/amd/common/block/include/amdblocks/acpimmio.h b/src/soc/amd/common/block/include/amdblocks/acpimmio.h index c441ab8..7194853 100644 --- a/src/soc/amd/common/block/include/amdblocks/acpimmio.h +++ b/src/soc/amd/common/block/include/amdblocks/acpimmio.h @@ -214,6 +214,36 @@ write32((void *)(ACPIMMIO_PMIO_BASE + reg), value); }
+static inline uint8_t pm2_read8(uint8_t reg) +{ + return read8((void *)(ACPIMMIO_PMIO2_BASE + reg)); +} + +static inline uint16_t pm2_read16(uint8_t reg) +{ + return read16((void *)(ACPIMMIO_PMIO2_BASE + reg)); +} + +static inline uint32_t pm2_read32(uint8_t reg) +{ + return read32((void *)(ACPIMMIO_PMIO2_BASE + reg)); +} + +static inline void pm2_write8(uint8_t reg, uint8_t value) +{ + write8((void *)(ACPIMMIO_PMIO2_BASE + reg), value); +} + +static inline void pm2_write16(uint8_t reg, uint16_t value) +{ + write16((void *)(ACPIMMIO_PMIO2_BASE + reg), value); +} + +static inline void pm2_write32(uint8_t reg, uint32_t value) +{ + write32((void *)(ACPIMMIO_PMIO2_BASE + reg), value); +} + static inline uint8_t biosram_read8(uint8_t reg) { return read8((void *)(ACPIMMIO_BIOSRAM_BASE + reg)); @@ -354,6 +384,131 @@ write32((void *)(ACPIMMIO_MISC_BASE + reg), value); }
+/* Old GPIO configuration registers */ +static inline uint8_t gpio_100_read8(uint8_t reg) +{ + return read8((void *)(ACPIMMIO_GPIO_BASE_100 + reg)); +} + +static inline uint16_t gpio_100_read16(uint8_t reg) +{ + return read16((void *)(ACPIMMIO_GPIO_BASE_100 + reg)); +} + +static inline uint32_t gpio_100_read32(uint8_t reg) +{ + return read32((void *)(ACPIMMIO_GPIO_BASE_100 + reg)); +} + +static inline void gpio_100_write8(uint8_t reg, uint8_t value) +{ + write8((void *)(ACPIMMIO_GPIO_BASE_100 + reg), value); +} + +static inline void gpio_100_write16(uint8_t reg, uint16_t value) +{ + write16((void *)(ACPIMMIO_GPIO_BASE_100 + reg), value); +} + +static inline void gpio_100_write32(uint8_t reg, uint32_t value) +{ + write32((void *)(ACPIMMIO_GPIO_BASE_100 + reg), value); +} + +/* New GPIO banks configuration registers */ +/* GPIO bank 0 */ +static inline uint8_t gpio0_read8(uint8_t reg) +{ + return read8((void *)(ACPIMMIO_GPIO0_BASE + reg)); +} + +static inline uint16_t gpio0_read16(uint8_t reg) +{ + return read16((void *)(ACPIMMIO_GPIO0_BASE + reg)); +} + +static inline uint32_t gpio0_read32(uint8_t reg) +{ + return read32((void *)(ACPIMMIO_GPIO0_BASE + reg)); +} + +static inline void gpio0_write8(uint8_t reg, uint8_t value) +{ + write8((void *)(ACPIMMIO_GPIO0_BASE + reg), value); +} + +static inline void gpio0_write16(uint8_t reg, uint16_t value) +{ + write16((void *)(ACPIMMIO_GPIO0_BASE + reg), value); +} + +static inline void gpio0_write32(uint8_t reg, uint32_t value) +{ + write32((void *)(ACPIMMIO_GPIO0_BASE + reg), value); +} + +/* GPIO bank 1 */ +static inline uint8_t gpio1_read8(uint8_t reg) +{ + return read8((void *)(ACPIMMIO_GPIO1_BASE + reg)); +} + +static inline uint16_t gpio1_read16(uint8_t reg) +{ + return read16((void *)(ACPIMMIO_GPIO1_BASE + reg)); +} + +static inline uint32_t gpio1_read32(uint8_t reg) +{ + return read32((void *)(ACPIMMIO_GPIO1_BASE + reg)); +} + +static inline void gpio1_write8(uint8_t reg, uint8_t value) +{ + write8((void *)(ACPIMMIO_GPIO1_BASE + reg), value); +} + +static inline void gpio1_write16(uint8_t reg, uint16_t value) +{ + write16((void *)(ACPIMMIO_GPIO1_BASE + reg), value); +} + +static inline void gpio1_write32(uint8_t reg, uint32_t value) +{ + write32((void *)(ACPIMMIO_GPIO1_BASE + reg), value); +} + +/* GPIO bank 2 */ +static inline uint8_t gpio2_read8(uint8_t reg) +{ + return read8((void *)(ACPIMMIO_GPIO2_BASE + reg)); +} + +static inline uint16_t gpio2_read16(uint8_t reg) +{ + return read16((void *)(ACPIMMIO_GPIO2_BASE + reg)); +} + +static inline uint32_t gpio2_read32(uint8_t reg) +{ + return read32((void *)(ACPIMMIO_GPIO2_BASE + reg)); +} + +static inline void gpio2_write8(uint8_t reg, uint8_t value) +{ + write8((void *)(ACPIMMIO_GPIO2_BASE + reg), value); +} + +static inline void gpio2_write16(uint8_t reg, uint16_t value) +{ + write16((void *)(ACPIMMIO_GPIO2_BASE + reg), value); +} + +static inline void gpio2_write32(uint8_t reg, uint32_t value) +{ + write32((void *)(ACPIMMIO_GPIO2_BASE + reg), value); +} + static inline uint8_t xhci_pm_read8(uint8_t reg) { return read8((void *)(ACPIMMIO_XHCIPM_BASE + reg)); diff --git a/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h b/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h index 9a15840..4d62b39 100644 --- a/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h +++ b/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h @@ -48,6 +48,7 @@
#define AMD_SB_ACPI_MMIO_ADDR 0xfed80000 #define ACPIMMIO_SM_PCI_BASE 0xfed80000 +#define ACPIMMIO_GPIO_BASE_100 0xfed80100 #define ACPIMMIO_SMI_BASE 0xfed80200 #define ACPIMMIO_PMIO_BASE 0xfed80300 #define ACPIMMIO_PMIO2_BASE 0xfed80400