[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: Move GPIO PM configuration to soc level

[Jes Klinke (Code Review)]

Hello Jes Klinke,

I'd like you to do a code review. Please visit

https://review.coreboot.org/c/coreboot/+/41182

to review the following change.

Change subject: soc/intel/tigerlake: Move GPIO PM configuration to soc level
......................................................................

soc/intel/tigerlake: Move GPIO PM configuration to soc level

This CL attempts to mirror prior Cannonlake CL:
https://review.coreboot.org/c/coreboot/+/37685

Change-Id: Ia7dfeace7c7d7540affb9170c00622d1699f3c6b
Signed-off-by: Jes Klinke
---
M src/soc/intel/tigerlake/acpi/gpio.asl
1 file changed, 41 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/41182/1

diff --git a/src/soc/intel/tigerlake/acpi/gpio.asl b/src/soc/intel/tigerlake/acpi/gpio.asl
index d1e4955..7de8c5f 100644
--- a/src/soc/intel/tigerlake/acpi/gpio.asl
+++ b/src/soc/intel/tigerlake/acpi/gpio.asl
@@ -129,3 +129,44 @@

Return (Local0)
 }
+
+/* GPIO Power Management bits */
+Name(GPMB, Package(TOTAL_GPIO_COMM) {0})
+
+/*
+ * Save GPIO Power Management bits
+ */
+Method (SGPM, 0, Serialized)
+{
+	For (Local0 = 0, Local0 < TOTAL_GPIO_COMM, Local0++)
+	{
+		Local1 = GPID (Local0)
+		GPMB[Local0] = PCRR (Local1, GPIO_MISCCFG)
+	}
+}
+
+/*
+ * Restore GPIO Power Management bits
+ */
+Method (RGPM, 0, Serialized)
+{
+	For (Local0 = 0, Local0 < TOTAL_GPIO_COMM, Local0++)
+	{
+		CGPM (Local0, DerefOf(GPMB[Local0]))
+	}
+}
+
+/*
+ * Save current setting of GPIO Power Management bits and
+ * enable all Power Management bits for all communities
+ */
+Method (EGPM, 0, Serialized)
+{
+	/* Save current setting and will restore it when resuming */
+	SGPM ()
+	/* Enable PM bits */
+	For (Local0 = 0, Local0 < TOTAL_GPIO_COMM, Local0++)
+	{
+		CGPM (Local0, MISCCFG_ENABLE_GPIO_PM_CONFIG)
+	}
+}