[coreboot-gerrit] Change in coreboot[master]: sb/intel/lynxpoint/sata.c: Don't enable Bus Master

[Angel Pons (Code Review)]

Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/47031 )

Change subject: sb/intel/lynxpoint/sata.c: Don't enable Bus Master
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sb/intel/lynxpoint/sata.c: Don't enable Bus Master

Bus Master is not required and reference code does not set it.

Tested on Asrock B85M Pro4, still boots from SATA SSD with TianoCore.

Change-Id: I7a84da5b712e6fa569ad9f412c440afeb6a8cc5d
Signed-off-by: Angel Pons 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47031
Tested-by: build bot (Jenkins) 
Reviewed-by:  Felix Singer 
Reviewed-by: Michael Niewöhner 
---
M src/southbridge/intel/lynxpoint/sata.c
1 file changed, 2 insertions(+), 3 deletions(-)

Approvals:
  build bot (Jenkins): Verified
   Felix Singer: Looks good to me, approved
  Michael Niewöhner: Looks good to me, approved

diff --git a/src/southbridge/intel/lynxpoint/sata.c b/src/southbridge/intel/lynxpoint/sata.c
index 510440b..e1a2fa5 100644
--- a/src/southbridge/intel/lynxpoint/sata.c
+++ b/src/southbridge/intel/lynxpoint/sata.c
@@ -41,9 +41,8 @@

/* SATA configuration */

-	/* Enable BARs */
-	pci_write_config16(dev, PCI_COMMAND,
-			   PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
+	/* Enable memory space decoding for ABAR */
+	pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_IO);

if (config->ide_legacy_combined) {
    	printk(BIOS_DEBUG, "SATA: Controller in combined mode.\n");