Hannah Williams (hannah.williams@intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13424
-gerrit
commit 9bfbf42a37ee3490548c543aa306e8fed795969f Author: Kumar, Gomathi gomathi.kumar@intel.com Date: Fri Aug 7 16:39:48 2015 +0530
intel/strago: Fix for Crossystem "wpsw_cur" status
The GPIO mapping was incorrect for wpsw_cur. The GPIOs for East community are in two ranges - 0: INT33FF:02 GPIOS [373 - 384] PINS [0 - 11] and 12: INT33FF:02 GPIOS [385 - 396] PINS [15 - 26] The discontinuity was not accounted for, hence the error.Original offset was 0x16 whereas it should be 0x13
TEST=Run crossystem and test wpsw_cur entry. If screw is present, it should be 1 and if not present, it should be 0
Change-Id: I29e19589b3a358a42818afbc6d017d6cbc6a9c4c Original-Signed-off-by: Kumar, Gomathi gomathi.kumar@intel.com Original-Reviewed-on: https://chromium-review.googlesource.com/291572 Original-Reviewed-by: Aaron Durbin adurbin@chromium.org Original-Commit-Queue: Icarus W Sparry icarus.w.sparry@intel.com --- src/mainboard/intel/strago/acpi/chromeos.asl | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/mainboard/intel/strago/acpi/chromeos.asl b/src/mainboard/intel/strago/acpi/chromeos.asl index 84c1313..c470ca3 100644 --- a/src/mainboard/intel/strago/acpi/chromeos.asl +++ b/src/mainboard/intel/strago/acpi/chromeos.asl @@ -23,11 +23,11 @@ * * Note: We need to encode gpios within the 4 separate banks * with the MMIO offset of each banks space. e.g. MF_ISH_GPIO_4 would be encoded - * as 0x10016 where the SUS offset (COMMUNITY_OFFSET_GPEAST) is 0x10000. + * as 0x10013 where the SUS offset (COMMUNITY_OFFSET_GPEAST) is 0x10000. */
Name(OIPG, Package() { /* No physical recovery button */ Package () { 0x0001, 0, 0xFFFFFFFF, "Braswell" }, - Package () { 0x0003, 1, 0x10016, "Braswell" }, + Package () { 0x0003, 1, 0x10013, "Braswell" }, })