Patrick Rudolph has submitted this change. ( https://review.coreboot.org/c/coreboot/+/37371 )
Change subject: ironlake: Fix compilation on x86_64 ......................................................................
ironlake: Fix compilation on x86_64
Use correct datasize to compile on x86_64. Tested on Lenovo T410 with additional x86_64 patches.
Change-Id: I213b2b1c5de174b5c14b67d1b437d19c656d13fd Signed-off-by: Patrick Rudolph siro@das-labor.org Reviewed-on: https://review.coreboot.org/c/coreboot/+/37371 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Angel Pons th3fanbus@gmail.com --- M src/northbridge/intel/ironlake/raminit.c M src/southbridge/intel/bd82x6x/me_common.c M src/southbridge/intel/ibexpeak/azalia.c M src/southbridge/intel/ibexpeak/lpc.c M src/southbridge/intel/ibexpeak/me.c M src/southbridge/intel/ibexpeak/sata.c M src/southbridge/intel/ibexpeak/smihandler.c 7 files changed, 9 insertions(+), 8 deletions(-)
Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved
diff --git a/src/northbridge/intel/ironlake/raminit.c b/src/northbridge/intel/ironlake/raminit.c index 68eefec..dfe9853 100644 --- a/src/northbridge/intel/ironlake/raminit.c +++ b/src/northbridge/intel/ironlake/raminit.c @@ -1941,7 +1941,7 @@
end = start + (ALIGN_DOWN(size + 4096, 4096)); for (addr = start; addr < end; addr += 64) - clflush((void *)addr); + clflush((void *)(uintptr_t)addr); }
static void clear_errors(void) @@ -1956,7 +1956,7 @@ u32 offset; u8 *base;
- base = (u8 *)(totalrank << 28); + base = (u8 *)(uintptr_t)(totalrank << 28); for (offset = 0; offset < 9 * 480; offset += 2) { write32(base + offset * 8, get_etalon2(flip, offset)); write32(base + offset * 8 + 4, get_etalon2(flip, offset)); diff --git a/src/southbridge/intel/bd82x6x/me_common.c b/src/southbridge/intel/bd82x6x/me_common.c index 8e38171..cdfd832 100644 --- a/src/southbridge/intel/bd82x6x/me_common.c +++ b/src/southbridge/intel/bd82x6x/me_common.c @@ -321,7 +321,8 @@
static inline void update_mei_base_address(void) { - mei_base_address = (u32 *)(pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf); + uint32_t reg32 = pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf; + mei_base_address = (u32 *)(uintptr_t)reg32; }
static inline bool is_mei_base_address_valid(void) diff --git a/src/southbridge/intel/ibexpeak/azalia.c b/src/southbridge/intel/ibexpeak/azalia.c index f686514..011bde6 100644 --- a/src/southbridge/intel/ibexpeak/azalia.c +++ b/src/southbridge/intel/ibexpeak/azalia.c @@ -212,7 +212,7 @@ // NOTE this will break as soon as the Azalia get's a bar above 4G. // Is there anything we can do about it? base = res2mmio(res, 0, 0); - printk(BIOS_DEBUG, "Azalia: base = %08x\n", (u32)base); + printk(BIOS_DEBUG, "Azalia: base = %p\n", base);
if (RCBA32(0x2030) & (1 << 31)) { reg32 = pci_read_config32(dev, 0x120); diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index 1ede5d6..55dcb02 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -573,7 +573,7 @@
/* Add it to SSDT. */ acpigen_write_scope("\"); - acpigen_write_name_dword("NVSA", (u32) gnvs); + acpigen_write_name_dword("NVSA", (uintptr_t) gnvs); acpigen_pop_len(); } } diff --git a/src/southbridge/intel/ibexpeak/me.c b/src/southbridge/intel/ibexpeak/me.c index 3477d8c..b355d9d 100644 --- a/src/southbridge/intel/ibexpeak/me.c +++ b/src/southbridge/intel/ibexpeak/me.c @@ -359,7 +359,7 @@ u32 reg32; u16 reg16;
- mei_base_address = (u32 *) + mei_base_address = (u32 *)(uintptr_t) (pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf);
/* S3 path will have hidden this device already */ diff --git a/src/southbridge/intel/ibexpeak/sata.c b/src/southbridge/intel/ibexpeak/sata.c index 2137149..d148570 100644 --- a/src/southbridge/intel/ibexpeak/sata.c +++ b/src/southbridge/intel/ibexpeak/sata.c @@ -90,7 +90,7 @@ pci_write_config32(dev, 0x98, 0x00590200);
/* Initialize AHCI memory-mapped space */ - abar = (u32 *)pci_read_config32(dev, PCI_BASE_ADDRESS_5); + abar = (u32 *)(uintptr_t)pci_read_config32(dev, PCI_BASE_ADDRESS_5); printk(BIOS_DEBUG, "ABAR: %p\n", abar); /* CAP (HBA Capabilities) : enable power management */ reg32 = read32(abar + 0x00); diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c index 3ca85c5..cce464b 100644 --- a/src/southbridge/intel/ibexpeak/smihandler.c +++ b/src/southbridge/intel/ibexpeak/smihandler.c @@ -150,7 +150,7 @@ smi_apmc_find_state_save(apm_cnt); if (state) { /* EBX in the state save contains the GNVS pointer */ - gnvs = (struct global_nvs *)((u32)state->rbx); + gnvs = (struct global_nvs *)(uintptr_t)((u32)state->rbx); if (smm_points_to_smram(gnvs, sizeof(*gnvs))) { printk(BIOS_ERR, "SMI#: ERROR: GNVS overlaps SMM\n"); return;