Werner Zeh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56032 )
Change subject: mb/siemens/mc_ehl: Add new mainboard based on elkhartlake_crb ......................................................................
mb/siemens/mc_ehl: Add new mainboard based on elkhartlake_crb
Add a new mainboard called mc_ehl which is based on Intel's 'elkhartlake_crb'. This commit simply copies the mainboard directory and adjusts the naming to match the new board's name. Follow-up commits will introduce the needed changes for the new mainboard.
Change-Id: Ia7c0616098046d975aa698910ac81f435d7882cb Signed-off-by: Werner Zeh werner.zeh@siemens.com --- A src/mainboard/siemens/mc_ehl/Kconfig A src/mainboard/siemens/mc_ehl/Kconfig.name A src/mainboard/siemens/mc_ehl/Makefile.inc A src/mainboard/siemens/mc_ehl/board_info.txt A src/mainboard/siemens/mc_ehl/bootblock.c A src/mainboard/siemens/mc_ehl/dsdt.asl A src/mainboard/siemens/mc_ehl/mainboard.c A src/mainboard/siemens/mc_ehl/romstage_fsp_params.c A src/mainboard/siemens/mc_ehl/spd/Makefile.inc A src/mainboard/siemens/mc_ehl/spd/empty.spd.hex A src/mainboard/siemens/mc_ehl/spd/mc_ehl.spd.hex A src/mainboard/siemens/mc_ehl/spd/spd.h A src/mainboard/siemens/mc_ehl/variants/baseboard/include/baseboard/variants.h A src/mainboard/siemens/mc_ehl/variants/mc_ehl1/Makefile.inc A src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb A src/mainboard/siemens/mc_ehl/variants/mc_ehl1/gpio.c A src/mainboard/siemens/mc_ehl/variants/mc_ehl1/memory.c 17 files changed, 860 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/56032/1
diff --git a/src/mainboard/siemens/mc_ehl/Kconfig b/src/mainboard/siemens/mc_ehl/Kconfig new file mode 100644 index 0000000..c2eb56e --- /dev/null +++ b/src/mainboard/siemens/mc_ehl/Kconfig @@ -0,0 +1,50 @@ +if BOARD_SIEMENS_MC_EHL + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_32768 + select DRIVERS_I2C_HID + select DRIVERS_INTEL_DPTF + select DRIVERS_I2C_GENERIC + select DRIVERS_SPI_ACPI + select DRIVERS_USB_ACPI + select EC_ACPI + select HAVE_SPD_IN_CBFS + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select SOC_INTEL_ELKHARTLAKE + +config MAINBOARD_DIR + string + default "siemens/mc_ehl" + +config VARIANT_DIR + string + default "mc_ehl1" if BOARD_SIEMENS_MC_EHL + +config MAINBOARD_PART_NUMBER + string + default "MC EHL" + +config MAINBOARD_FAMILY + string + default "Siemens EHL" + +config DEVICETREE + string + default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" + +config DIMM_SPD_SIZE + int + default 512 + +config VBOOT + select VBOOT_LID_SWITCH + select VBOOT_MOCK_SECDATA if !MAINBOARD_HAS_TPM2 + +config UART_FOR_CONSOLE + int + default 2 if INTEL_LPSS_UART_FOR_CONSOLE + default 0 + +endif diff --git a/src/mainboard/siemens/mc_ehl/Kconfig.name b/src/mainboard/siemens/mc_ehl/Kconfig.name new file mode 100644 index 0000000..0560d39 --- /dev/null +++ b/src/mainboard/siemens/mc_ehl/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_SIEMENS_MC_EHL + bool "MC EHL" diff --git a/src/mainboard/siemens/mc_ehl/Makefile.inc b/src/mainboard/siemens/mc_ehl/Makefile.inc new file mode 100644 index 0000000..382ec2e --- /dev/null +++ b/src/mainboard/siemens/mc_ehl/Makefile.inc @@ -0,0 +1,15 @@ +## SPDX-License-Identifier: GPL-2.0-only + +subdirs-y += spd + +bootblock-y += bootblock.c + +romstage-y += romstage_fsp_params.c + +ramstage-y += mainboard.c + +subdirs-y += variants/baseboard +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include + +subdirs-y += variants/$(VARIANT_DIR) diff --git a/src/mainboard/siemens/mc_ehl/board_info.txt b/src/mainboard/siemens/mc_ehl/board_info.txt new file mode 100644 index 0000000..72f257d --- /dev/null +++ b/src/mainboard/siemens/mc_ehl/board_info.txt @@ -0,0 +1,5 @@ +Vendor name: Siemens +Board name: MC EHL +Category: misc +ROM protocol: SPI +ROM socketed: n diff --git a/src/mainboard/siemens/mc_ehl/bootblock.c b/src/mainboard/siemens/mc_ehl/bootblock.c new file mode 100644 index 0000000..c39a8ff --- /dev/null +++ b/src/mainboard/siemens/mc_ehl/bootblock.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/variants.h> +#include <bootblock_common.h> +#include <soc/gpio.h> + +void bootblock_mainboard_init(void) +{ + const struct pad_config *pads; + size_t num; + + pads = variant_early_gpio_table(&num); + gpio_configure_pads(pads, num); +} diff --git a/src/mainboard/siemens/mc_ehl/dsdt.asl b/src/mainboard/siemens/mc_ehl/dsdt.asl new file mode 100644 index 0000000..5e93d62 --- /dev/null +++ b/src/mainboard/siemens/mc_ehl/dsdt.asl @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 /* OEM revision */ +) +{ + #include <acpi/dsdt_top.asl> + #include <soc/intel/common/block/acpi/acpi/platform.asl> + + /* global NVS and variables */ + #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> + + /* CPU */ + #include <cpu/intel/common/acpi/cpu.asl> + + Scope (_SB) { + Device (PCI0) + { + #include <soc/intel/common/block/acpi/acpi/northbridge.asl> + #include <soc/intel/elkhartlake/acpi/southbridge.asl> + } + } + + #include <southbridge/intel/common/acpi/sleepstates.asl> +} diff --git a/src/mainboard/siemens/mc_ehl/mainboard.c b/src/mainboard/siemens/mc_ehl/mainboard.c new file mode 100644 index 0000000..c63beb74 --- /dev/null +++ b/src/mainboard/siemens/mc_ehl/mainboard.c @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/variants.h> +#include <device/device.h> +#include <soc/gpio.h> + +static void mainboard_init(void *chip_info) +{ + const struct pad_config *pads; + size_t num; + + pads = variant_gpio_table(&num); + gpio_configure_pads(pads, num); +} + +struct chip_operations mainboard_ops = { + .init = mainboard_init, +}; diff --git a/src/mainboard/siemens/mc_ehl/romstage_fsp_params.c b/src/mainboard/siemens/mc_ehl/romstage_fsp_params.c new file mode 100644 index 0000000..259870a --- /dev/null +++ b/src/mainboard/siemens/mc_ehl/romstage_fsp_params.c @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/variants.h> +#include <soc/meminit.h> +#include <soc/romstage.h> + +void mainboard_memory_init_params(FSPM_UPD *memupd) +{ + static struct spd_info spd_info; + const struct mb_cfg *board_cfg = variant_memcfg_config(); + + /* TODO: Read the resistor strap to get number of memory segments */ + bool half_populated = false; + /* Initialize spd information for LPDDR4x board */ + spd_info.read_type = READ_SPD_CBFS; + spd_info.spd_spec.spd_index = 0x00; + + /* Initialize variant specific configurations */ + memcfg_init(&memupd->FspmConfig, board_cfg, &spd_info, half_populated); +} diff --git a/src/mainboard/siemens/mc_ehl/spd/Makefile.inc b/src/mainboard/siemens/mc_ehl/spd/Makefile.inc new file mode 100644 index 0000000..6d9e908 --- /dev/null +++ b/src/mainboard/siemens/mc_ehl/spd/Makefile.inc @@ -0,0 +1,3 @@ +## SPDX-License-Identifier: GPL-2.0-only + +SPD_SOURCES = mc_ehl # 0b000 diff --git a/src/mainboard/siemens/mc_ehl/spd/empty.spd.hex b/src/mainboard/siemens/mc_ehl/spd/empty.spd.hex new file mode 100644 index 0000000..67b46cd --- /dev/null +++ b/src/mainboard/siemens/mc_ehl/spd/empty.spd.hex @@ -0,0 +1,32 @@ +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/siemens/mc_ehl/spd/mc_ehl.spd.hex b/src/mainboard/siemens/mc_ehl/spd/mc_ehl.spd.hex new file mode 100644 index 0000000..71e5456 --- /dev/null +++ b/src/mainboard/siemens/mc_ehl/spd/mc_ehl.spd.hex @@ -0,0 +1,32 @@ +23 11 11 0E 15 21 90 08 00 40 00 00 02 22 00 00 +00 00 04 0F 92 54 05 00 87 00 90 A8 90 C0 08 60 +04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 E1 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 20 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/siemens/mc_ehl/spd/spd.h b/src/mainboard/siemens/mc_ehl/spd/spd.h new file mode 100644 index 0000000..f667e74 --- /dev/null +++ b/src/mainboard/siemens/mc_ehl/spd/spd.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef MAINBOARD_SPD_H +#define MAINBOARD_SPD_H + +#include <stdint.h> + +#define RCOMP_TARGET_PARAMS 0x5 + +void mainboard_fill_dq_map_ch0(u8 *dq_map_ptr); +void mainboard_fill_dq_map_ch1(u8 *dq_map_ptr); +void mainboard_fill_dqs_map_ch0(u8 *dqs_map_ptr); +void mainboard_fill_dqs_map_ch1(u8 *dqs_map_ptr); +void mainboard_fill_rcomp_res_data(u16 *rcomp_ptr); +void mainboard_fill_rcomp_strength_data(u16 *rcomp_strength_ptr); +#endif diff --git a/src/mainboard/siemens/mc_ehl/variants/baseboard/include/baseboard/variants.h b/src/mainboard/siemens/mc_ehl/variants/baseboard/include/baseboard/variants.h new file mode 100644 index 0000000..bf05765 --- /dev/null +++ b/src/mainboard/siemens/mc_ehl/variants/baseboard/include/baseboard/variants.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __BASEBOARD_VARIANTS_H__ +#define __BASEBOARD_VARIANTS_H__ + +#include <soc/gpio.h> +#include <soc/meminit.h> +#include <stdint.h> + +/* The following 2 functions return the gpio table and fill in the number + * of entries for each table. */ +const struct pad_config *variant_gpio_table(size_t *num); +const struct pad_config *variant_early_gpio_table(size_t *num); + +/* This function returns SPD related FSP-M mainboard configs */ +const struct mb_cfg *variant_memcfg_config(void); + +#endif /*__BASEBOARD_VARIANTS_H__ */ diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/Makefile.inc b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/Makefile.inc new file mode 100644 index 0000000..641e814 --- /dev/null +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/Makefile.inc @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += gpio.c +romstage-y += memory.c +ramstage-y += gpio.c diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb new file mode 100644 index 0000000..7c1d48a --- /dev/null +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb @@ -0,0 +1,259 @@ +chip soc/intel/elkhartlake + + device cpu_cluster 0 on + device lapic 0 on end + end + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "pmc_gpe0_dw0" = "GPP_B" + register "pmc_gpe0_dw1" = "GPP_F" + register "pmc_gpe0_dw2" = "GPP_E" + + # Enable heci1 communication + register "HeciEnabled" = "1" + + # FSP configuration + register "SaGv" = "SaGv_Enabled" + register "SmbusEnable" = "1" + register "Heci2Enable" = "1" + + # Display related UPDs + # Enable HPD for DDI ports C + register "DdiPortCHpd" = "1" + + # Enable DDC for DDI ports C + register "DdiPortCDdc" = "1" + + # USB related UPDs + register "usb2_ports[0]" = "USB2_PORT_MID(OC3)" # USB3/2 Type A port1 + register "usb2_ports[1]" = "USB2_PORT_MID(OC3)" # USB2 WWAN + register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # USB2 Bluetooth + register "usb2_ports[3]" = "USB2_PORT_MID(OC3)" # Type-C Port1 + register "usb2_ports[4]" = "USB2_PORT_MID(OC3)" # Type-C Port2 + register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Type-C Port3 + register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Type-C Port4 + register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # USB3/2 Type A port2 + register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # USB2 Type A port1 + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # USB2 Type A port2 + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC3)" # USB3/2 Type A port1 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC3)" # USB3/2 Type A port2 + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)" # USB3 WLAN + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" # UNUSED + + # Skip the CPU repalcement check + register "SkipCpuReplacementCheck" = "1" + + # PCIe root ports related UPDs + register "PcieRpEnable[0]" = "1" + register "PcieRpEnable[1]" = "1" + register "PcieRpEnable[2]" = "1" + register "PcieRpEnable[3]" = "1" + register "PcieRpEnable[4]" = "1" + register "PcieRpEnable[5]" = "1" + register "PcieRpEnable[6]" = "1" + + register "PcieClkSrcUsage[0]" = "0x00" + register "PcieClkSrcUsage[1]" = "0x06" + register "PcieClkSrcUsage[2]" = "0x04" + register "PcieClkSrcUsage[3]" = "0xFF" + register "PcieClkSrcUsage[4]" = "0xFF" + register "PcieClkSrcUsage[5]" = "0xFF" + + register "PcieClkSrcClkReq[0]" = "0x0" + register "PcieClkSrcClkReq[1]" = "0x1" + register "PcieClkSrcClkReq[2]" = "0x2" + register "PcieClkSrcClkReq[3]" = "0x3" + register "PcieClkSrcClkReq[4]" = "0x4" + register "PcieClkSrcClkReq[5]" = "0x5" + + # Storage (SATA/SDCARD/EMMC) related UPDs + register "SataSalpSupport" = "1" + register "SataPortsEnable[0]" = "1" + register "SataPortsEnable[1]" = "1" + register "SataPortsDevSlp[0]" = "0" + register "SataPortsDevSlp[1]" = "1" + + register "ScsEmmcHs400Enabled" = "1" + register "ScsEmmcDdr50Enabled" = "1" + register "SdCardPowerEnableActiveHigh" = "1" + + # LPSS Serial IO (I2C/UART/GSPI) related UPDs + register "SerialIoI2cMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoDisabled, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoPci, + [PchSerialIoIndexI2C5] = PchSerialIoDisabled, + [PchSerialIoIndexI2C6] = PchSerialIoPci, + [PchSerialIoIndexI2C7] = PchSerialIoPci, + }" + + register "SerialIoI2cPadsTermination" = "{ + [PchSerialIoIndexI2C0] = 1, + [PchSerialIoIndexI2C1] = 1, + [PchSerialIoIndexI2C2] = 1, + [PchSerialIoIndexI2C3] = 1, + [PchSerialIoIndexI2C4] = 1, + [PchSerialIoIndexI2C5] = 1, + [PchSerialIoIndexI2C6] = 1, + [PchSerialIoIndexI2C7] = 1, + }" + + register "SerialIoGSpiMode" = "{ + [PchSerialIoIndexGSPI0] = PchSerialIoDisabled, + [PchSerialIoIndexGSPI1] = PchSerialIoHidden, + [PchSerialIoIndexGSPI2] = PchSerialIoDisabled, + }" + + register "SerialIoGSpiCsEnable" = "{ + [PchSerialIoIndexGSPI0] = 1, + [PchSerialIoIndexGSPI1] = 1, + [PchSerialIoIndexGSPI2] = 1, + }" + + register "SerialIoGSpiCsMode" = "{ + [PchSerialIoIndexGSPI0] = 0, + [PchSerialIoIndexGSPI1] = 0, + [PchSerialIoIndexGSPI2] = 0, + }" + + register "SerialIoGSpiCsState" = "{ + [PchSerialIoIndexGSPI0] = 0, + [PchSerialIoIndexGSPI1] = 0, + [PchSerialIoIndexGSPI2] = 0, + }" + + register "SerialIoUartMode" = "{ + [PchSerialIoIndexUART0] = PchSerialIoDisabled, + [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART2] = PchSerialIoSkipInit, + }" + + register "SerialIoUartDmaEnable" = "{ + [PchSerialIoIndexUART0] = 1, + [PchSerialIoIndexUART1] = 1, + [PchSerialIoIndexUART2] = 1, + }" + + # TSN GBE related UPDs + register "PchTsnGbeLinkSpeed" = "Tsn_2_5_Gbps" + register "PchTsnGbeSgmiiEnable" = "1" + + # GPIO for SD card detect + register "sdcard_cd_gpio" = "GPP_G5" + + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + }" + + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Integrated Graphics Device + device pci 04.0 off end # SA Thermal device + device pci 08.0 off end # GNA + device pci 09.0 off end # CPU Intel Trace Hub + + device pci 10.0 on end # I2C6 + device pci 10.1 on end # I2C7 + device pci 10.5 on end # Integrated Error Handler + + device pci 11.0 off end # Intel PSE UART0 + device pci 11.1 off end # Intel PSE UART1 + device pci 11.2 off end # Intel PSE UART2 + device pci 11.3 off end # Intel PSE UART3 + device pci 11.4 off end # Intel PSE UART4 + device pci 11.5 off end # Intel PSE UART5 + device pci 11.6 off end # Intel PSE IS20 + device pci 11.7 off end # Intel PSE IS21 + + device pci 12.0 on end # GSPI2 + device pci 12.3 on end # Management Engine UMA Access + device pci 12.4 on end # Management Engine PTT DMA Controller + device pci 12.5 off end # UFS0 + device pci 12.7 off end # UFS1 + + device pci 13.0 off end # Intel PSE GSPI0 + device pci 13.1 off end # Intel PSE GSPI1 + device pci 13.2 off end # Intel PSE GSPI2 + device pci 13.3 off end # Intel PSE GSPI3 + device pci 13.4 off end # Intel PSE GPIO0 + device pci 13.5 off end # Intel PSE GPIO1 + + device pci 14.0 on end # USB3.1 xHCI + device pci 14.1 off end # USB3.1 xDCI (OTG) + + device pci 15.0 on end # I2C0 + device pci 15.1 on end # I2C1 + device pci 15.2 on end # I2C2 + device pci 15.3 on end # I2C3 + + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 on end # Management Engine Interface 2 + device pci 16.4 on end # Management Engine Interface 3 + device pci 16.5 on end # Management Engine Interface 4 + + device pci 17.0 on end # SATA + + device pci 18.0 off end # Intel PSE I2C7 + device pci 18.1 off end # Intel PSE CAN0 + device pci 18.2 off end # Intel PSE CAN1 + device pci 18.3 off end # Intel PSE QEP0 + device pci 18.4 off end # Intel PSE QEP1 + device pci 18.5 off end # Intel PSE QEP2 + device pci 18.6 off end # Intel PSE QEP3 + + device pci 19.0 on end # I2C4 + device pci 19.1 on end # I2C5 + device pci 19.2 on end # UART2 + + device pci 1a.0 on end # eMMC + device pci 1a.1 off end # SD + device pci 1a.3 off end # Intel Safety Island + + device pci 1b.0 off end # Intel PSE I2C0 + device pci 1b.1 off end # Intel PSE I2C1 + device pci 1b.2 off end # Intel PSE I2C2 + device pci 1b.3 off end # Intel PSE I2C3 + device pci 1b.4 off end # Intel PSE I2C4 + device pci 1b.5 off end # Intel PSE I2C5 + device pci 1b.6 off end # Intel PSE I2C6 + + device pci 1c.0 on end # RP1 (pcie0 single VC) + device pci 1c.1 on end # RP2 (pcie0 single VC) + device pci 1c.2 on end # RP3 (pcie0 single VC) + device pci 1c.3 on end # RP4 (pcie0 single VC) + device pci 1c.4 on end # RP5 (pcie1 multi VC) + device pci 1c.5 on end # RP6 (pcie2 multi VC) + device pci 1c.6 on end # RP7 (pcie3 multi VC) + + device pci 1d.0 off end # Intel PSE IPC (local host to PSE) + device pci 1d.1 on end # Intel PSE Time-Sensitive Networking GbE 0 + device pci 1d.2 on end # Intel PSE Time-Sensitive Networking GbE 1 + device pci 1d.3 off end # Intel PSE DMA0 + device pci 1d.4 off end # Intel PSE DMA1 + device pci 1d.5 off end # Intel PSE DMA2 + device pci 1d.6 off end # Intel PSE PWM + device pci 1d.7 off end # Intel PSE ADC + + device pci 1e.0 on end # UART0 + device pci 1e.1 on end # UART1 + device pci 1e.2 on end # GSPI0 + device pci 1e.3 on end # GSPI1 + device pci 1e.4 on end # PCH Time-Sensitive Networking GbE + device pci 1e.6 on end # HPET + device pci 1e.7 on end # IOAPIC + + device pci 1f.0 on end # eSPI Interface + device pci 1f.1 on end # P2SB + device pci 1f.2 hidden end # Power Management Controller + device pci 1f.3 off end # Intel cAVS/HDA + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # PCH SPI (flash & TPM) + device pci 1f.7 off end # PCH Intel Trace Hub + end +end diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/gpio.c b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/gpio.c new file mode 100644 index 0000000..9d17c80 --- /dev/null +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/gpio.c @@ -0,0 +1,280 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/variants.h> +#include <commonlib/helpers.h> + +/* Pad configuration in ramstage*/ +static const struct pad_config gpio_table[] = { +/*BT_RF_KILL_N*/ +PAD_CFG_GPO(GPP_E11, 1, DEEP), + +/*WIFI_RF_KILL_N*/ +PAD_CFG_GPO(GPP_E10, 1, DEEP), + +/*M.2_WLAN_PERST_N*/ +PAD_CFG_GPO(GPD7, 1, PLTRST), + +/*M.2_WLAN_SLP*/ +PAD_CFG_GPO(GPD9, 1, PLTRST), + +/*WIFI_WAKE_N*/ +PAD_CFG_GPI_SCI(GPP_F4, UP_5K, DEEP, LEVEL, INVERT), + +/*UART_BT_WAKE_N*/ +PAD_CFG_GPI_SCI(GPP_F20, NONE, DEEP, LEVEL, INVERT), + +/*ONBOARD_X4_PCIE_SLOT1_RESET_N*/ +PAD_CFG_GPO(GPD11, 1, PLTRST), + +/*ONBOARD_X4_PCIE_SLOT1_WAKE_N*/ +PAD_CFG_GPI_SCI(GPP_E2, NONE, DEEP, LEVEL, INVERT), + +/*M.2_WWAN_PWR_EN*/ +PAD_CFG_GPO(GPP_F21, 1, PLTRST), + +/*M.2_WWAN_RST_N*/ +PAD_CFG_GPO(GPP_V13, 1, PLTRST), + +/*M.2_WWAN_PE_RST_N*/ +PAD_CFG_GPO(GPP_B14, 1, PLTRST), + +/*M.2_WWAN_PE_WAKE_N*/ +PAD_CFG_GPO(GPP_B17, 1, PLTRST), + +/*M.2_WWAN_FCP_OFF_N*/ +PAD_CFG_GPO(GPP_E0, 1, PLTRST), + +/*M.2_SSD_SATA_DEVSLP_1*/ +PAD_CFG_NF(GPP_E8, NONE, DEEP, NF2), + +/*BC_PROCHOT_N*/ +PAD_CFG_GPI_SCI(GPP_B2, NONE, PLTRST, EDGE_SINGLE, INVERT), + +/*FPS_RST_N*/ +PAD_CFG_GPO(GPP_V14, 1, PLTRST), + +/*FPS_INT*/ +PAD_CFG_GPI_APIC(GPP_V15, NONE, PLTRST, LEVEL, NONE), + +/*CODEC_INT_N*/ +PAD_CFG_GPI(GPP_B15, NONE, PLTRST), + +/*TCH_PNL_PWR_EN*/ +PAD_CFG_GPO(GPP_B16, 1, PLTRST), + +/*THC0_SPI1_INT_N*/ +PAD_CFG_GPI_APIC(GPP_E17, NONE, PLTRST, LEVEL, INVERT), + +/*SPI_TPM_INT_N*/ +PAD_CFG_GPI_APIC(GPP_G19, NONE, DEEP, LEVEL, NONE), + +/*EMMC_CMD*/ +PAD_CFG_NF(GPP_V0, UP_20K, DEEP, NF1), + +/*EMMC_DATA0*/ +PAD_CFG_NF(GPP_V1, UP_20K, DEEP, NF1), + +/*EMMC_DATA1*/ +PAD_CFG_NF(GPP_V2, UP_20K, DEEP, NF1), + +/*EMMC_DATA2*/ +PAD_CFG_NF(GPP_V3, UP_20K, DEEP, NF1), + +/*EMMC_DATA3*/ +PAD_CFG_NF(GPP_V4, UP_20K, DEEP, NF1), + +/*EMMC_DATA4*/ +PAD_CFG_NF(GPP_V5, UP_20K, DEEP, NF1), + +/*EMMC_DATA5*/ +PAD_CFG_NF(GPP_V6, UP_20K, DEEP, NF1), + +/*EMMC_DATA6*/ +PAD_CFG_NF(GPP_V7, UP_20K, DEEP, NF1), + +/*EMMC_DATA7*/ +PAD_CFG_NF(GPP_V8, UP_20K, DEEP, NF1), + +/*EMMC_RCLK*/ +PAD_CFG_NF(GPP_V9, DN_20K, DEEP, NF1), + +/*EMMC_CLK*/ +PAD_CFG_NF(GPP_V10, DN_20K, DEEP, NF1), + +/*EMMC_RESET*/ +PAD_CFG_NF(GPP_V11, UP_20K, DEEP, NF1), + +/*ACPRESENT*/ +PAD_CFG_NF(GPD1, NONE, PLTRST, NF1), + +/*RGMII0_MDC*/ +PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), + +/*RGMII0_MDIO*/ +PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), + +/*RGMII0_INT*/ +PAD_CFG_NF(GPP_T4, NONE, DEEP, NF1), + +/*RGMII0_RESETB*/ +PAD_CFG_GPO(GPP_T5, 1, DEEP), + +/*RGMII0_AUXTS*/ +PAD_CFG_NF(GPP_T6, NONE, DEEP, NF1), + +/*RGMII0_PPS*/ +PAD_CFG_NF(GPP_T7, NONE, DEEP, NF1), + +/*RGMII0_PPS*/ +PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), + +/*RGMII0_PPS*/ +PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), + +/*RGMII0_PPS*/ +PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), + +/*RGMII0_PPS*/ +PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), + +/*RGMII0_PPS*/ +PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), + +/*RGMII0_PPS*/ +PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), + +/*RGMII0_PPS*/ +PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), + +/*RGMII0_PPS*/ +PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), + +/*RGMII0_PPS*/ +PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), + +/*RGMII0_PPS*/ +PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), + +/*RGMII0_PPS*/ +PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), + +/*RGMII0_PPS*/ +PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1), + +/*RGMII1_MDC*/ +PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), + +/*RGMII1_MDIO*/ +PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), + +/*RGMII1_INT*/ +PAD_CFG_NF(GPP_H0, NONE, DEEP, NF1), + +/*RGMII1_RESETB*/ +PAD_CFG_GPO(GPP_H1, 1, DEEP), + +/*RGMII1_AUXTS*/ +PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1), + +/*RGMII1_PPS*/ +PAD_CFG_NF(GPP_H3, NONE, DEEP, NF1), + +/*RGMII1_PPS*/ +PAD_CFG_NF(GPP_A11, NONE, DEEP, NF1), + +/*RGMII1_PPS*/ +PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), + +/*RGMII1_PPS*/ +PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), + +/*RGMII1_PPS*/ +PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), + +/*RGMII1_PPS*/ +PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), + +/*RGMII1_PPS*/ +PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), + +/*RGMII1_PPS*/ +PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1), + +/*RGMII1_PPS*/ +PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), + +/*RGMII1_PPS*/ +PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), + +/*RGMII1_PPS*/ +PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1), + +/*RGMII1_PPS*/ +PAD_CFG_NF(GPP_A21, NONE, DEEP, NF1), + +/*RGMII1_PPS*/ +PAD_CFG_NF(GPP_A22, NONE, DEEP, NF1), + +/*RGMII2_MDC*/ +PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), + +/*RGMII2_MDIO*/ +PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), + +/*RGMII2_INT*/ +PAD_CFG_NF(GPP_U0, NONE, DEEP, NF1), + +/*RGMII2_RESETB*/ +PAD_CFG_GPO(GPP_U1, 1, DEEP), +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { +/* UART1 RX */ +PAD_CFG_NF(GPP_C12, NONE, DEEP, NF4), + +/* UART1 TX */ +PAD_CFG_NF(GPP_C13, NONE, DEEP, NF4), + +/* UART2 RX */ +PAD_CFG_NF(GPP_C20, NONE, DEEP, NF4), + +/* UART2 TX */ +PAD_CFG_NF(GPP_C21, NONE, DEEP, NF4), + +/*WWAN_FCP_OFF_N*/ +PAD_CFG_GPO(GPP_E0, 1, PLTRST), + +/*WWAN_PWREN*/ +PAD_CFG_GPO(GPP_F21, 1, PLTRST), + +/*WWAN_PERST_N*/ +PAD_CFG_GPO(GPP_B14, 0, PLTRST), + +/*WWAN_RST_N*/ +PAD_CFG_GPO(GPP_V13, 0, PLTRST), + +/* LAN_WAKEB*/ +PAD_CFG_GPI_SCI(GPD2, NONE, DEEP, EDGE_SINGLE, INVERT), + +/*WWAN_RST_N*/ +PAD_CFG_GPO(GPP_V13, 0, PWROK), + +/*WWAN_PERST_N*/ +PAD_CFG_GPO(GPP_B14, 0, PWROK), + +/*WWAN_FCP_OFF_N*/ +PAD_CFG_GPO(GPP_E0, 0, PWROK), +}; + +const struct pad_config *variant_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/memory.c b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/memory.c new file mode 100644 index 0000000..7b7dad1 --- /dev/null +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/memory.c @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/variants.h> +#include <gpio.h> +#include <soc/meminit.h> +#include <soc/romstage.h> + +static const struct mb_cfg mc_ehl_lpddr4x_memcfg_cfg = { + + .dq_map[DDR_CH0] = { + {0xf, 0xf0}, + {0xf, 0xf0}, + {0xff, 0x0}, + {0x0, 0x0}, + {0x0, 0x0}, + {0x0, 0x0} + }, + + .dq_map[DDR_CH1] = { + {0xf, 0xf0}, + {0xf, 0xf0}, + {0xff, 0x0}, + {0x0, 0x0}, + {0x0, 0x0}, + {0x0, 0x0} + }, + + /* + * The dqs_map arrays map the ddr4 pins to the SoC pins + * for both channels. + * + * the index = pin number on ddr4 part + * the value = pin number on SoC + */ + .dqs_map[DDR_CH0] = {3, 0, 1, 2, 7, 4, 5, 6}, + .dqs_map[DDR_CH1] = {3, 0, 1, 2, 7, 4, 5, 6}, + + /* Baseboard uses 100, 100 and 100 rcomp resistors */ + .rcomp_resistor = {100, 100, 100}, + + .rcomp_targets = {60, 40, 30, 20, 30}, + + /* LPDDR4x does not allow interleaved memory */ + .dq_pins_interleaved = 0, + + /* Baseboard is using config 2 for vref_ca */ + .vref_ca_config = 2, + + /* Enable Early Command Training */ + .ect = 1, + + /* Set Board Type */ + .UserBd = BOARD_TYPE_MOBILE, +}; + +const struct mb_cfg *variant_memcfg_config(void) +{ + return &mc_ehl_lpddr4x_memcfg_cfg; +}