Paul Menzel (paulepanter@users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5927
-gerrit
commit b91bb1bc4f92444b687eaedeb9fcc11093c78f34 Author: Paul Menzel paulepanter@users.sourceforge.net Date: Thu Jun 5 22:45:35 2014 +0200
lenovo/x60/i915.c: Place GTT below top of memory
PGETBL_CTL differs between Video BIOS (-) and native graphics init (+).
- PGETBL_CTL: 0x3ffc0001 + PGETBL_CTL: 0x3f800001
Currently it is set above the base address of stolen memory. The Video BIOS sets it below. The Linux Intel driver expects it to be below top of memory so do it this way.
Also adapt setgtt() to use the new address.
There is still an error thrown but 3D works with Linux 3.12+.
Change-Id: I0a5b04c2c5300f5056cb48075aa5804984bc9948 Signed-off-by: Paul Menzel paulepanter@users.sourceforge.net --- src/mainboard/lenovo/x60/i915.c | 14 +++++++++++--- src/mainboard/lenovo/x60/i915_reg.h | 2 ++ 2 files changed, 13 insertions(+), 3 deletions(-)
diff --git a/src/mainboard/lenovo/x60/i915.c b/src/mainboard/lenovo/x60/i915.c index 43efb08..640dcda 100644 --- a/src/mainboard/lenovo/x60/i915.c +++ b/src/mainboard/lenovo/x60/i915.c @@ -139,11 +139,19 @@ int gtt_setup(unsigned int mmiobase); int gtt_setup(unsigned int mmiobase) { unsigned long pgetbl_ctl; + unsigned long tom;
pgetbl_ctl = read32(mmiobase + PGETBL_CTL) & ~PGETBL_ENABLED; pgetbl_ctl |= PGETBL_ENABLED;
- pgetbl_ctl |= pci_read_config32(dev_find_slot(0, PCI_DEVFN(2,0)), BSM) & 0xfff00000; + /* The Video BIOS places the GTT right below top of memory. + * It is not documented in the datasheet, but the Intel developers said + * that it is normally placed there. + * + * TODO: Add option table value to make the GTT size runtime configurable. + */ + tom = pci_read_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), TOLUD) << 24; + pgetbl_ctl |= tom - 256 * KiB; pgetbl_ctl |= PGETBL_GTT_SIZE_256KB << 1; /* set GTT to 256kb */
write32(mmiobase + GFX_FLSH_CNTL, 0); @@ -359,11 +367,11 @@ int i915lightup(unsigned int pphysbase, unsigned int piobase, return 0; }
- setgtt(0, FRAME_BUFFER_PAGES, physbase, 4096); - temp = READ32(PGETBL_CTL); printk(BIOS_INFO, "GTT PGETBL_CTL register: 0x%lx\n", temp);
+ setgtt(0, FRAME_BUFFER_PAGES, temp & 0xfffff000, 4096); + if (temp & 1) printk(BIOS_INFO, "GTT enabled.\n"); else diff --git a/src/mainboard/lenovo/x60/i915_reg.h b/src/mainboard/lenovo/x60/i915_reg.h index 382b822..a12ba55 100644 --- a/src/mainboard/lenovo/x60/i915_reg.h +++ b/src/mainboard/lenovo/x60/i915_reg.h @@ -27,6 +27,8 @@
#define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a)))
+#define TOLUD 0x9c + /* * The Bridge device's PCI config space has information about the * fb aperture size and the amount of pre-reserved memory.