Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60731 )
Change subject: soc/intel/adl: Replace dt `HeciEnabled` by `CSE disable` config ......................................................................
soc/intel/adl: Replace dt `HeciEnabled` by `CSE disable` config
Lists of changes:
1. Drop `HeciEnabled` from dt and dt chip configuration. 2. Replace all logic that disables CSE based on the `HeciEnabled` chip config with `DISABLE_CSE_AT_PRE_BOOT` config.
Mainboards that choose to make CSE enable during boot don't select `cse disable` config.
Signed-off-by: Subrata Banik subratabanik@google.com Change-Id: Ie673e634fbc0bdece419c379d417b08dfb4819e2 --- M src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb M src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb M src/mainboard/intel/adlrvp/devicetree.cb M src/mainboard/intel/adlrvp/devicetree_m.cb M src/mainboard/intel/adlrvp/devicetree_n.cb M src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/smihandler.c 8 files changed, 1 insertion(+), 27 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/60731/1
diff --git a/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb index 4662b95..2ba2889 100644 --- a/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb @@ -17,9 +17,6 @@ # DPTF enable register "dptf_enable" = "1"
- # Enable heci communication - register "HeciEnabled" = "1" - # Enable CNVi BT register "CnviBtCore" = "true"
diff --git a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb index b330e98..16517c5 100644 --- a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb @@ -19,9 +19,6 @@
register "tcc_offset" = "10" # TCC of 90
- # Enable heci communication - register "HeciEnabled" = "1" - # Enable CNVi BT register "CnviBtCore" = "true"
diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb index 2c45e85..a272c1b 100644 --- a/src/mainboard/intel/adlrvp/devicetree.cb +++ b/src/mainboard/intel/adlrvp/devicetree.cb @@ -8,9 +8,6 @@ register "pmc_gpe0_dw1" = "GPP_D" register "pmc_gpe0_dw2" = "GPP_E"
- # Enable HECI1 interface - register "HeciEnabled" = "1" - # FSP configuration
# Enable CNVi BT diff --git a/src/mainboard/intel/adlrvp/devicetree_m.cb b/src/mainboard/intel/adlrvp/devicetree_m.cb index b73ded1..7707bf5 100644 --- a/src/mainboard/intel/adlrvp/devicetree_m.cb +++ b/src/mainboard/intel/adlrvp/devicetree_m.cb @@ -18,9 +18,6 @@ register "pmc_gpe0_dw1" = "GPP_D" register "pmc_gpe0_dw2" = "GPP_E"
- # Enable HECI1 communication - register "HeciEnabled" = "1" - # FSP configuration register "usb2_ports[0]" = "USB2_PORT_MID(OC1)" # Type-C port 0 register "usb2_ports[1]" = "USB2_PORT_MID(OC1)" # Type-C port 1 diff --git a/src/mainboard/intel/adlrvp/devicetree_n.cb b/src/mainboard/intel/adlrvp/devicetree_n.cb index cec0422..f013596 100644 --- a/src/mainboard/intel/adlrvp/devicetree_n.cb +++ b/src/mainboard/intel/adlrvp/devicetree_n.cb @@ -8,9 +8,6 @@ register "pmc_gpe0_dw1" = "GPP_D" register "pmc_gpe0_dw2" = "GPP_E"
- # Enable HECI1 interface - register "HeciEnabled" = "1" - # FSP configuration
# Enable CNVi BT diff --git a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb index 5757392..63d3da4 100644 --- a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb @@ -16,9 +16,6 @@ register "TcssAuxOri" = "1" register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_A5, .pad_auxn_dc = GPP_A6}"
- # Enable heci communication - register "HeciEnabled" = "1" - # Enable CNVi Bluetooth register "CnviBtCore" = "true"
diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index 771fc5a..5b52214 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -310,10 +310,6 @@ } IgdDvmt50PreAlloc; uint8_t SkipExtGfxScan;
- /* HeciEnabled decides the state of Heci1 at end of boot - * Setting to 0 (default) disables Heci1 and hides the device from OS */ - uint8_t HeciEnabled; - /* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */ uint8_t eist_enable;
diff --git a/src/soc/intel/alderlake/smihandler.c b/src/soc/intel/alderlake/smihandler.c index 5b53038..f842ddd 100644 --- a/src/soc/intel/alderlake/smihandler.c +++ b/src/soc/intel/alderlake/smihandler.c @@ -16,11 +16,7 @@ */ void smihandler_soc_at_finalize(void) { - const struct soc_intel_alderlake_config *config; - - config = config_of_soc(); - - if (!config->HeciEnabled && CONFIG(HECI_DISABLE_USING_SMM)) + if (CONFIG(DISABLE_CSE_AT_PRE_BOOT) && CONFIG(HECI_DISABLE_USING_SMM)) heci_disable(); }