[coreboot-gerrit] New patch to review for coreboot: skylake: honor pcie root port settings already in chip.h

[Patrick Georgi]

Patrick Georgi ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10987

-gerrit

commit 44defe03bb81c056eec5307abe645409cc498abb
Author: Aaron Durbin 
Date:   Mon Jul 13 14:03:41 2015 -0500

skylake: honor pcie root port settings already in chip.h

For some unkonwn reason the pcie root port settings weren't
    being honored in the device tree. Fix that omission.

BUG=chrome-os-partner:41861
    BRANCH=None
    TEST=Built with CONFIG_DISPLAY_UPD_DATA and noted devicetree
         settings were being honored.

Change-Id: Id880eca57544efb13f5cbbc06b2634c86b7c5d29
    Signed-off-by: Patrick Georgi 
    Original-Commit-Id: 2d00e68ce6cfcb3d63d69848f4a8ce232f6c1257
    Original-Change-Id: Idd37d65374842294f4b0c91eb841c6d1d93e92ee
    Original-Signed-off-by: Aaron Durbin 
    Original-Reviewed-on: https://chromium-review.googlesource.com/285027
    Original-Reviewed-by: Duncan Laurie 
---
 src/soc/intel/skylake/romstage/romstage.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c
index 6d1310a..4230664 100644
--- a/src/soc/intel/skylake/romstage/romstage.c
+++ b/src/soc/intel/skylake/romstage/romstage.c
@@ -90,6 +90,13 @@ void soc_memory_init_params(MEMORY_INIT_UPD *params)
    for (i = 0; i < PchSerialIoIndexMax; i++)
    	params->SerialIoDevMode[i] = config->SerialIoDevMode[i];

+	memcpy(params->PcieRpEnable, config->PcieRpEnable,
+		sizeof(params->PcieRpEnable));
+	memcpy(params->PcieRpClkReqSupport, config->PcieRpClkReqSupport,
+		sizeof(params->PcieRpClkReqSupport));
+	memcpy(params->PcieRpClkReqNumber, config->PcieRpClkReqNumber,
+		sizeof(params->PcieRpClkReqNumber));
+
    params->MmioSize = 0x800; /* 2GB in MB */
    params->TsegSize = CONFIG_SMM_TSEG_SIZE;
    params->IedSize = config->IedSize;