[coreboot-gerrit] Change in coreboot[master]: soc/intel/jasperlake: Add a workaround for cnvi

[Tim Wawrzynczak (Code Review)]

Attention is currently required from: Jamie Chen, Subrata Banik, Tim Wawrzynczak, Karthik Ramasubramanian.
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63675 )

Change subject: soc/intel/jasperlake: Add a workaround for cnvi
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Patch Set 1: Code-Review+1

(1 comment)

File src/soc/intel/jasperlake/chip.h:

https://review.coreboot.org/c/coreboot/+/63675/comment/4ba8a26c_2a915ea9 
PS1, Line 424: 	/*
             : 	 * This is a workaround to mitigate higher SoC power consumption in S0ix
             : 	 * when the CNVI has background activity.
             : 	 *
             : 	 * This setting can only be enabled if xtalsdqdis (Bit 22) in cppmvric1
             : 	 * register is 1.
             : 	 * 1: Enabled ; 0: Disabled
             : 	 */
             : 	bool cnvi_s0ix_wa;
Can we also please mention

- Setting this on a system that supports S0i3 (e.g. external bypass rails) will apparently break S0ix.
 - Affected Intel wireless chipsets
 - Tradeoff of fewer wakes vs. higher power