[coreboot-gerrit] Change in coreboot[master]: mb/google/zork: Add support for GPIO configuration on sleep path

[Furquan Shaikh (Code Review)]

Hello Aaron Durbin,

I'd like you to do a code review. Please visit

https://review.coreboot.org/c/coreboot/+/42932

to review the following change.

Change subject: mb/google/zork: Add support for GPIO configuration on sleep path
......................................................................

mb/google/zork: Add support for GPIO configuration on sleep path

This change adds support to configure GPIOs on the sleep path. This is
required to turn off power to devices that do not act as wake sources
and to assert reset to devices.

Currently, variant_sleep_gpio_table() returns an empty table by
default. In the following changes, entries will be added to
gpio_sleep_table.

BUG=b:152582706

Signed-off-by: Furquan Shaikh 
Change-Id: I7286cbf165024bdd81f8748e525542dce8dd8702
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+...
Tested-by: Furquan Shaikh 
Reviewed-by: Aaron Durbin 
Commit-Queue: Furquan Shaikh 
---
M src/mainboard/google/zork/smihandler.c
M src/mainboard/google/zork/variants/baseboard/Makefile.inc
M src/mainboard/google/zork/variants/baseboard/gpio_baseboard_common.c
M src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h
4 files changed, 27 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/42932/1

diff --git a/src/mainboard/google/zork/smihandler.c b/src/mainboard/google/zork/smihandler.c
index 7c88215..12a3b64 100644
--- a/src/mainboard/google/zork/smihandler.c
+++ b/src/mainboard/google/zork/smihandler.c
@@ -1,5 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
+
 #include <acpi/acpi.h>
+#include <baseboard/variants.h>
 #include <cpu/x86/smm.h>
 #include <ec/google/chromeec/smm.h>
 #include <gpio.h>
@@ -15,10 +17,17 @@
 }
 void mainboard_smi_sleep(u8 slp_typ)
 {
+	size_t num_gpios;
+	const struct soc_amd_gpio *gpios;
+
    if (CONFIG(EC_GOOGLE_CHROMEEC))
    	chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS,
    				MAINBOARD_EC_S5_WAKE_EVENTS);
+
+	gpios = variant_sleep_gpio_table(&num_gpios, slp_typ);
+	program_gpios(gpios, num_gpios);
 }
+
 int mainboard_smi_apmc(u8 apmc)
 {
    if (CONFIG(EC_GOOGLE_CHROMEEC))
diff --git a/src/mainboard/google/zork/variants/baseboard/Makefile.inc b/src/mainboard/google/zork/variants/baseboard/Makefile.inc
index 7e4ccae..0f025e0 100644
--- a/src/mainboard/google/zork/variants/baseboard/Makefile.inc
+++ b/src/mainboard/google/zork/variants/baseboard/Makefile.inc
@@ -24,6 +24,8 @@
 ramstage-y += helpers.c
 ramstage-y += tpm_tis.c

+smm-y += gpio_baseboard_common.c
+
 # Add OEM ID table
 ifeq ($(CONFIG_USE_OEM_BIN),y)
 cbfs-files-y += oem.bin
diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_common.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_common.c
index a4e8648..614e837 100644
--- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_common.c
+++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_common.c
@@ -30,3 +30,12 @@
    *size = ARRAY_SIZE(early_gpio_table);
    return early_gpio_table;
 }
+
+static const struct soc_amd_gpio gpio_sleep_table[] = {
+};
+
+const __weak struct soc_amd_gpio *variant_sleep_gpio_table(size_t *size, int slp_typ)
+{
+	*size = ARRAY_SIZE(gpio_sleep_table);
+	return gpio_sleep_table;
+}
diff --git a/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h
index 4f8f225..6c5b95b 100644
--- a/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h
+++ b/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h
@@ -25,6 +25,13 @@
  * configuration provided by variant_base_gpio_table().
  */
 const struct soc_amd_gpio *variant_override_gpio_table(size_t *size);
+
+/*
+ * This function provides GPIO table for the pads that need to be configured when entering
+ * sleep.
+ */
+const struct soc_amd_gpio *variant_sleep_gpio_table(size_t *size, int slp_typ);
+
 void variant_romstage_entry(void);
 /* Modify devictree settings during ramstage. */
 void variant_devtree_update(void);