Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Mohan Viswanathan, Name of user not set #1004133, Al Hirani, Avinash Alevoor, Rob Barnes, Fred Reitberger, Felix Held.
Jason Glenesk has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61462 )
Change subject: soc/amd/common/block/psp: add PSP command
......................................................................
Patch Set 7:
(3 comments)
File src/soc/amd/common/block/psp/psp_def.h:
https://review.coreboot.org/c/coreboot/+/61462/comment/4a6ce2b7_b81a7e7d
PS6, Line 30: #define CORE_2_PSP_MSG_38_FUSE_SPL BIT(3)
This should be BIT(12). PSP sets bit 12 to indicate fusing is required.
Done
File src/soc/amd/common/block/psp/psp_gen2.c:
https://review.coreboot.org/c/coreboot/+/61462/comment/4b17120e_3d3bd65d
PS5, Line 124: static u32 soc_read_c2p38(void)
commented on https://review.coreboot.org/c/coreboot/+/60968/11/src/soc/amd/common/block/p.... […]
Done
https://review.coreboot.org/c/coreboot/+/61462/comment/e1149d4d_884876f8
PS5, Line 128: return 0;
not sure if this will do the right thing in the error case; the other implementation linked above mi […]
Done
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