[coreboot-gerrit] Change in coreboot[master]: mb/google/drallion/variants/drallion: Set PCH Thermal Trip point to 77°C

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39395 )

Change subject: mb/google/drallion/variants/drallion: Set PCH Thermal Trip point to 77°C
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mb/google/drallion/variants/drallion: Set PCH Thermal Trip point to 77°C

PMC logic shuts down the PCH thermal sensor when CPU is in a C-state and
DTS Temp <= Low Temp Threshold (LTT) in case of Dynamic Thermal shutdown
when S0ix is enabled.

BUG=None
BRANCH=None
TEST=Verified Thermal Device(B0: D18: F0) TSPM offset 0x1c [LTT (8:0)]
value is 0xFE on Drallion.

Change-Id: I146068d8019859be1c27e2a8174dfe7909d42d0a
Signed-off-by: Sumeet Pawnikar 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39395
Tested-by: build bot (Jenkins) 
Reviewed-by: Paul Menzel 
Reviewed-by: Bora Guvendik 
---
M src/mainboard/google/drallion/variants/drallion/devicetree.cb
1 file changed, 3 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Paul Menzel: Looks good to me, but someone else must approve
  Bora Guvendik: Looks good to me, approved

diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb
index d0006d6..60be8c9 100644
--- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb
+++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb
@@ -175,6 +175,9 @@

register "tcc_offset" = "1"

+	# PCH Thermal Trip Temperature in deg C
+	register "common_soc_config.pch_thermal_trip" = "77"
+
    register "common_soc_config" = "{
    	.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
    	.i2c[0] = {