[coreboot-gerrit] Change in ...coreboot[master]: soc/intel/cannonlake: Add FSP SPI CS options

[Shelley Chen (Code Review)]

Shelley Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32793

Change subject: soc/intel/cannonlake: Add FSP SPI CS options
......................................................................

soc/intel/cannonlake: Add FSP SPI CS options

Allow setting of SPI CS FSP options.

BUG=b:130329260
BRANCH=None
TEST=boot up and make sure these options are set as expected in
     fsp_params.

Change-Id: I3a77f8bd3b447bec5a2807a2afab723aa500f146
Signed-off-by: Shelley Chen 
---
M src/soc/intel/cannonlake/chip.h
M src/soc/intel/cannonlake/fsp_params.c
2 files changed, 34 insertions(+), 9 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/32793/1

diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h
index b17df4b..65009f0 100644
--- a/src/soc/intel/cannonlake/chip.h
+++ b/src/soc/intel/cannonlake/chip.h
@@ -21,7 +21,6 @@
 #include <intelblocks/chip.h>
 #include <drivers/i2c/designware/dw_i2c.h>
 #include <intelblocks/gspi.h>
-#include <smbios.h>
 #include <stdint.h>
 #include <soc/gpio.h>
 #include <soc/pch.h>
@@ -338,6 +337,27 @@
     */
    uint8_t SerialIoDevMode[PchSerialIoIndexMAX];

+	/*
+	 * Chip Select Polarity
+	 * 0 : PchSerialIoCsActiveLow
+	 * 1 : PchSerialIoCsActiveHigh
+	 */
+	uint8_t SerialIoSpi0CsPolarity[2];
+	uint8_t SerialIoSpi1CsPolarity[2];
+	/*
+	 * Chip Select Enable
+	 * 0 : Disabled
+	 * 1 : Enabled
+	 */
+	uint8_t SerialIoSpi0CsEnable[2];
+	uint8_t SerialIoSpi1CsEnable[2];
+	/*
+	 * Default Chip Select Output
+	 * 0 : CS0
+	 * 1 : CS1
+	 */
+	uint8_t SerialIoSpiDefaultCsOutput[2];
+
    /* GPIO SD card detect pin */
    unsigned int sdcard_cd_gpio;

@@ -401,10 +421,6 @@

/* Unlock all GPIO Pads */
    uint8_t PchUnlockGpioPads;
-
-	/* Enable GBE wakeup */
-	uint8_t LanWakeFromDeepSx;
-	uint8_t WolEnableOverride;
 };

typedef struct soc_intel_cannonlake_config config_t;
diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c
index cc01d10..e9043e2 100644
--- a/src/soc/intel/cannonlake/fsp_params.c
+++ b/src/soc/intel/cannonlake/fsp_params.c
@@ -86,6 +86,19 @@
    	params->SerialIoUartMode[i] =
    			get_param_value(config, dev_offset);
    }
+
+	params->SerialIoSpi0CsPolarity[0] = config->SerialIoSpi0CsPolarity[0];
+	params->SerialIoSpi0CsPolarity[1] = config->SerialIoSpi0CsPolarity[1];
+	params->SerialIoSpi1CsPolarity[0] = config->SerialIoSpi1CsPolarity[0];
+	params->SerialIoSpi1CsPolarity[1] = config->SerialIoSpi1CsPolarity[1];
+	params->SerialIoSpi0CsEnable[0] = config->SerialIoSpi0CsEnable[0];
+	params->SerialIoSpi0CsEnable[1] = config->SerialIoSpi0CsEnable[1];
+	params->SerialIoSpi1CsEnable[0] = config->SerialIoSpi1CsEnable[0];
+	params->SerialIoSpi1CsEnable[1] = config->SerialIoSpi1CsEnable[1];
+	params->SerialIoSpiDefaultCsOutput[0] =
+		config->SerialIoSpiDefaultCsOutput[0];
+	params->SerialIoSpiDefaultCsOutput[1] =
+		config->SerialIoSpiDefaultCsOutput[1];
 }
 #else
 static void parse_devicetree_param(const config_t *config, FSP_S_CONFIG *params)
@@ -212,10 +225,6 @@
    params->DdiPortDDdc = config->DdiPortDDdc;
    params->DdiPortFDdc = config->DdiPortFDdc;

-	/* WOL */
-	params->PchPmPcieWakeFromDeepSx = config->LanWakeFromDeepSx;
-	params->PchPmWolEnableOverride = config->WolEnableOverride;
-
    /* S0ix */
    params->PchPmSlpS0Enable = config->s0ix_enable;