[coreboot-gerrit] Change in coreboot[master]: mb/google/dedede/var/drawcia: Add MIPI camera support

[Sugnan Prabhu S (Code Review)]

Sugnan Prabhu S has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44939 )

Change subject: mb/google/dedede/var/drawcia: Add MIPI camera support
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Patch Set 13:

(1 comment)

https://review.coreboot.org/c/coreboot/+/44939/10/src/mainboard/google/deded... 
File src/mainboard/google/dedede/variants/drawcia/overridetree.cb:

https://review.coreboot.org/c/coreboot/+/44939/10/src/mainboard/google/deded... 
PS10, Line 277: 				register "pr0" = ""\_SB.PCI0.I2C3.CAM1.PRIC""
> Okay, then it sounds like at least the userspace now does the right thing and doesn't attempt to use […]

@Karthik/@Tomasz,

As per my understand, you would want to have a different or subset of power sequence for the EEPROM/NVM0, which is already possible if we set has_power_resource and define the power sequence just like the UFC,WFC and not define pr0

register "has_power_resource" = "1"
#Controls
register "clk_panel.clks[0].clknum" = "1" #IMGCLKOUT_1
register "clk_panel.clks[0].freq" = "1" #19.2 Mhz
register "gpio_panel.gpio[0].gpio_num" = "GPP_D13" #power_enable_2p8
register "gpio_panel.gpio[1].gpio_num" = "GPP_D14" #power_enable_1p2
#_ON
register "on_seq.ops_cnt" = "5"
register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)"
register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 5)"
register "on_seq.ops[2]" = "SEQ_OPS_GPIO_ENABLE(1, 5)"