Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49082 )
Change subject: [NOTFORMERGE_YET]soc/intel/xeon_sp/cpx: Hook up microcode update ......................................................................
[NOTFORMERGE_YET]soc/intel/xeon_sp/cpx: Hook up microcode update
Update the Intel microcode repo to the microcode-20201118 tag.
The CPX microcode updates hit the microcode repo as of 20201110 release.
Some CPUs seem to have stability issues with these newer microcode updates: See https://review.coreboot.org/c/coreboot/+/47914 for discussion on that. So it might be better to wait until Intel fixes those.
Change-Id: Ie1776925e7f6c1523d6b398a90949c5bbd471203 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M 3rdparty/intel-microcode M src/soc/intel/xeon_sp/cpx/Kconfig M src/soc/intel/xeon_sp/cpx/Makefile.inc 3 files changed, 3 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/49082/1
diff --git a/3rdparty/intel-microcode b/3rdparty/intel-microcode index 0e4288f..49bb67f 160000 --- a/3rdparty/intel-microcode +++ b/3rdparty/intel-microcode @@ -1 +1 @@ -Subproject commit 0e4288f81f806620c65f70ee2bcf94b69d574096 +Subproject commit 49bb67f32a2e3e631ba1a9a73da1c52e1cac7fd9 diff --git a/src/soc/intel/xeon_sp/cpx/Kconfig b/src/soc/intel/xeon_sp/cpx/Kconfig index 7b583cd..cd4384b 100644 --- a/src/soc/intel/xeon_sp/cpx/Kconfig +++ b/src/soc/intel/xeon_sp/cpx/Kconfig @@ -2,10 +2,6 @@
if SOC_INTEL_COOPERLAKE_SP
-config SOC_SPECIFIC_OPTIONS - def_bool y - select MICROCODE_BLOB_NOT_HOOKED_UP - config FSP_HEADER_PATH string "Location of FSP headers" depends on MAINBOARD_USES_FSP2_0 diff --git a/src/soc/intel/xeon_sp/cpx/Makefile.inc b/src/soc/intel/xeon_sp/cpx/Makefile.inc index a5c6848..97c156c 100644 --- a/src/soc/intel/xeon_sp/cpx/Makefile.inc +++ b/src/soc/intel/xeon_sp/cpx/Makefile.inc @@ -19,4 +19,6 @@
CPPFLAGS_common += -I$(src)/soc/intel/xeon_sp/cpx/include -I$(src)/soc/intel/xeon_sp/cpx
+cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-55-0b + endif ## CONFIG_SOC_INTEL_COOPERLAKE_SP