HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32407 )
Change subject: soc/amd/picasso: Create picasso as a copy of stoneyridge ......................................................................
Patch Set 3: Code-Review+1
(14 comments)
https://review.coreboot.org/#/c/32407/3/src/soc/amd/picasso/Kconfig File src/soc/amd/picasso/Kconfig:
https://review.coreboot.org/#/c/32407/3/src/soc/amd/picasso/Kconfig@16 PS3, Line 16: STONEYRIDGE looks like it is intentional
https://review.coreboot.org/#/c/32407/3/src/soc/amd/picasso/chip.c File src/soc/amd/picasso/chip.c:
https://review.coreboot.org/#/c/32407/3/src/soc/amd/picasso/chip.c@17 PS3, Line 17: include <console/console.h> if I'm not wrong, this is not used
https://review.coreboot.org/#/c/32407/3/src/soc/amd/picasso/chip.c@35 PS3, Line 35: stoneyridge is it intentional?
https://review.coreboot.org/#/c/32407/3/src/soc/amd/picasso/chip.c@42 PS3, Line 42: stoney is it intentional?
https://review.coreboot.org/#/c/32407/3/src/soc/amd/picasso/enable_usbdebug.... File src/soc/amd/picasso/enable_usbdebug.c:
https://review.coreboot.org/#/c/32407/3/src/soc/amd/picasso/enable_usbdebug.... PS3, Line 22: <device/pci_def.h maybe not used?
https://review.coreboot.org/#/c/32407/3/src/soc/amd/picasso/include/soc/nort... File src/soc/amd/picasso/include/soc/northbridge.h:
https://review.coreboot.org/#/c/32407/3/src/soc/amd/picasso/include/soc/nort... PS3, Line 17: PI_STONEYRIDGE_NORTHBRIDGE_H ?
https://review.coreboot.org/#/c/32407/3/src/soc/amd/picasso/include/soc/nvs.... File src/soc/amd/picasso/include/soc/nvs.h:
https://review.coreboot.org/#/c/32407/3/src/soc/amd/picasso/include/soc/nvs.... PS3, Line 20: stoneyridge is it intentional?
https://review.coreboot.org/#/c/32407/3/src/soc/amd/picasso/include/soc/nvs.... PS3, Line 24: __SOC_STONEYRIDGE_NVS_H__ ?
https://review.coreboot.org/#/c/32407/3/src/soc/amd/picasso/include/soc/pci_... File src/soc/amd/picasso/include/soc/pci_devs.h:
https://review.coreboot.org/#/c/32407/3/src/soc/amd/picasso/include/soc/pci_... PS3, Line 16: __PI_STONEYRIDGE_PCI_DEVS_H__ : #define __PI_STONEYRIDGE_PCI_DEVS_H__ ?
https://review.coreboot.org/#/c/32407/3/src/soc/amd/picasso/include/soc/roms... File src/soc/amd/picasso/include/soc/romstage.h:
https://review.coreboot.org/#/c/32407/3/src/soc/amd/picasso/include/soc/roms... PS3, Line 16: __STONEYRIDGE_ROMSTAGE_H__ ?
https://review.coreboot.org/#/c/32407/3/src/soc/amd/picasso/include/soc/smbu... File src/soc/amd/picasso/include/soc/smbus.h:
https://review.coreboot.org/#/c/32407/3/src/soc/amd/picasso/include/soc/smbu... PS3, Line 16: _STONEYRIDGE is it intentional?
https://review.coreboot.org/#/c/32407/3/src/soc/amd/picasso/include/soc/smi.... File src/soc/amd/picasso/include/soc/smi.h:
https://review.coreboot.org/#/c/32407/3/src/soc/amd/picasso/include/soc/smi.... PS3, Line 18: SOUTHBRIDGE_AMD_PI_STONEYRIDGE ?
https://review.coreboot.org/#/c/32407/3/src/soc/amd/picasso/include/soc/sout... File src/soc/amd/picasso/include/soc/southbridge.h:
https://review.coreboot.org/#/c/32407/3/src/soc/amd/picasso/include/soc/sout... PS3, Line 17: _STONEYRIDGE ?
https://review.coreboot.org/#/c/32407/3/src/soc/amd/picasso/tsc_freq.c File src/soc/amd/picasso/tsc_freq.c:
https://review.coreboot.org/#/c/32407/3/src/soc/amd/picasso/tsc_freq.c@33 PS3, Line 33: Family 15h Models 70h-7Fh 17h ?