[coreboot-gerrit] Change in coreboot[master]: soc/intel/cannonlake: pch rp groups

[Felix Singer (Code Review)]

Attention is currently required from: Patrick Rudolph.
 Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52628 )

Change subject: soc/intel/cannonlake: pch rp groups
......................................................................

soc/intel/cannonlake: pch rp groups

Change-Id: Ie256222ece35f1f607af1cc922aacf7c026432b9
Signed-off-by: Felix Singer 
---
M src/soc/intel/cannonlake/chip.c
1 file changed, 8 insertions(+), 11 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/52628/1

diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c
index c651c59..642b618 100644
--- a/src/soc/intel/cannonlake/chip.c
+++ b/src/soc/intel/cannonlake/chip.c
@@ -16,17 +16,17 @@

#include "chip.h"

-static const struct pcie_rp_group pch_lp_rp_groups[] = {
-	{ .slot = PCH_DEV_SLOT_PCIE,	.count = 8 },
-	{ .slot = PCH_DEV_SLOT_PCIE_1,	.count = 8 },
-	{ 0 }
-};
-
-static const struct pcie_rp_group pch_h_rp_groups[] = {
+static const struct pcie_rp_group pch_rp_groups[] = {
+#if CONFIG(SOC_INTEL_CANNONLAKE_PCH_H)
    { .slot = PCH_DEV_SLOT_PCIE,	.count = 8 },
    { .slot = PCH_DEV_SLOT_PCIE_1,	.count = 8 },
    { .slot = PCH_DEV_SLOT_PCIE_2,	.count = 8 },
    { 0 }
+#else
+	{ .slot = PCH_DEV_SLOT_PCIE,	.count = 8 },
+	{ .slot = PCH_DEV_SLOT_PCIE_1,	.count = 8 },
+	{ 0 }
+#endif
 };

#if CONFIG(HAVE_ACPI_TABLES)
@@ -150,10 +150,7 @@
    soc_gpio_pm_configuration();

/* swap enabled PCI ports in device tree if needed */
-	if (CONFIG(SOC_INTEL_CANNONLAKE_PCH_H))
-		pcie_rp_update_devicetree(pch_h_rp_groups);
-	else
-		pcie_rp_update_devicetree(pch_lp_rp_groups);
+	pcie_rp_update_devicetree(pch_rp_groups);
 }

static struct device_operations pci_domain_ops = {