[coreboot-gerrit] Change in coreboot[master]: soc/amd/picasso: Set max_speed_mts and configured_speed_mts

[Rob Barnes (Code Review)]

Hello Raul Rangel, Furquan Shaikh,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/44984

to look at the new patch set (#2).

Change subject: soc/amd/picasso: Set max_speed_mts and configured_speed_mts
......................................................................

soc/amd/picasso: Set max_speed_mts and configured_speed_mts

ddr_frequency is deprecated. Set max_speed_mts and configured_speed_mts
instead. This will result in SMBIOS type 17 displaying more accurate
speed information.

BUG=b:167218112
TEST=Boot ezkinil and observe dmidecode -t17
  dmidecode -t17
  # dmidecode 3.2
  Getting SMBIOS data from sysfs.
  SMBIOS 3.0 present.

Handle 0x000B, DMI type 17, 40 bytes
  Memory Device
    Array Handle: 0x000A
    Error Information Handle: Not Provided
    Total Width: 64 bits
    Data Width: 64 bits
    Size: 4096 MB
    Form Factor: SODIMM
    Set: None
    Locator: Channel-0-DIMM-0
    Bank Locator: BANK 0
    Type: DDR4
    Type Detail: Synchronous
    Speed: 3200 MT/s
    Manufacturer: Unknown (0)
    Serial Number: 00000000
    Asset Tag: Not Specified
    Part Number: MT40A512M16TB-062E:J
    Rank: 1
    Configured Memory Speed: 2400 MT/s
    Minimum Voltage: Unknown
    Maximum Voltage: Unknown
    Configured Voltage: Unknown

Signed-off-by: Rob Barnes 
Change-Id: I1879676ea9436b6d19c768f1b78487a4e179f8d6
---
M src/soc/amd/picasso/dmi.c
1 file changed, 5 insertions(+), 7 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/44984/2