[coreboot-gerrit] [M] Change in coreboot[master]: soc/amd/mendocino: Remove the SPL DPTC parameter

[Tim Van Patten (Code Review)]

Attention is currently required from: Frank Wu, Jason Glenesk, Raul Rangel, Jason Nien, EricKY Cheng, Matt DeVillier, Isaac Lee, Chris Wang, Martin Roth, Fred Reitberger, Felix Held.

Tim Van Patten has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73124 )

Change subject: soc/amd/mendocino: Remove the SPL DPTC parameter
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Patch Set 6:

(1 comment)

File src/mainboard/google/skyrim/variants/baseboard/devicetree.cb:

https://review.coreboot.org/c/coreboot/+/73124/comment/5873ef2a_b6e24e3f 
PS6, Line 263: # Remove the sustained_power_limit_mW when STT is enabled
             : 	register "sustained_power_limit_mW"              = "15000"
> It may need to submit another CL if we want to move 'sustained_power_limit_mW' from the baseboard to […]

I'm leaning towards Frank's suggestion, since the current comment is not entirely accurate. STT is enabled for Frostflow and Whiterun, but this setting will still be applied (although only via the FSP during boot), so it can't/won't be removed.

While `sustained_power_limit_mW` would be duplicated for the boards that need it, we don't want it configured for every board. The current split is:

STT Enabled:
* Frostflow
* Whiterun

STT Disabled:
* Skyrim
* Markarth
* Crystaldrift

It does look better to set the value in the each `overridetree.cb` that wants it (STT disabled), so it can be removed if/when STT is enabled for that board. Additionally, it prevents `sustained_power_limit_mW` from being set for boards that do have STT enabled.