Philipp Deppenwiese (zaolin.daisuki@googlemail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15531
-gerrit
commit d401b071223922cc1ded1a7d40fd67771ddafe64 Author: Philipp Deppenwiese zaolin@das-labor.org Date: Sat Jul 2 00:00:36 2016 +0200
Documentation: Introduce Hugo static page documentation
Currently WIP.
Change-Id: I40e320c7f78da0fedb5769ba8fd473ce6a26aff6 Signed-off-by: Philipp Deppenwiese zaolin@das-labor.org --- .gitmodules | 4 + Documentation/.gitignore | 1 + Documentation/AMD-S3.txt | 153 -- Documentation/CorebootBuildingGuide.tex | 671 -------- Documentation/Doxyfile.coreboot | 1639 -------------------- Documentation/Doxyfile.coreboot_simple | 259 ---- Documentation/Intel/Board/Galileo_checklist.html | 162 -- Documentation/Intel/Board/board.html | 240 --- Documentation/Intel/Board/galileo.html | 114 -- Documentation/Intel/SoC/quark.html | 179 --- Documentation/Intel/SoC/soc.html | 734 --------- Documentation/Intel/development.html | 377 ----- Documentation/Intel/fsp1_1.html | 77 - Documentation/Intel/index.html | 86 - Documentation/Kconfig.tex | 480 ------ Documentation/Makefile | 70 - Documentation/POSTCODES | 25 - Documentation/RFC/chip.tex | 266 ---- Documentation/RFC/config.tex | 290 ---- Documentation/abi-data-consumption.txt | 22 - Documentation/backup-docs/index.md | 10 + Documentation/backup-docs/old/AMD-S3.txt | 153 ++ .../backup-docs/old/CorebootBuildingGuide.tex | 671 ++++++++ Documentation/backup-docs/old/Doxyfile.coreboot | 1639 ++++++++++++++++++++ .../backup-docs/old/Doxyfile.coreboot_simple | 259 ++++ .../old/Intel/Board/Galileo_checklist.html | 162 ++ .../backup-docs/old/Intel/Board/board.html | 240 +++ .../backup-docs/old/Intel/Board/galileo.html | 114 ++ Documentation/backup-docs/old/Intel/SoC/quark.html | 179 +++ Documentation/backup-docs/old/Intel/SoC/soc.html | 734 +++++++++ .../backup-docs/old/Intel/development.html | 377 +++++ Documentation/backup-docs/old/Intel/fsp1_1.html | 77 + Documentation/backup-docs/old/Intel/index.html | 86 + Documentation/backup-docs/old/Kconfig.tex | 480 ++++++ Documentation/backup-docs/old/Makefile | 70 + Documentation/backup-docs/old/POSTCODES | 25 + Documentation/backup-docs/old/RFC/chip.tex | 266 ++++ Documentation/backup-docs/old/RFC/config.tex | 290 ++++ .../backup-docs/old/abi-data-consumption.txt | 22 + Documentation/backup-docs/old/beginverbatim.tex | 1 + Documentation/backup-docs/old/cbfs.txt | 421 +++++ Documentation/backup-docs/old/codeflow.svg | 234 +++ Documentation/backup-docs/old/coreboot_logo.png | Bin 0 -> 2236 bytes Documentation/backup-docs/old/endverbatim.tex | 1 + Documentation/backup-docs/old/gcov.txt | 227 +++ Documentation/backup-docs/old/gerrit_guidelines.md | 277 ++++ Documentation/backup-docs/old/hypertransport.svg | 59 + .../old/mainboard_io_trap_handler_sample.c | 51 + Documentation/backup-docs/old/submodules.txt | 46 + Documentation/backup-docs/old/timestamp.md | 200 +++ Documentation/beginverbatim.tex | 1 - Documentation/cbfs.txt | 421 ----- Documentation/codeflow.svg | 234 --- Documentation/config.toml | 53 + Documentation/content/docs/core/index.md | 8 + Documentation/content/docs/core/timestamps.md | 116 ++ .../content/docs/vendor/intel/boards/boards.md | 169 ++ .../content/docs/vendor/intel/boards/galileo.md | 100 ++ .../docs/vendor/intel/boards/galileo_checklist.md | 1356 ++++++++++++++++ .../content/docs/vendor/intel/development.md | 129 ++ Documentation/content/docs/vendor/intel/fsp1_1.md | 66 + Documentation/content/docs/vendor/intel/index.md | 9 + .../content/docs/vendor/intel/soc/quark.md | 152 ++ Documentation/content/docs/vendor/intel/soc/soc.md | 593 +++++++ .../content/docs/vendor/intel/tableofcontents.md | 70 + Documentation/content/getting-started/gerrit.md | 126 ++ Documentation/content/getting-started/index.md | 10 + .../content/getting-started/submodules.md | 43 + Documentation/content/index.md | 10 + Documentation/content/licenses/index.md | 9 + Documentation/coreboot_logo.png | Bin 2236 -> 0 bytes Documentation/endverbatim.tex | 1 - Documentation/gcov.txt | 227 --- Documentation/gerrit_guidelines.md | 277 ---- Documentation/hypertransport.svg | 59 - Documentation/mainboard_io_trap_handler_sample.c | 51 - Documentation/static/favicon.ico | Bin 0 -> 318 bytes Documentation/static/images/favicon.ico | Bin 0 -> 15086 bytes Documentation/static/images/logo.png | Bin 0 -> 25721 bytes Documentation/submodules.txt | 46 - Documentation/themes/hugo-material-docs | 1 + Documentation/timestamp.md | 200 --- 82 files changed, 10396 insertions(+), 7361 deletions(-)
diff --git a/.gitmodules b/.gitmodules index ad6b899..99824ea 100644 --- a/.gitmodules +++ b/.gitmodules @@ -15,3 +15,7 @@ [submodule "3rdparty/chromeec"] path = 3rdparty/chromeec url = ../chrome-ec.git +[submodule "docs-site-theme"] + path = Documentation/themes/hugo-material-docs + url = https://github.com/digitalcraftsman/hugo-material-docs.git + branch = master diff --git a/Documentation/.gitignore b/Documentation/.gitignore new file mode 100644 index 0000000..364fdec --- /dev/null +++ b/Documentation/.gitignore @@ -0,0 +1 @@ +public/ diff --git a/Documentation/AMD-S3.txt b/Documentation/AMD-S3.txt deleted file mode 100644 index 48d4c8f..0000000 --- a/Documentation/AMD-S3.txt +++ /dev/null @@ -1,153 +0,0 @@ - _____ ____ _____ ______ ____ ____ ____ _______ - / ____/ __ | __ | ____| _ \ / __ \ / __ __ __| - | | | | | | |__) | |__ | |_) | | | | | | | | | - | | | | | | _ /| __| | _ <| | | | | | | | | - | |___| |__| | | \ | |____| |_) | |__| | |__| | | | - _________/|_| _______|____/ ____/ ____/ |_| - - __ __ _____ _____ ____ - /\ | / | __ \ / ____| |___ \ - / \ | \ / | | | | | (___ __) | - / /\ \ | |/| | | | | ___ \ |__ < - / ____ | | | | |__| | ____) | ___) | - /_/ __| |_|_____/ |_____/ |____/ - - - S3 in Coreboot (V 1.2) ----------------------------------------- - Zheng Bao - zheng.bao@amd.com - fishbaozi@gmail.com - -Introduction -============ -This document is about how the feature S3 is implemented on coreboot, -specifically on AMD platform. This topic deals with ACPI spec, hardware, -BIOS, OS. We try to help coreboot users to realize their own S3. - -S3 in a nutshell -================ -The S3 sleeping state is a low wake latency sleeping state where all -system context is lost except system memory. [1]. S3 is a ACPI -definition. -To enter S3, write 3 in SLP_TYPx and set the SLP_EN bit (See ACPI -registers). But if you do that, board can not resume at where it -sleeps, because you don't save the context. More often than not, we -make the board go into S3 by the tools which OSes provide. For -windows, click Start->sleep. For linux, some distribution provide a -tools called pm-suspend, which can make the system goto S3. If -pm-suspend is not available, we can run "echo mem > /sys/power/state", -but this way may not save all the needed context. -In S3 state, the power is off. So when the power button is pressed, -BIOS runs as it does in cold boot. If BIOS didn't detect whether -board boots or resumes, it would go the same way as boot. It is not -what we expect. BIOS detects the SLP_TYPx. If it is 3, it means BIOS -are waking up. -BIOS is responsible for restore the machine state as it is before -sleep. It needs restore the memory controller, not overwriting memory -which is not marked as reserved. For the peripheral which loses its -registers, BIOS needs to write the original value. -When everything is done, BIOS needs to find out the wakeup vector -provided by OSes and jump there. OSes also have work to do. We can go -to linux kernel or some other open source projects to find out how they -handle S3 resume. - -ACPI registers -============== -ACPI specification defines a group of registers. OSes handle all these -registers to read and write status to all the platform. -On AMD platform, these registers are provided by southbridge. For -example, Hudson uses PMIO 60:6F to define ACPI registers. -OSes don't have any specific driver to know where these registers -are. BIOS has the responsibility to allocated the IO resources and -write all these address to FADT, a ACPI defined table. - -Memory Layout -============= -Restoring memory is the most important job done by BIOS. When the -power is off, the memory is maintained by standby power. BIOS need to -make sure that when flow goes to OS, everything in memory should be -the same as it was. - -The chip vendor will provide a way, or code, to wake up the memory -from sleeping. In AGESA 2008 arch, it is called AmdInitResume. - -The BIOS itself needs some memory to run. Either, BIOS marks the erea -as reserved in e820, or BIOS saves the content into reserved space. - -Here is the address Map for S3 Resume. Assumingly the total memory is 1GB. -00000000 --- 00100000 BIOS Reserved area. -00100000 --- 00200000 Free -00200000 --- 01000000 Coreboot ramstage area. -01000000 --- 2e160000 Free -2e160000 --- 2e170000 ACPI table -2e170000 --- 2ef70000 OSRAM -2ef70000 --- 2efe0000 Stack in highmem -2efe0000 --- 2f000000 heap in highmem -2f000000 TOM - -AMD requirements in S3 -====================== -Chip vendor like AMD will provide bunch of routines to restore the -board.[2] - * AmdS3Save: It is called in cold boot, save required register into - non-volatile storage. Currently, we use SPI flash to store the data. - * AmdInitResume: Restore the memory controller. - * AmdS3LateRestore: Called after AmdInitResume, restore other - register that memory. - * (SouthBridge)InitS3EarlyRestore, (SouthBridge)InitS3LateRestore: - Provided by Southbridge vendor code. Early is called before PCI - enumeration, and Late is called after that. - -Lifecycle of booting, sleeping and waking Coreboot and Ubuntu -============================================================= -1. Cold boot. -For a system with S3 feature, the BIOS needs to save some data to -non-volatile storage at cold boot stage. What data need to be save are -provided by AmdS3Save. After the wrapper calls the AmdS3Save, it gets -the VolatileStorage and NvStorage, which are where the data are -located. It is the wrappers's responsibility to save the data.[3][4] -Currently, the wrappers allocate a CBFS modules in BIOS image. To do -that, the wrapper needs to have the ability to write flash chips. It -is not as comprehensive as flashrom. But for the SST chip on Parmer, -MX chip on Thather, coreboot works well.[5] - -2. OS goes in S3. -For Linux, besides the kernel needs to do some saving, most distributions -run some scripts. For Ubuntu, scripts are located at /usr/lib/pm-utils/sleep.d. - # ls /usr/lib/pm-utils/sleep.d - 000kernel-change 49bluetooth 90clock 95led - 00logging 55NetworkManager 94cpufreq 98video-quirk-db-handler - 00powersave 60_wpa_supplicant 95anacron 99video - 01PulseAudio 75modules 95hdparm-apm -The script with lower prefix runs before the one with higher prefix. -99video is the last one. -Those scripts have hooks called hibernate, suspend, thaw, resume. For -each script, suspend is called when system sleeps and wakeup is called -when system wakeups. - -3. Firmware detects S3 wakeup -As we mentioned, Firmware detects the SLP_TYPx to find out if the board -wakes up. In romstage.c, AmdInitReset and AmdInitEarly are called -as they are during cold boot. AmdInitResume and AmdS3LateRestore are -called only during resume. For whole ramstage, Coreboot goes through -almost the same way as cold boot, other than not calling the AmdInitMid, -AmdInitLate and AmdS3Save, and restoring all the MTRRs. -At last step of coreboot stage, coreboot finds out the wakeup vector in FADT, -written by OS, and jump. - -4. OS resumes. -When Linux resumes, all the sleeping scripts call their resume -hooks. If we are more lucky, all the scripts can go through. More -chances that the 99video hangs or fails to get the display -back. Sometimes it can fixed if CONFIG_S3_VGA_ROM_RUN is unset in -Coreboot/Kconfig. That needs more troubleshooting. - - -Reference -========= -[1] ACPI40a, http://www.acpi.info/spec40a.htm -[2] Coreboot Vendorcode, {top}/src/vendorcode/amd/agesa/{family}/Proc/Common/ -[3] Coreboot AGESA wrapper, {top}/src/mainboard/amd/parmer/agesawrapper.c -[4] Coreboot AGESA wrapper, {top}/src/cpu/amd/agesa/s3_resume.c -[5] Coreboot Southbridge, {top}/src/southbridge/amd/agesa/hudson/spi.c diff --git a/Documentation/CorebootBuildingGuide.tex b/Documentation/CorebootBuildingGuide.tex deleted file mode 100644 index dac031a..0000000 --- a/Documentation/CorebootBuildingGuide.tex +++ /dev/null @@ -1,671 +0,0 @@ -% -% This document is released under the GPL -% Initially written by Stefan Reinauer, stepan@coresystems.de -% - -\documentclass[titlepage,12pt]{article} -\usepackage{a4} -\usepackage{graphicx} -\usepackage{epsfig} -\usepackage{epstopdf} -\usepackage{url} -\usepackage{color} -% \usepackage{geometry} -\usepackage[pdftex]{hyperref} -% \usepackage{makeidx} -% \makeindex -% \geometry{left=2cm,right=2cm,top=2cm,bottom=2cm} - -\hypersetup{ - urlbordercolor={1 1 1}, - menubordercolor={1 1 1}, - linkbordercolor={1 1 1}, - colorlinks=false, - % pdfpagemode=None, % PDF-Viewer starts without TOC - % pdfstartview=FitH, - pdftitle={Coreboot Porting Guide}, - pdfauthor={Zheng Bao}, - pdfsubject={coreboot configuration and build process}, - pdfkeywords={coreboot, AMD, configuration, Build} -} - -\setlength{\parindent}{0pt} -\setlength{\hoffset}{0pt} - -\title{Coreboot from Scratch} -\author{Stefan Reinauer $<$stepan@coresystems.de$>$\and Zheng Bao $<$zheng.bao@amd.com$>$} -\date{Dec 4th, 2013} - -\begin{document} - -\maketitle - -\thispagestyle{empty} - -\tableofcontents - -\newpage - -\section{What is Coreboot} -coreboot aims to replace the normal BIOS found on x86, AMD64, PPC, -Alpha, and other machines with a Linux kernel that can boot Linux from a cold -start. The startup code of an average coreboot port is about 500 lines of -assembly and 5000 lines of C. It executes 16 instructions to get into 32bit -protected mode and then performs DRAM and other hardware initializations -required before Linux can take over. - -The projects primary motivation initially was maintenance of large -clusters. Not surprisingly interest and contributions have come from -people with varying backgrounds. Nowadays a large and growing number of -Systems can be booted with coreboot, including embedded systems, -Desktop PCs and Servers. - -This document is used to build, modify, and port the CoreBoot code -base on the AMD platform. - - -\section{Changes} - - \begin{itemize} - \item 2013/12/20 Add Git, Gerrit, toolchains building. - \item 2009/04/19 replace LinuxBIOS with coreboot - \item 2004/06/02 url and language fixes from Ken Fuchs $<$kfuchs@winternet.com$>$ - \item 2004/02/10 acpi and option rom updates - \item 2003/11/18 initial release - \end{itemize} - -% -% Build Requirements -% - -\section{Build Requirements} -To build coreboot for AMD64 from the sources you need a recent Linux. -SUSE Linux 11.2, CentOS release 6.3, Fedora Core 16, Cygwin, FreeBSD, -NetBSD are known to work fine. - -To build the toolchain, you need following host compilers: - - \begin{itemize} - \item GNUtar - \item GNUpatch - \item GNUmake - \item GCC - \item binutils - \item bison - \item flex - \item m4 - \item wget - \end{itemize} - -Besides the tools above, after the toolchains are built, you also need the following -tools to build the source. - - \begin{itemize} - \item git: Get the source code from repository - \item libncurses-dev (or ncursesw, ncurses, curses, pdcursesw, pdcurses): for menuconfig - \item python: Optional for gdb. - \item perl: Optional for gdb. - \end{itemize} - -% -% Getting Coreboot -% - -\section{Getting Coreboot} -The latest coreboot sources are available via GIT. -For users who doesn't need to change and commit the code: -{ \small -\begin{verbatim} -$ git clone http://review.coreboot.org/p/coreboot -\end{verbatim} -} -For developers, you need to get a gerrit account which you can register -at \url{http://review.coreboot.org%7D. Please refer section ~\ref{sec:gerrit} -{ \small -\begin{verbatim} -$ git clone ssh://<username>@review.coreboot.org:29418/coreboot -$ git clone http://[<username>:<password>@]review.coreboot.org/coreboot.git -\end{verbatim} -} - -Checks out a sub-repository in the 3rdparty directory. -{ \small -\begin{verbatim} -$ git submodule update --init --checkout -\end{verbatim} -} - -% -% Building the toolchain -% - -\section{Building the toolchain} -Coreboot recommends and guarantees the toolchain integrated with Coreboot. -Linux distributions usually modify their compilers in ways incompatible with Coreboot. - -{ \small -\begin{verbatim} -$ cd coreboot -$ make crossgcc -\end{verbatim} -} - -or - -{ \small -\begin{verbatim} -$ cd util/crossgcc -$ buildgcc -\end{verbatim} -} - -The buildgcc will try to get packages from website. You need to make sure you can -get access the internet. Or you can get the source.tar.gz and put it in util/crossgcc/tarballs. - -{ \small -\textcolor{blue} {Welcome to the} \textcolor{red} {coreboot} \textcolor{blue} {cross toolchain builder v1.23 (September 20th, 2013)} - -Target arch is now i386-elf - -Will skip GDB ... ok - -Downloading tar balls ... - - * gmp-5.1.2.tar.bz2 (cached) - - * mpfr-3.1.2.tar.bz2 (cached) - - * mpc-1.0.1.tar.gz (cached) - - * libelf-0.8.13.tar.gz (cached) - - * gcc-4.7.3.tar.bz2 (cached) - - * binutils-2.23.2.tar.bz2 (cached) - - * acpica-unix-20130626.tar.gz (cached) - -Downloaded tar balls ... \textcolor {green}{ok} - -Unpacking and patching ... - - * gmp-5.1.2.tar.bz2 - - * mpfr-3.1.2.tar.bz2 - - * mpc-1.0.1.tar.gz - - * libelf-0.8.13.tar.gz - - * gcc-4.7.3.tar.bz2 - - * binutils-2.23.2.tar.bz2 - - o binutils-2.23.2_arv7a.patch - - o binutils-2.23.2_no-bfd-doc.patch - - * acpica-unix-20130626.tar.gz - -Unpacked and patched ... \textcolor {green}{ok} - -Building GMP 5.1.2 ... \textcolor {green}{ok} - -Building MPFR 3.1.2 ... \textcolor {green}{ok} - -Building MPC 1.0.1 ... \textcolor {green}{ok} - -Building libelf 0.8.13 ... \textcolor {green}{ok} - -Building binutils 2.23.2 ... \textcolor {green}{ok} - -Building GCC 4.7.3 ... ok - -Skipping Expat (Python scripting not enabled) - -Skipping Python (Python scripting not enabled) - -Skipping GDB (GDB support not enabled) - -Building IASL 20130626 ... \textcolor {green}{ok} - -Cleaning up... \textcolor {green}{ok} - -\textcolor {green}{You can now run your i386-elf cross toolchain from /home/baozheng/x86/coreboot-gerrit/util/crossgcc/xgcc.} -} -If you are lucky, you can get toolchains located in util/crossgcc/xgcc. - -% -% Build Coreboot -% - -\section{Building Coreboot} -\subsection{Build main module of Coreboot} -{ \small -\begin{verbatim} -$ cd coreboot -$ make menuconfig -.config - coreboot v4.0-4895-gc5025a4-dirty Configuration -+------------------------ coreboot Configuration -------------------------+ -| Arrow keys navigate the menu. <Enter> selects submenus --->. | -| Highlighted letters are hotkeys. Pressing <Y> includes, <N> excludes, | -| <M> modularizes features. Press <Esc><Esc> to exit, <?> for Help, </> | -| for Search. Legend: [*] built-in [ ] excluded <M> module < > | -| +---------------------------------------------------------------------+ | -| | General setup ---> | | -| | Mainboard ---> | | -| | Architecture (x86) ---> | | -| | Chipset ---> | | -| | Devices ---> | | -| | VGA BIOS ---> | | -| | Display ---> | | -| | PXE ROM ---> | | -| | Generic Drivers ---> | | -| | Console ---> | | -| | [ ] Relocatable Modules | | -| | System tables ---> | | -| | Payload ---> | | -| | Debugging ---> | | -| | --- | | -| +----v(+)-------------------------------------------------------------+ | -+-------------------------------------------------------------------------+ -| <Select> < Exit > < Help > | -+------------------------------------------------------------------------- -\end{verbatim} -} -Select Mainboard -$>$ Mainboard Vendor -$>$ AMD - -$>$ Mainboard Model -$>$ Olive Hill - -Then save, exit and run make. - -{ \small -\begin{verbatim} -$ make -\end{verbatim} -} -The built image, coreboot.rom, is located at folder build. - -\section{Programming coreboot to flash memory} -The image resulting from a coreboot build can be directly programmed to -a flash device, either using an external flash programmers, e.g., Dediprog SF100, or by using the -Linux flash utility, flashrom. - - -\subsection{Add modules and payload} - -\subsubsection{VGA BIOS} -There is a big Chance that you need to get a VGA BIOS. -{ \small -\begin{verbatim} -.config - coreboot v4.0 Configuration ------------------------------------------------------------------------------- -+-------------------------------- VGA BIOS --------------------------------+ -| Arrow keys navigate the menu. <Enter> selects submenus --->. | -| Highlighted letters are hotkeys. Pressing <Y> includes, <N> excludes, | -| <M> modularizes features. Press <Esc><Esc> to exit, <?> for Help, </> | -| for Search. Legend: [*] built-in [ ] excluded <M> module < > module | -| +----------------------------------------------------------------------+ | -| | [*] Add a VGA BIOS image | | -| | (vgabios.bin) VGA BIOS path and filename | | -| | (1002,1306) VGA device PCI IDs | | -| | | | -| | | | -| | | | -| | | | -| | | | -| | | | -| +----------------------------------------------------------------------+ | -+--------------------------------------------------------------------------+ -| <Select> < Exit > < Help > | -+--------------------------------------------------------------------------+ -\end{verbatim} -} -Select VGA BIOS. ``The VGA device PCI IDs'' should be the same as your device. Get the -Option ROM from Vendor's website. - -\subsubsection{Payload} -coreboot in itself is "only" minimal code for initializing a mainboard -with peripherals. After the initialization, it jumps to a payload. - -Currently, SeaBIOS is the most widely used payload. The best way to integrate SeaBIOS -is setting it in menuconfig. -{ \small -\begin{verbatim} -+------------------------------- Payload ---------------------------------+ -| Arrow keys navigate the menu. <Enter> selects submenus --->. | -| Highlighted letters are hotkeys. Pressing <Y> includes, <N> excludes, | -| <M> modularizes features. Press <Esc><Esc> to exit, <?> for Help, </> | -| for Search. Legend: [*] built-in [ ] excluded <M> module < > module | -| +----------------------------------------------------------------------+ | -| | Add a payload (SeaBIOS) ---> | | -| | SeaBIOS version (1.7.2.1) ---> | | -| | [*] Use LZMA compression for payloads (NEW) | | -| | | | -| | | | -| | | | -| | | | -| | | | -| | | | -| +----------------------------------------------------------------------+ | -+--------------------------------------------------------------------------+ -| <Select> < Exit > < Help > | -+--------------------------------------------------------------------------+ -\end{verbatim} -The script in Makefile will automatically checkout, config, build the SeaBIOS source, -and integrat the binary into the final image. - -% -% Working with Git -% - -\section{Working with Git} -\subsection{Configuration of Git} -Inside the checkout you should install a commit-msg hook that adds a -Change-Id into commit messages, which uniquely identifies the logical -change in Gerrit even across multiple iterations of the commit. The -hook only needs to be installed once per clone, and installation can -be done with: -{ \small -\begin{verbatim} -$ cd coreboot -$ cp ./util/gitconfig/* .git/hooks -\end{verbatim} -} -configure your name and email in git. -{ \small -\begin{verbatim} -$ git config --global user.name "Your Name Comes Here" -$ git config --global user.email your.email@example.com' -\end{verbatim} -} -The name~\ref{user name} and email~\ref{Contact Information} should be the same the settings in gerrit. -Otherwise you can not push you code to community. - -Then run the following command once, to tell git that by default you -want to submit all commits in the currently checked-out branch for -review on gerrit: -{ \small -\begin{verbatim} -$ git config remote.origin.push HEAD:refs/for/master -\end{verbatim} -} - -The above configurations for git has been integrated into Makefile. You can run -{ \small -\begin{verbatim} -$ make gitconfig -\end{verbatim} -} - -\subsection{Work flow} - -It is recommended that you make a new branch when you start to work, not pushing changes to master. -{ \small -\begin{verbatim} -$ git checkout master -b mybranch -\end{verbatim} -} -After you have done your changes, run: -{ \small -\begin{verbatim} -$ git add file_need_to_submit.c -$ git commit -m "my first change." -\end{verbatim} -} - -% Does anyone have a better word to describe the phylosophy of spliting changes to patches? -You need to realize that the changes you have made should be well devided into -several commits. Each of them has one and only one meaning. You could use git rebase -i to -split, squash, remove, rewrite you comment. - -Here is an example of a well-formatted commit message: - -{ \small -\begin{verbatim} -examplecomponent: Refactor duplicated setup into a function - -Setting up the demo device correctly requires the exact same register -values to be written into each of the PCI device functions. Moving the -writes into a function allows also otherexamplecomponent to use them. - -Signed-off-by: Joe Hacker <joe@hacker.email> -\end{verbatim} -} - -Then you can push the code. -{ \small -\begin{verbatim} -$ git push -\end{verbatim} -} - -You can go to the ~\ref{sec:gerrit} gerrit to see if your changes is successfully pushed. - -Often it might happen that the patch you sent for approval is not good -enough from the first attempt. Gerrit and git make it easy to track -patch evolution during the review process until patches meet our -quality standards and are ready for approval. - -You can easily modify a patch sent to gerrit by you or even by someone -else. Just apply it locally using one of the possible ways to do it, -make a new local commit that fixes the issues reported by the -reviewers, then rebase the change by preserving the same Change-ID. We -recommend you to use the git rebase command in interactive mode, - -Once your patch gets a +2 comment, your patch can be merged (cherry-pick, actually) to origin/master. - -% -% Working with Gerrit -% - -\section{Working with Gerrit} -\label{sec:gerrit} -If you are a coreboot user, not planning to contribute, you can skip this section. -\subsection{Get gerrit account} -You need to get an OpenID first. Currently Google account give you an OpenID. It means, if you have a gmail account, you have an OpenID. You can try to signed in. -click \url{http://review.coreboot.org} - -%\includegraphics[width=6.00in,height=1.00in]{gerrit_signin.png} -{ \small -\begin{verbatim} -+-----------------------------------------------------------+ -|All Projects Documentation Register Sign In | -|Open Merged Abandoned | -|Search for status:open | -+-----------------------------------------------------------+ -|Subject Status Owner Project Branch Updated CR V | -|cpu: Rename.. Alexandru coreboot master 1:20 PM +1 | -|cpu: Only a.. Alexandru coreboot master 1:17 PM X | -|arch/x86: D.. Alexandru coreboot master 1:09 PM | -| | -| Next -> | -|Press '?' to view keyboard shortcuts | Powered by Gerrit | -+-----------------------------------------------------------+ -\end{verbatim} -} -Click ``Sign In'', You will get - -%\includegraphics[width=6.00in,height=4.00in]{openid.png} - -You will be redirected to Google to get logging in. - -% \includegraphics[width=6.00in,height=1.50in]{login.png} -{ \small -\begin{verbatim} -Sign In to Gerrit Code Review at review.coreboot.org -+--------------------------------------------------+ -+--------------------------------------------------+ -[] Remember me -Sign In Cancel -Sign in with a Google Account -Sign in with a Yahoo! ID -What is OpenID? - -OpenID provides secure single-sign-on, without revealing your passwords to this website. - -There are many OpenID providers available. You may already be member of one! - -Get OpenID -\end{verbatim} -} - -\subsection{Configure account} -Click the dropdown button near the user name and click ``Settings'' - -% \includegraphics[width=6.00in,height=4.00in]{settings} -% \epsfig{figure=keystroke_left} -% \epstopdf {file=settings.eps} -% \epsfig{file=settings.eps} - -\label{user name} In ``profile'' section, type the user name for git. This probably can be changed only once. -{ \small -\begin{verbatim} -Profile Username zbao -Preferences Full Name Zheng Bao -Watched Projects Email Address zheng.bao@amd.com -Contact Information Registered Jun 28, 2011 4:33 PM -SSH Public Keys Account ID 1000034 -HTTP Password -Identities -Groups -\end{verbatim} -} - -\label{Contact Information} In ``Contact Information'', enter you full name and your Email, which should be configured in your .gitconfig -{ \small -\begin{verbatim} - Full Name __________________________________ -Preferred Email ______________ Registered Email - -Save Changes -\end{verbatim} -} - -In ``SSH Public Keys'' section, upload your public key. -{ \small -\begin{verbatim} -Status Algorithm Key Comment - -Delete -Add SSH Public Key - > How to Generate an SSH Key -+--------------------------+ -| | -| | -| | -| | -| | -| | -| | -| | -| | -+--------------------------+ -clear Add Close -\end{verbatim} -} - -Click ``Add Key ...'' -Go back to you linux command line and type: -{ \small -\begin{verbatim} -$ ssh-keygen -Generating public/private rsa key pair. -Enter file in which to save the key (/home/zhengbao/.ssh/id_rsa): -Enter passphrase (empty for no passphrase): -Enter same passphrase again: -Your identification has been saved in /home/zhengbao/.ssh/id_rsa. -Your public key has been saved in /home/zhengbao/.ssh/id_rsa.pub. -The key fingerprint is: -xx:xx:xx:xx:xx:xx:xx:xx:xx:xx:xx:xx:xx:xx:xx:xx zhengb@host.domain -The key's randomart image is: -+--[ RSA 2048]----+ -| | -| | -| | -| | -| | -| | -| | -| | -| | -+-----------------+ -\end{verbatim} -} -The data in ~/.ssh/id\_rsa.pub is your public key. Copy them to the box in the page of ``SSH Public Keys'' and click add. - -In ``HTTP Password'' section, click button ``Generate Password''. You will get the password for http checkout. -{ \small -\begin{verbatim} -Username XXX -Password XXXXXXXXXXXX - -Generate Password Clear Password - -\end{verbatim} -} - -\subsection{Reviewing Changes} -For each listed changes in Gerrit, you can review, comment, evaluate, -cherry-pick, and even re-submit them. For you own patches, only you can -abandon them. Click in the file and commit message, you can add in-line comment. - -% -% 14 Glossary -% - -\section{Glossary} -\begin{itemize} -\item payload - -coreboot only cares about low level machine initialization, but also has -very simple mechanisms to boot a file either from FLASHROM or IDE. That -file, possibly a Linux Kernel, a boot loader or Etherboot, are called -payload, since it is the first software executed that does not cope with -pure initialization. - -\item flash device - -Flash devices are commonly used in all different computers since unlike -ROMs they can be electronically erased and reprogrammed. - -\item Gerrit - -Gerrit is a web based code review system, facilitating online code -reviews for projects using the Git version control system. - -Gerrit makes reviews easier by showing changes in a side-by-side -display, and allowing inline comments to be added by any reviewer. - -Gerrit simplifies Git based project maintainership by permitting any -authorized user to submit changes to the master Git repository, rather -than requiring all approved changes to be merged in by hand by the -project maintainer. This functionality enables a more centralized -usage of Git. - -\end{itemize} - -\newpage - -% -% 14 Bibliography -% - -\section{Bibliography} -\subsection{Additional Papers on coreboot} - -\begin{itemize} - \item - \textit{\url{http://www.coreboot.org/Documentation}} -\end{itemize} - -\subsection {Links} - -\begin{itemize} - \item Etherboot: \textit{\url{http://www.etherboot.org/}} - \item OpenBIOS: \textit{\url{http://www.openbios.org/}} - \item Flashrom: \textit{\url{http://www.flashrom.org/}} - \item Seabios: \textit{\url{http://www.seabios.org/}} -\end{itemize} - - -\end{document} diff --git a/Documentation/Doxyfile.coreboot b/Documentation/Doxyfile.coreboot deleted file mode 100644 index e6c06fe..0000000 --- a/Documentation/Doxyfile.coreboot +++ /dev/null @@ -1,1639 +0,0 @@ -# Doxyfile 1.7.1 - -# This file describes the settings to be used by the documentation system -# doxygen (www.doxygen.org) for a project -# -# All text after a hash (#) is considered a comment and will be ignored -# The format is: -# TAG = value [value, ...] -# For lists items can also be appended using: -# TAG += value [value, ...] -# Values that contain spaces should be placed between quotes (" ") - -#--------------------------------------------------------------------------- -# Project related configuration options -#--------------------------------------------------------------------------- - -# This tag specifies the encoding used for all characters in the config file -# that follow. The default is UTF-8 which is also the encoding used for all -# text before the first occurrence of this tag. Doxygen uses libiconv (or the -# iconv built into libc) for the transcoding. See -# http://www.gnu.org/software/libiconv for the list of possible encodings. - -DOXYFILE_ENCODING = UTF-8 - -# The PROJECT_NAME tag is a single word (or a sequence of words surrounded -# by quotes) that should identify the project. - -PROJECT_NAME = coreboot - -# The PROJECT_NUMBER tag can be used to enter a project or revision number. -# This could be handy for archiving the generated documentation or -# if some version control system is used. - -PROJECT_NUMBER = - -# The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute) -# base path where the generated documentation will be put. -# If a relative path is entered, it will be relative to the location -# where doxygen was started. If left blank the current directory will be used. - -OUTPUT_DIRECTORY = doxygen - -# If the CREATE_SUBDIRS tag is set to YES, then doxygen will create -# 4096 sub-directories (in 2 levels) under the output directory of each output -# format and will distribute the generated files over these directories. -# Enabling this option can be useful when feeding doxygen a huge amount of -# source files, where putting all generated files in the same directory would -# otherwise cause performance problems for the file system. - -CREATE_SUBDIRS = NO - -# The OUTPUT_LANGUAGE tag is used to specify the language in which all -# documentation generated by doxygen is written. Doxygen will use this -# information to generate all constant output in the proper language. -# The default language is English, other supported languages are: -# Afrikaans, Arabic, Brazilian, Catalan, Chinese, Chinese-Traditional, -# Croatian, Czech, Danish, Dutch, Esperanto, Farsi, Finnish, French, German, -# Greek, Hungarian, Italian, Japanese, Japanese-en (Japanese with English -# messages), Korean, Korean-en, Lithuanian, Norwegian, Macedonian, Persian, -# Polish, Portuguese, Romanian, Russian, Serbian, Serbian-Cyrilic, Slovak, -# Slovene, Spanish, Swedish, Ukrainian, and Vietnamese. - -OUTPUT_LANGUAGE = English - -# If the BRIEF_MEMBER_DESC tag is set to YES (the default) Doxygen will -# include brief member descriptions after the members that are listed in -# the file and class documentation (similar to JavaDoc). -# Set to NO to disable this. - -BRIEF_MEMBER_DESC = YES - -# If the REPEAT_BRIEF tag is set to YES (the default) Doxygen will prepend -# the brief description of a member or function before the detailed description. -# Note: if both HIDE_UNDOC_MEMBERS and BRIEF_MEMBER_DESC are set to NO, the -# brief descriptions will be completely suppressed. - -REPEAT_BRIEF = YES - -# This tag implements a quasi-intelligent brief description abbreviator -# that is used to form the text in various listings. Each string -# in this list, if found as the leading text of the brief description, will be -# stripped from the text and the result after processing the whole list, is -# used as the annotated text. Otherwise, the brief description is used as-is. -# If left blank, the following values are used ("$name" is automatically -# replaced with the name of the entity): "The $name class" "The $name widget" -# "The $name file" "is" "provides" "specifies" "contains" -# "represents" "a" "an" "the" - -ABBREVIATE_BRIEF = - -# If the ALWAYS_DETAILED_SEC and REPEAT_BRIEF tags are both set to YES then -# Doxygen will generate a detailed section even if there is only a brief -# description. - -ALWAYS_DETAILED_SEC = YES - -# If the INLINE_INHERITED_MEMB tag is set to YES, doxygen will show all -# inherited members of a class in the documentation of that class as if those -# members were ordinary class members. Constructors, destructors and assignment -# operators of the base classes will not be shown. - -INLINE_INHERITED_MEMB = NO - -# If the FULL_PATH_NAMES tag is set to YES then Doxygen will prepend the full -# path before files name in the file list and in the header files. If set -# to NO the shortest path that makes the file name unique will be used. - -FULL_PATH_NAMES = YES - -# If the FULL_PATH_NAMES tag is set to YES then the STRIP_FROM_PATH tag -# can be used to strip a user-defined part of the path. Stripping is -# only done if one of the specified strings matches the left-hand part of -# the path. The tag can be used to show relative paths in the file list. -# If left blank the directory from which doxygen is run is used as the -# path to strip. - -STRIP_FROM_PATH = - -# The STRIP_FROM_INC_PATH tag can be used to strip a user-defined part of -# the path mentioned in the documentation of a class, which tells -# the reader which header file to include in order to use a class. -# If left blank only the name of the header file containing the class -# definition is used. Otherwise one should specify the include paths that -# are normally passed to the compiler using the -I flag. - -STRIP_FROM_INC_PATH = - -# If the SHORT_NAMES tag is set to YES, doxygen will generate much shorter -# (but less readable) file names. This can be useful is your file systems -# doesn't support long names like on DOS, Mac, or CD-ROM. - -SHORT_NAMES = NO - -# If the JAVADOC_AUTOBRIEF tag is set to YES then Doxygen -# will interpret the first line (until the first dot) of a JavaDoc-style -# comment as the brief description. If set to NO, the JavaDoc -# comments will behave just like regular Qt-style comments -# (thus requiring an explicit @brief command for a brief description.) - -JAVADOC_AUTOBRIEF = YES - -# If the QT_AUTOBRIEF tag is set to YES then Doxygen will -# interpret the first line (until the first dot) of a Qt-style -# comment as the brief description. If set to NO, the comments -# will behave just like regular Qt-style comments (thus requiring -# an explicit \brief command for a brief description.) - -QT_AUTOBRIEF = NO - -# The MULTILINE_CPP_IS_BRIEF tag can be set to YES to make Doxygen -# treat a multi-line C++ special comment block (i.e. a block of //! or /// -# comments) as a brief description. This used to be the default behaviour. -# The new default is to treat a multi-line C++ comment block as a detailed -# description. Set this tag to YES if you prefer the old behaviour instead. - -MULTILINE_CPP_IS_BRIEF = NO - -# If the INHERIT_DOCS tag is set to YES (the default) then an undocumented -# member inherits the documentation from any documented member that it -# re-implements. - -INHERIT_DOCS = YES - -# If the SEPARATE_MEMBER_PAGES tag is set to YES, then doxygen will produce -# a new page for each member. If set to NO, the documentation of a member will -# be part of the file/class/namespace that contains it. - -SEPARATE_MEMBER_PAGES = NO - -# The TAB_SIZE tag can be used to set the number of spaces in a tab. -# Doxygen uses this value to replace tabs by spaces in code fragments. - -TAB_SIZE = 8 - -# This tag can be used to specify a number of aliases that acts -# as commands in the documentation. An alias has the form "name=value". -# For example adding "sideeffect=\par Side Effects:\n" will allow you to -# put the command \sideeffect (or @sideeffect) in the documentation, which -# will result in a user-defined paragraph with heading "Side Effects:". -# You can put \n's in the value part of an alias to insert newlines. - -ALIASES = - -# Set the OPTIMIZE_OUTPUT_FOR_C tag to YES if your project consists of C -# sources only. Doxygen will then generate output that is more tailored for C. -# For instance, some of the names that are used will be different. The list -# of all members will be omitted, etc. - -OPTIMIZE_OUTPUT_FOR_C = YES - -# Set the OPTIMIZE_OUTPUT_JAVA tag to YES if your project consists of Java -# sources only. Doxygen will then generate output that is more tailored for -# Java. For instance, namespaces will be presented as packages, qualified -# scopes will look different, etc. - -OPTIMIZE_OUTPUT_JAVA = NO - -# Set the OPTIMIZE_FOR_FORTRAN tag to YES if your project consists of Fortran -# sources only. Doxygen will then generate output that is more tailored for -# Fortran. - -OPTIMIZE_FOR_FORTRAN = NO - -# Set the OPTIMIZE_OUTPUT_VHDL tag to YES if your project consists of VHDL -# sources. Doxygen will then generate output that is tailored for -# VHDL. - -OPTIMIZE_OUTPUT_VHDL = NO - -# Doxygen selects the parser to use depending on the extension of the files it -# parses. With this tag you can assign which parser to use for a given extension. -# Doxygen has a built-in mapping, but you can override or extend it using this -# tag. The format is ext=language, where ext is a file extension, and language -# is one of the parsers supported by doxygen: IDL, Java, Javascript, CSharp, C, -# C++, D, PHP, Objective-C, Python, Fortran, VHDL, C, C++. For instance to make -# doxygen treat .inc files as Fortran files (default is PHP), and .f files as C -# (default is Fortran), use: inc=Fortran f=C. Note that for custom extensions -# you also need to set FILE_PATTERNS otherwise the files are not read by doxygen. - -EXTENSION_MAPPING = - -# If you use STL classes (i.e. std::string, std::vector, etc.) but do not want -# to include (a tag file for) the STL sources as input, then you should -# set this tag to YES in order to let doxygen match functions declarations and -# definitions whose arguments contain STL classes (e.g. func(std::string); v.s. -# func(std::string) {}). This also make the inheritance and collaboration -# diagrams that involve STL classes more complete and accurate. - -BUILTIN_STL_SUPPORT = NO - -# If you use Microsoft's C++/CLI language, you should set this option to YES to -# enable parsing support. - -CPP_CLI_SUPPORT = NO - -# Set the SIP_SUPPORT tag to YES if your project consists of sip sources only. -# Doxygen will parse them like normal C++ but will assume all classes use public -# instead of private inheritance when no explicit protection keyword is present. - -SIP_SUPPORT = NO - -# For Microsoft's IDL there are propget and propput attributes to indicate getter -# and setter methods for a property. Setting this option to YES (the default) -# will make doxygen to replace the get and set methods by a property in the -# documentation. This will only work if the methods are indeed getting or -# setting a simple type. If this is not the case, or you want to show the -# methods anyway, you should set this option to NO. - -IDL_PROPERTY_SUPPORT = YES - -# If member grouping is used in the documentation and the DISTRIBUTE_GROUP_DOC -# tag is set to YES, then doxygen will reuse the documentation of the first -# member in the group (if any) for the other members of the group. By default -# all members of a group must be documented explicitly. - -DISTRIBUTE_GROUP_DOC = NO - -# Set the SUBGROUPING tag to YES (the default) to allow class member groups of -# the same type (for instance a group of public functions) to be put as a -# subgroup of that type (e.g. under the Public Functions section). Set it to -# NO to prevent subgrouping. Alternatively, this can be done per class using -# the \nosubgrouping command. - -SUBGROUPING = YES - -# When TYPEDEF_HIDES_STRUCT is enabled, a typedef of a struct, union, or enum -# is documented as struct, union, or enum with the name of the typedef. So -# typedef struct TypeS {} TypeT, will appear in the documentation as a struct -# with name TypeT. When disabled the typedef will appear as a member of a file, -# namespace, or class. And the struct will be named TypeS. This can typically -# be useful for C code in case the coding convention dictates that all compound -# types are typedef'ed and only the typedef is referenced, never the tag name. - -TYPEDEF_HIDES_STRUCT = NO - -# The SYMBOL_CACHE_SIZE determines the size of the internal cache use to -# determine which symbols to keep in memory and which to flush to disk. -# When the cache is full, less often used symbols will be written to disk. -# For small to medium size projects (<1000 input files) the default value is -# probably good enough. For larger projects a too small cache size can cause -# doxygen to be busy swapping symbols to and from disk most of the time -# causing a significant performance penality. -# If the system has enough physical memory increasing the cache will improve the -# performance by keeping more symbols in memory. Note that the value works on -# a logarithmic scale so increasing the size by one will rougly double the -# memory usage. The cache size is given by this formula: -# 2^(16+SYMBOL_CACHE_SIZE). The valid range is 0..9, the default is 0, -# corresponding to a cache size of 2^16 = 65536 symbols - -SYMBOL_CACHE_SIZE = 0 - -#--------------------------------------------------------------------------- -# Build related configuration options -#--------------------------------------------------------------------------- - -# If the EXTRACT_ALL tag is set to YES doxygen will assume all entities in -# documentation are documented, even if no documentation was available. -# Private class members and static file members will be hidden unless -# the EXTRACT_PRIVATE and EXTRACT_STATIC tags are set to YES - -EXTRACT_ALL = YES - -# If the EXTRACT_PRIVATE tag is set to YES all private members of a class -# will be included in the documentation. - -EXTRACT_PRIVATE = NO - -# If the EXTRACT_STATIC tag is set to YES all static members of a file -# will be included in the documentation. - -EXTRACT_STATIC = YES - -# If the EXTRACT_LOCAL_CLASSES tag is set to YES classes (and structs) -# defined locally in source files will be included in the documentation. -# If set to NO only classes defined in header files are included. - -EXTRACT_LOCAL_CLASSES = YES - -# This flag is only useful for Objective-C code. When set to YES local -# methods, which are defined in the implementation section but not in -# the interface are included in the documentation. -# If set to NO (the default) only methods in the interface are included. - -EXTRACT_LOCAL_METHODS = NO - -# If this flag is set to YES, the members of anonymous namespaces will be -# extracted and appear in the documentation as a namespace called -# 'anonymous_namespace{file}', where file will be replaced with the base -# name of the file that contains the anonymous namespace. By default -# anonymous namespace are hidden. - -EXTRACT_ANON_NSPACES = NO - -# If the HIDE_UNDOC_MEMBERS tag is set to YES, Doxygen will hide all -# undocumented members of documented classes, files or namespaces. -# If set to NO (the default) these members will be included in the -# various overviews, but no documentation section is generated. -# This option has no effect if EXTRACT_ALL is enabled. - -HIDE_UNDOC_MEMBERS = NO - -# If the HIDE_UNDOC_CLASSES tag is set to YES, Doxygen will hide all -# undocumented classes that are normally visible in the class hierarchy. -# If set to NO (the default) these classes will be included in the various -# overviews. This option has no effect if EXTRACT_ALL is enabled. - -HIDE_UNDOC_CLASSES = NO - -# If the HIDE_FRIEND_COMPOUNDS tag is set to YES, Doxygen will hide all -# friend (class|struct|union) declarations. -# If set to NO (the default) these declarations will be included in the -# documentation. - -HIDE_FRIEND_COMPOUNDS = NO - -# If the HIDE_IN_BODY_DOCS tag is set to YES, Doxygen will hide any -# documentation blocks found inside the body of a function. -# If set to NO (the default) these blocks will be appended to the -# function's detailed documentation block. - -HIDE_IN_BODY_DOCS = NO - -# The INTERNAL_DOCS tag determines if documentation -# that is typed after a \internal command is included. If the tag is set -# to NO (the default) then the documentation will be excluded. -# Set it to YES to include the internal documentation. - -INTERNAL_DOCS = NO - -# If the CASE_SENSE_NAMES tag is set to NO then Doxygen will only generate -# file names in lower-case letters. If set to YES upper-case letters are also -# allowed. This is useful if you have classes or files whose names only differ -# in case and if your file system supports case sensitive file names. Windows -# and Mac users are advised to set this option to NO. - -CASE_SENSE_NAMES = YES - -# If the HIDE_SCOPE_NAMES tag is set to NO (the default) then Doxygen -# will show members with their full class and namespace scopes in the -# documentation. If set to YES the scope will be hidden. - -HIDE_SCOPE_NAMES = NO - -# If the SHOW_INCLUDE_FILES tag is set to YES (the default) then Doxygen -# will put a list of the files that are included by a file in the documentation -# of that file. - -SHOW_INCLUDE_FILES = YES - -# If the FORCE_LOCAL_INCLUDES tag is set to YES then Doxygen -# will list include files with double quotes in the documentation -# rather than with sharp brackets. - -FORCE_LOCAL_INCLUDES = NO - -# If the INLINE_INFO tag is set to YES (the default) then a tag [inline] -# is inserted in the documentation for inline members. - -INLINE_INFO = YES - -# If the SORT_MEMBER_DOCS tag is set to YES (the default) then doxygen -# will sort the (detailed) documentation of file and class members -# alphabetically by member name. If set to NO the members will appear in -# declaration order. - -SORT_MEMBER_DOCS = YES - -# If the SORT_BRIEF_DOCS tag is set to YES then doxygen will sort the -# brief documentation of file, namespace and class members alphabetically -# by member name. If set to NO (the default) the members will appear in -# declaration order. - -SORT_BRIEF_DOCS = NO - -# If the SORT_MEMBERS_CTORS_1ST tag is set to YES then doxygen -# will sort the (brief and detailed) documentation of class members so that -# constructors and destructors are listed first. If set to NO (the default) -# the constructors will appear in the respective orders defined by -# SORT_MEMBER_DOCS and SORT_BRIEF_DOCS. -# This tag will be ignored for brief docs if SORT_BRIEF_DOCS is set to NO -# and ignored for detailed docs if SORT_MEMBER_DOCS is set to NO. - -SORT_MEMBERS_CTORS_1ST = NO - -# If the SORT_GROUP_NAMES tag is set to YES then doxygen will sort the -# hierarchy of group names into alphabetical order. If set to NO (the default) -# the group names will appear in their defined order. - -SORT_GROUP_NAMES = NO - -# If the SORT_BY_SCOPE_NAME tag is set to YES, the class list will be -# sorted by fully-qualified names, including namespaces. If set to -# NO (the default), the class list will be sorted only by class name, -# not including the namespace part. -# Note: This option is not very useful if HIDE_SCOPE_NAMES is set to YES. -# Note: This option applies only to the class list, not to the -# alphabetical list. - -SORT_BY_SCOPE_NAME = NO - -# The GENERATE_TODOLIST tag can be used to enable (YES) or -# disable (NO) the todo list. This list is created by putting \todo -# commands in the documentation. - -GENERATE_TODOLIST = YES - -# The GENERATE_TESTLIST tag can be used to enable (YES) or -# disable (NO) the test list. This list is created by putting \test -# commands in the documentation. - -GENERATE_TESTLIST = YES - -# The GENERATE_BUGLIST tag can be used to enable (YES) or -# disable (NO) the bug list. This list is created by putting \bug -# commands in the documentation. - -GENERATE_BUGLIST = YES - -# The GENERATE_DEPRECATEDLIST tag can be used to enable (YES) or -# disable (NO) the deprecated list. This list is created by putting -# \deprecated commands in the documentation. - -GENERATE_DEPRECATEDLIST= YES - -# The ENABLED_SECTIONS tag can be used to enable conditional -# documentation sections, marked by \if sectionname ... \endif. - -ENABLED_SECTIONS = - -# The MAX_INITIALIZER_LINES tag determines the maximum number of lines -# the initial value of a variable or define consists of for it to appear in -# the documentation. If the initializer consists of more lines than specified -# here it will be hidden. Use a value of 0 to hide initializers completely. -# The appearance of the initializer of individual variables and defines in the -# documentation can be controlled using \showinitializer or \hideinitializer -# command in the documentation regardless of this setting. - -MAX_INITIALIZER_LINES = 30 - -# Set the SHOW_USED_FILES tag to NO to disable the list of files generated -# at the bottom of the documentation of classes and structs. If set to YES the -# list will mention the files that were used to generate the documentation. - -SHOW_USED_FILES = YES - -# If the sources in your project are distributed over multiple directories -# then setting the SHOW_DIRECTORIES tag to YES will show the directory hierarchy -# in the documentation. The default is NO. - -SHOW_DIRECTORIES = YES - -# Set the SHOW_FILES tag to NO to disable the generation of the Files page. -# This will remove the Files entry from the Quick Index and from the -# Folder Tree View (if specified). The default is YES. - -SHOW_FILES = YES - -# Set the SHOW_NAMESPACES tag to NO to disable the generation of the -# Namespaces page. -# This will remove the Namespaces entry from the Quick Index -# and from the Folder Tree View (if specified). The default is YES. - -SHOW_NAMESPACES = YES - -# The FILE_VERSION_FILTER tag can be used to specify a program or script that -# doxygen should invoke to get the current version for each file (typically from -# the version control system). Doxygen will invoke the program by executing (via -# popen()) the command <command> <input-file>, where <command> is the value of -# the FILE_VERSION_FILTER tag, and <input-file> is the name of an input file -# provided by doxygen. Whatever the program writes to standard output -# is used as the file version. See the manual for examples. - -FILE_VERSION_FILTER = - -# The LAYOUT_FILE tag can be used to specify a layout file which will be parsed -# by doxygen. The layout file controls the global structure of the generated -# output files in an output format independent way. The create the layout file -# that represents doxygen's defaults, run doxygen with the -l option. -# You can optionally specify a file name after the option, if omitted -# DoxygenLayout.xml will be used as the name of the layout file. - -LAYOUT_FILE = - -#--------------------------------------------------------------------------- -# configuration options related to warning and progress messages -#--------------------------------------------------------------------------- - -# The QUIET tag can be used to turn on/off the messages that are generated -# by doxygen. Possible values are YES and NO. If left blank NO is used. - -QUIET = YES - -# The WARNINGS tag can be used to turn on/off the warning messages that are -# generated by doxygen. Possible values are YES and NO. If left blank -# NO is used. - -WARNINGS = YES - -# If WARN_IF_UNDOCUMENTED is set to YES, then doxygen will generate warnings -# for undocumented members. If EXTRACT_ALL is set to YES then this flag will -# automatically be disabled. - -WARN_IF_UNDOCUMENTED = YES - -# If WARN_IF_DOC_ERROR is set to YES, doxygen will generate warnings for -# potential errors in the documentation, such as not documenting some -# parameters in a documented function, or documenting parameters that -# don't exist or using markup commands wrongly. - -WARN_IF_DOC_ERROR = YES - -# This WARN_NO_PARAMDOC option can be abled to get warnings for -# functions that are documented, but have no documentation for their parameters -# or return value. If set to NO (the default) doxygen will only warn about -# wrong or incomplete parameter documentation, but not about the absence of -# documentation. - -WARN_NO_PARAMDOC = YES - -# The WARN_FORMAT tag determines the format of the warning messages that -# doxygen can produce. The string should contain the $file, $line, and $text -# tags, which will be replaced by the file and line number from which the -# warning originated and the warning text. Optionally the format may contain -# $version, which will be replaced by the version of the file (if it could -# be obtained via FILE_VERSION_FILTER) - -WARN_FORMAT = "$file:$line: $text" - -# The WARN_LOGFILE tag can be used to specify a file to which warning -# and error messages should be written. If left blank the output is written -# to stderr. - -WARN_LOGFILE = - -#--------------------------------------------------------------------------- -# configuration options related to the input files -#--------------------------------------------------------------------------- - -# The INPUT tag can be used to specify the files and/or directories that contain -# documented source files. You may enter file names like "myfile.cpp" or -# directories like "/usr/src/myproject". Separate the files or directories -# with spaces. - -INPUT = . - -# This tag can be used to specify the character encoding of the source files -# that doxygen parses. Internally doxygen uses the UTF-8 encoding, which is -# also the default input encoding. Doxygen uses libiconv (or the iconv built -# into libc) for the transcoding. See http://www.gnu.org/software/libiconv for -# the list of possible encodings. - -INPUT_ENCODING = UTF-8 - -# If the value of the INPUT tag contains directories, you can use the -# FILE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp -# and *.h) to filter out the source-files in the directories. If left -# blank the following patterns are tested: -# *.c *.cc *.cxx *.cpp *.c++ *.java *.ii *.ixx *.ipp *.i++ *.inl *.h *.hh *.hxx -# *.hpp *.h++ *.idl *.odl *.cs *.php *.php3 *.inc *.m *.mm *.py *.f90 - -FILE_PATTERNS = - -# The RECURSIVE tag can be used to turn specify whether or not subdirectories -# should be searched for input files as well. Possible values are YES and NO. -# If left blank NO is used. - -RECURSIVE = YES - -# The EXCLUDE tag can be used to specify files and/or directories that should -# excluded from the INPUT source files. This way you can easily exclude a -# subdirectory from a directory tree whose root is specified with the INPUT tag. - -EXCLUDE = util/romcc/tests \ - util/vgabios \ - util/abuild \ - util/kconfig \ - payloads - -# The EXCLUDE_SYMLINKS tag can be used select whether or not files or -# directories that are symbolic links (a Unix filesystem feature) are excluded -# from the input. - -EXCLUDE_SYMLINKS = NO - -# If the value of the INPUT tag contains directories, you can use the -# EXCLUDE_PATTERNS tag to specify one or more wildcard patterns to exclude -# certain files from those directories. Note that the wildcards are matched -# against the file with absolute path, so to exclude all test directories -# for example use the pattern */test/* - -EXCLUDE_PATTERNS = - -# The EXCLUDE_SYMBOLS tag can be used to specify one or more symbol names -# (namespaces, classes, functions, etc.) that should be excluded from the -# output. The symbol name can be a fully qualified name, a word, or if the -# wildcard * is used, a substring. Examples: ANamespace, AClass, -# AClass::ANamespace, ANamespace::*Test - -EXCLUDE_SYMBOLS = - -# The EXAMPLE_PATH tag can be used to specify one or more files or -# directories that contain example code fragments that are included (see -# the \include command). - -EXAMPLE_PATH = - -# If the value of the EXAMPLE_PATH tag contains directories, you can use the -# EXAMPLE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp -# and *.h) to filter out the source-files in the directories. If left -# blank all files are included. - -EXAMPLE_PATTERNS = - -# If the EXAMPLE_RECURSIVE tag is set to YES then subdirectories will be -# searched for input files to be used with the \include or \dontinclude -# commands irrespective of the value of the RECURSIVE tag. -# Possible values are YES and NO. If left blank NO is used. - -EXAMPLE_RECURSIVE = NO - -# The IMAGE_PATH tag can be used to specify one or more files or -# directories that contain image that are included in the documentation (see -# the \image command). - -IMAGE_PATH = - -# The INPUT_FILTER tag can be used to specify a program that doxygen should -# invoke to filter for each input file. Doxygen will invoke the filter program -# by executing (via popen()) the command <filter> <input-file>, where <filter> -# is the value of the INPUT_FILTER tag, and <input-file> is the name of an -# input file. Doxygen will then use the output that the filter program writes -# to standard output. -# If FILTER_PATTERNS is specified, this tag will be -# ignored. - -INPUT_FILTER = - -# The FILTER_PATTERNS tag can be used to specify filters on a per file pattern -# basis. -# Doxygen will compare the file name with each pattern and apply the -# filter if there is a match. -# The filters are a list of the form: -# pattern=filter (like *.cpp=my_cpp_filter). See INPUT_FILTER for further -# info on how filters are used. If FILTER_PATTERNS is empty, INPUT_FILTER -# is applied to all files. - -FILTER_PATTERNS = - -# If the FILTER_SOURCE_FILES tag is set to YES, the input filter (if set using -# INPUT_FILTER) will be used to filter the input files when producing source -# files to browse (i.e. when SOURCE_BROWSER is set to YES). - -FILTER_SOURCE_FILES = NO - -#--------------------------------------------------------------------------- -# configuration options related to source browsing -#--------------------------------------------------------------------------- - -# If the SOURCE_BROWSER tag is set to YES then a list of source files will -# be generated. Documented entities will be cross-referenced with these sources. -# Note: To get rid of all source code in the generated output, make sure also -# VERBATIM_HEADERS is set to NO. - -SOURCE_BROWSER = YES - -# Setting the INLINE_SOURCES tag to YES will include the body -# of functions and classes directly in the documentation. - -INLINE_SOURCES = NO - -# Setting the STRIP_CODE_COMMENTS tag to YES (the default) will instruct -# doxygen to hide any special comment blocks from generated source code -# fragments. Normal C and C++ comments will always remain visible. - -STRIP_CODE_COMMENTS = NO - -# If the REFERENCED_BY_RELATION tag is set to YES -# then for each documented function all documented -# functions referencing it will be listed. - -REFERENCED_BY_RELATION = YES - -# If the REFERENCES_RELATION tag is set to YES -# then for each documented function all documented entities -# called/used by that function will be listed. - -REFERENCES_RELATION = YES - -# If the REFERENCES_LINK_SOURCE tag is set to YES (the default) -# and SOURCE_BROWSER tag is set to YES, then the hyperlinks from -# functions in REFERENCES_RELATION and REFERENCED_BY_RELATION lists will -# link to the source code. -# Otherwise they will link to the documentation. - -REFERENCES_LINK_SOURCE = YES - -# If the USE_HTAGS tag is set to YES then the references to source code -# will point to the HTML generated by the htags(1) tool instead of doxygen -# built-in source browser. The htags tool is part of GNU's global source -# tagging system (see http://www.gnu.org/software/global/global.html). You -# will need version 4.8.6 or higher. - -USE_HTAGS = NO - -# If the VERBATIM_HEADERS tag is set to YES (the default) then Doxygen -# will generate a verbatim copy of the header file for each class for -# which an include is specified. Set to NO to disable this. - -VERBATIM_HEADERS = YES - -#--------------------------------------------------------------------------- -# configuration options related to the alphabetical class index -#--------------------------------------------------------------------------- - -# If the ALPHABETICAL_INDEX tag is set to YES, an alphabetical index -# of all compounds will be generated. Enable this if the project -# contains a lot of classes, structs, unions or interfaces. - -ALPHABETICAL_INDEX = YES - -# If the alphabetical index is enabled (see ALPHABETICAL_INDEX) then -# the COLS_IN_ALPHA_INDEX tag can be used to specify the number of columns -# in which this list will be split (can be a number in the range [1..20]) - -COLS_IN_ALPHA_INDEX = 5 - -# In case all classes in a project start with a common prefix, all -# classes will be put under the same header in the alphabetical index. -# The IGNORE_PREFIX tag can be used to specify one or more prefixes that -# should be ignored while generating the index headers. - -IGNORE_PREFIX = - -#--------------------------------------------------------------------------- -# configuration options related to the HTML output -#--------------------------------------------------------------------------- - -# If the GENERATE_HTML tag is set to YES (the default) Doxygen will -# generate HTML output. - -GENERATE_HTML = YES - -# The HTML_OUTPUT tag is used to specify where the HTML docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `html' will be used as the default path. - -HTML_OUTPUT = html - -# The HTML_FILE_EXTENSION tag can be used to specify the file extension for -# each generated HTML page (for example: .htm,.php,.asp). If it is left blank -# doxygen will generate files with .html extension. - -HTML_FILE_EXTENSION = .html - -# The HTML_HEADER tag can be used to specify a personal HTML header for -# each generated HTML page. If it is left blank doxygen will generate a -# standard header. - -HTML_HEADER = - -# The HTML_FOOTER tag can be used to specify a personal HTML footer for -# each generated HTML page. If it is left blank doxygen will generate a -# standard footer. - -HTML_FOOTER = - -# If the HTML_FOOTER_DESCRIPTION tag is set to YES, Doxygen will -# add generated date, project name and doxygen version to HTML footer. - -HTML_FOOTER_DESCRIPTION= YES - -# The HTML_STYLESHEET tag can be used to specify a user-defined cascading -# style sheet that is used by each HTML page. It can be used to -# fine-tune the look of the HTML output. If the tag is left blank doxygen -# will generate a default style sheet. Note that doxygen will try to copy -# the style sheet file to the HTML output directory, so don't put your own -# stylesheet in the HTML output directory as well, or it will be erased! - -HTML_STYLESHEET = - -# The HTML_COLORSTYLE_HUE tag controls the color of the HTML output. -# Doxygen will adjust the colors in the stylesheet and background images -# according to this color. Hue is specified as an angle on a colorwheel, -# see http://en.wikipedia.org/wiki/Hue for more information. -# For instance the value 0 represents red, 60 is yellow, 120 is green, -# 180 is cyan, 240 is blue, 300 purple, and 360 is red again. -# The allowed range is 0 to 359. - -HTML_COLORSTYLE_HUE = 220 - -# The HTML_COLORSTYLE_SAT tag controls the purity (or saturation) of -# the colors in the HTML output. For a value of 0 the output will use -# grayscales only. A value of 255 will produce the most vivid colors. - -HTML_COLORSTYLE_SAT = 100 - -# The HTML_COLORSTYLE_GAMMA tag controls the gamma correction applied to -# the luminance component of the colors in the HTML output. Values below -# 100 gradually make the output lighter, whereas values above 100 make -# the output darker. The value divided by 100 is the actual gamma applied, -# so 80 represents a gamma of 0.8, The value 220 represents a gamma of 2.2, -# and 100 does not change the gamma. - -HTML_COLORSTYLE_GAMMA = 80 - -# If the HTML_TIMESTAMP tag is set to YES then the footer of each generated HTML -# page will contain the date and time when the page was generated. Setting -# this to NO can help when comparing the output of multiple runs. - -HTML_TIMESTAMP = NO - -# If the HTML_ALIGN_MEMBERS tag is set to YES, the members of classes, -# files or namespaces will be aligned in HTML using tables. If set to -# NO a bullet list will be used. - -HTML_ALIGN_MEMBERS = YES - -# If the HTML_DYNAMIC_SECTIONS tag is set to YES then the generated HTML -# documentation will contain sections that can be hidden and shown after the -# page has loaded. For this to work a browser that supports -# JavaScript and DHTML is required (for instance Mozilla 1.0+, Firefox -# Netscape 6.0+, Internet explorer 5.0+, Konqueror, or Safari). - -HTML_DYNAMIC_SECTIONS = NO - -# If the GENERATE_DOCSET tag is set to YES, additional index files -# will be generated that can be used as input for Apple's Xcode 3 -# integrated development environment, introduced with OSX 10.5 (Leopard). -# To create a documentation set, doxygen will generate a Makefile in the -# HTML output directory. Running make will produce the docset in that -# directory and running "make install" will install the docset in -# ~/Library/Developer/Shared/Documentation/DocSets so that Xcode will find -# it at startup. -# See http://developer.apple.com/tools/creatingdocsetswithdoxygen.html -# for more information. - -GENERATE_DOCSET = NO - -# When GENERATE_DOCSET tag is set to YES, this tag determines the name of the -# feed. A documentation feed provides an umbrella under which multiple -# documentation sets from a single provider (such as a company or product suite) -# can be grouped. - -DOCSET_FEEDNAME = "Doxygen documentation" - -# When GENERATE_DOCSET tag is set to YES, this tag specifies a string that -# should uniquely identify the documentation set bundle. This should be a -# reverse domain-name style string, e.g. com.mycompany.MyDocSet. Doxygen -# will append .docset to the name. - -DOCSET_BUNDLE_ID = org.doxygen.Project - -# When GENERATE_PUBLISHER_ID tag specifies a string that should uniquely identify -# the documentation publisher. This should be a reverse domain-name style -# string, e.g. com.mycompany.MyDocSet.documentation. - -DOCSET_PUBLISHER_ID = org.doxygen.Publisher - -# The GENERATE_PUBLISHER_NAME tag identifies the documentation publisher. - -DOCSET_PUBLISHER_NAME = Publisher - -# If the GENERATE_HTMLHELP tag is set to YES, additional index files -# will be generated that can be used as input for tools like the -# Microsoft HTML help workshop to generate a compiled HTML help file (.chm) -# of the generated HTML documentation. - -GENERATE_HTMLHELP = NO - -# If the GENERATE_HTMLHELP tag is set to YES, the CHM_FILE tag can -# be used to specify the file name of the resulting .chm file. You -# can add a path in front of the file if the result should not be -# written to the html output directory. - -CHM_FILE = - -# If the GENERATE_HTMLHELP tag is set to YES, the HHC_LOCATION tag can -# be used to specify the location (absolute path including file name) of -# the HTML help compiler (hhc.exe). If non-empty doxygen will try to run -# the HTML help compiler on the generated index.hhp. - -HHC_LOCATION = - -# If the GENERATE_HTMLHELP tag is set to YES, the GENERATE_CHI flag -# controls if a separate .chi index file is generated (YES) or that -# it should be included in the master .chm file (NO). - -GENERATE_CHI = NO - -# If the GENERATE_HTMLHELP tag is set to YES, the CHM_INDEX_ENCODING -# is used to encode HtmlHelp index (hhk), content (hhc) and project file -# content. - -CHM_INDEX_ENCODING = - -# If the GENERATE_HTMLHELP tag is set to YES, the BINARY_TOC flag -# controls whether a binary table of contents is generated (YES) or a -# normal table of contents (NO) in the .chm file. - -BINARY_TOC = NO - -# The TOC_EXPAND flag can be set to YES to add extra items for group members -# to the contents of the HTML help documentation and to the tree view. - -TOC_EXPAND = NO - -# If the GENERATE_QHP tag is set to YES and both QHP_NAMESPACE and -# QHP_VIRTUAL_FOLDER are set, an additional index file will be generated -# that can be used as input for Qt's qhelpgenerator to generate a -# Qt Compressed Help (.qch) of the generated HTML documentation. - -GENERATE_QHP = NO - -# If the QHG_LOCATION tag is specified, the QCH_FILE tag can -# be used to specify the file name of the resulting .qch file. -# The path specified is relative to the HTML output folder. - -QCH_FILE = - -# The QHP_NAMESPACE tag specifies the namespace to use when generating -# Qt Help Project output. For more information please see -# http://doc.trolltech.com/qthelpproject.html#namespace - -QHP_NAMESPACE = org.doxygen.Project - -# The QHP_VIRTUAL_FOLDER tag specifies the namespace to use when generating -# Qt Help Project output. For more information please see -# http://doc.trolltech.com/qthelpproject.html#virtual-folders - -QHP_VIRTUAL_FOLDER = doc - -# If QHP_CUST_FILTER_NAME is set, it specifies the name of a custom filter to -# add. For more information please see -# http://doc.trolltech.com/qthelpproject.html#custom-filters - -QHP_CUST_FILTER_NAME = - -# The QHP_CUST_FILT_ATTRS tag specifies the list of the attributes of the -# custom filter to add. For more information please see -# <a href="http://doc.trolltech.com/qthelpproject.html#custom-filters"> -# Qt Help Project / Custom Filters</a>. - -QHP_CUST_FILTER_ATTRS = - -# The QHP_SECT_FILTER_ATTRS tag specifies the list of the attributes this -# project's -# filter section matches. -# <a href="http://doc.trolltech.com/qthelpproject.html#filter-attributes"> -# Qt Help Project / Filter Attributes</a>. - -QHP_SECT_FILTER_ATTRS = - -# If the GENERATE_QHP tag is set to YES, the QHG_LOCATION tag can -# be used to specify the location of Qt's qhelpgenerator. -# If non-empty doxygen will try to run qhelpgenerator on the generated -# .qhp file. - -QHG_LOCATION = - -# If the GENERATE_ECLIPSEHELP tag is set to YES, additional index files -# will be generated, which together with the HTML files, form an Eclipse help -# plugin. To install this plugin and make it available under the help contents -# menu in Eclipse, the contents of the directory containing the HTML and XML -# files needs to be copied into the plugins directory of eclipse. The name of -# the directory within the plugins directory should be the same as -# the ECLIPSE_DOC_ID value. After copying Eclipse needs to be restarted before -# the help appears. - -GENERATE_ECLIPSEHELP = NO - -# A unique identifier for the eclipse help plugin. When installing the plugin -# the directory name containing the HTML and XML files should also have -# this name. - -ECLIPSE_DOC_ID = org.doxygen.Project - -# The DISABLE_INDEX tag can be used to turn on/off the condensed index at -# top of each HTML page. The value NO (the default) enables the index and -# the value YES disables it. - -DISABLE_INDEX = NO - -# This tag can be used to set the number of enum values (range [1..20]) -# that doxygen will group on one line in the generated HTML documentation. - -ENUM_VALUES_PER_LINE = 4 - -# The GENERATE_TREEVIEW tag is used to specify whether a tree-like index -# structure should be generated to display hierarchical information. -# If the tag value is set to YES, a side panel will be generated -# containing a tree-like index structure (just like the one that -# is generated for HTML Help). For this to work a browser that supports -# JavaScript, DHTML, CSS and frames is required (i.e. any modern browser). -# Windows users are probably better off using the HTML help feature. - -GENERATE_TREEVIEW = YES - -# By enabling USE_INLINE_TREES, doxygen will generate the Groups, Directories, -# and Class Hierarchy pages using a tree view instead of an ordered list. - -USE_INLINE_TREES = YES - -# If the treeview is enabled (see GENERATE_TREEVIEW) then this tag can be -# used to set the initial width (in pixels) of the frame in which the tree -# is shown. - -TREEVIEW_WIDTH = 250 - -# When the EXT_LINKS_IN_WINDOW option is set to YES doxygen will open -# links to external symbols imported via tag files in a separate window. - -EXT_LINKS_IN_WINDOW = NO - -# Use this tag to change the font size of Latex formulas included -# as images in the HTML documentation. The default is 10. Note that -# when you change the font size after a successful doxygen run you need -# to manually remove any form_*.png images from the HTML output directory -# to force them to be regenerated. - -FORMULA_FONTSIZE = 10 - -# Use the FORMULA_TRANPARENT tag to determine whether or not the images -# generated for formulas are transparent PNGs. Transparent PNGs are -# not supported properly for IE 6.0, but are supported on all modern browsers. -# Note that when changing this option you need to delete any form_*.png files -# in the HTML output before the changes have effect. - -FORMULA_TRANSPARENT = YES - -# When the SEARCHENGINE tag is enabled doxygen will generate a search box -# for the HTML output. The underlying search engine uses javascript -# and DHTML and should work on any modern browser. Note that when using -# HTML help (GENERATE_HTMLHELP), Qt help (GENERATE_QHP), or docsets -# (GENERATE_DOCSET) there is already a search function so this one should -# typically be disabled. For large projects the javascript based search engine -# can be slow, then enabling SERVER_BASED_SEARCH may provide a better solution. - -SEARCHENGINE = YES - -# When the SERVER_BASED_SEARCH tag is enabled the search engine will be -# implemented using a PHP enabled web server instead of at the web client -# using Javascript. Doxygen will generate the search PHP script and index -# file to put on the web server. The advantage of the server -# based approach is that it scales better to large projects and allows -# full text search. The disadvances is that it is more difficult to setup -# and does not have live searching capabilities. - -SERVER_BASED_SEARCH = NO - -#--------------------------------------------------------------------------- -# configuration options related to the LaTeX output -#--------------------------------------------------------------------------- - -# If the GENERATE_LATEX tag is set to YES (the default) Doxygen will -# generate Latex output. - -GENERATE_LATEX = NO - -# The LATEX_OUTPUT tag is used to specify where the LaTeX docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `latex' will be used as the default path. - -LATEX_OUTPUT = latex - -# The LATEX_CMD_NAME tag can be used to specify the LaTeX command name to be -# invoked. If left blank `latex' will be used as the default command name. -# Note that when enabling USE_PDFLATEX this option is only used for -# generating bitmaps for formulas in the HTML output, but not in the -# Makefile that is written to the output directory. - -LATEX_CMD_NAME = latex - -# The MAKEINDEX_CMD_NAME tag can be used to specify the command name to -# generate index for LaTeX. If left blank `makeindex' will be used as the -# default command name. - -MAKEINDEX_CMD_NAME = makeindex - -# If the COMPACT_LATEX tag is set to YES Doxygen generates more compact -# LaTeX documents. This may be useful for small projects and may help to -# save some trees in general. - -COMPACT_LATEX = NO - -# The PAPER_TYPE tag can be used to set the paper type that is used -# by the printer. Possible values are: a4, a4wide, letter, legal and -# executive. If left blank a4wide will be used. - -PAPER_TYPE = a4wide - -# The EXTRA_PACKAGES tag can be to specify one or more names of LaTeX -# packages that should be included in the LaTeX output. - -EXTRA_PACKAGES = - -# The LATEX_HEADER tag can be used to specify a personal LaTeX header for -# the generated latex document. The header should contain everything until -# the first chapter. If it is left blank doxygen will generate a -# standard header. Notice: only use this tag if you know what you are doing! - -LATEX_HEADER = - -# If the PDF_HYPERLINKS tag is set to YES, the LaTeX that is generated -# is prepared for conversion to pdf (using ps2pdf). The pdf file will -# contain links (just like the HTML output) instead of page references -# This makes the output suitable for online browsing using a pdf viewer. - -PDF_HYPERLINKS = NO - -# If the USE_PDFLATEX tag is set to YES, pdflatex will be used instead of -# plain latex in the generated Makefile. Set this option to YES to get a -# higher quality PDF documentation. - -USE_PDFLATEX = NO - -# If the LATEX_BATCHMODE tag is set to YES, doxygen will add the \\batchmode. -# command to the generated LaTeX files. This will instruct LaTeX to keep -# running if errors occur, instead of asking the user for help. -# This option is also used when generating formulas in HTML. - -LATEX_BATCHMODE = NO - -# If LATEX_HIDE_INDICES is set to YES then doxygen will not -# include the index chapters (such as File Index, Compound Index, etc.) -# in the output. - -LATEX_HIDE_INDICES = NO - -# If LATEX_SOURCE_CODE is set to YES then doxygen will include -# source code with syntax highlighting in the LaTeX output. -# Note that which sources are shown also depends on other settings -# such as SOURCE_BROWSER. - -LATEX_SOURCE_CODE = NO - -#--------------------------------------------------------------------------- -# configuration options related to the RTF output -#--------------------------------------------------------------------------- - -# If the GENERATE_RTF tag is set to YES Doxygen will generate RTF output -# The RTF output is optimized for Word 97 and may not look very pretty with -# other RTF readers or editors. - -GENERATE_RTF = NO - -# The RTF_OUTPUT tag is used to specify where the RTF docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `rtf' will be used as the default path. - -RTF_OUTPUT = rtf - -# If the COMPACT_RTF tag is set to YES Doxygen generates more compact -# RTF documents. This may be useful for small projects and may help to -# save some trees in general. - -COMPACT_RTF = NO - -# If the RTF_HYPERLINKS tag is set to YES, the RTF that is generated -# will contain hyperlink fields. The RTF file will -# contain links (just like the HTML output) instead of page references. -# This makes the output suitable for online browsing using WORD or other -# programs which support those fields. -# Note: wordpad (write) and others do not support links. - -RTF_HYPERLINKS = NO - -# Load stylesheet definitions from file. Syntax is similar to doxygen's -# config file, i.e. a series of assignments. You only have to provide -# replacements, missing definitions are set to their default value. - -RTF_STYLESHEET_FILE = - -# Set optional variables used in the generation of an rtf document. -# Syntax is similar to doxygen's config file. - -RTF_EXTENSIONS_FILE = - -#--------------------------------------------------------------------------- -# configuration options related to the man page output -#--------------------------------------------------------------------------- - -# If the GENERATE_MAN tag is set to YES (the default) Doxygen will -# generate man pages - -GENERATE_MAN = NO - -# The MAN_OUTPUT tag is used to specify where the man pages will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `man' will be used as the default path. - -MAN_OUTPUT = man - -# The MAN_EXTENSION tag determines the extension that is added to -# the generated man pages (default is the subroutine's section .3) - -MAN_EXTENSION = .3 - -# If the MAN_LINKS tag is set to YES and Doxygen generates man output, -# then it will generate one additional man file for each entity -# documented in the real man page(s). These additional files -# only source the real man page, but without them the man command -# would be unable to find the correct page. The default is NO. - -MAN_LINKS = NO - -#--------------------------------------------------------------------------- -# configuration options related to the XML output -#--------------------------------------------------------------------------- - -# If the GENERATE_XML tag is set to YES Doxygen will -# generate an XML file that captures the structure of -# the code including all documentation. - -GENERATE_XML = NO - -# The XML_OUTPUT tag is used to specify where the XML pages will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. 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<tr><td colspan=2><b>Legend</b></td></tr> - <tr><td bgcolor="#ffc0c0">Red</td><td>Required - To-be-implemented</td></tr> - <tr><td bgcolor="#ffffc0">Yellow</td><td>Optional</td></tr> - <tr><td bgcolor="#c0ffc0">Green</td><td>Implemented</td></tr> -</table> -<table> - <tr valign="top"> - <td> -<table border=1> -<tr><th colspan=2>bootblock: 100% Done</th></tr> -<tr><th>Type</th><th>Routine</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>bootblock_c_entry</td></tr> -<tr bgcolor=#c0ffc0><td>Required</td><td>bootblock_main_with_timestamp</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>bootblock_mainboard_early_init</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>bootblock_mainboard_init</td></tr> -<tr bgcolor=#c0ffc0><td>Required</td><td>bootblock_pre_c_entry</td></tr> -<tr bgcolor=#c0ffc0><td>Required</td><td>bootblock_protected_mode_entry</td></tr> -<tr bgcolor=#c0ffc0><td>Required</td><td>bootblock_soc_early_init</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>bootblock_soc_init</td></tr> -<tr bgcolor=#c0ffc0><td>Required</td><td>tsc_freq_mhz</td></tr> -<tr bgcolor=#c0ffc0><td>Required</td><td>uart_init</td></tr> -</table> - </td> - <td width=5> </td> - <td> -<table border=1> -<tr><th colspan=2>romstage: 66% Done</th></tr> -<tr><th>Type</th><th>Routine</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>arch_segment_loaded</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>backup_top_of_ram</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>boot_device_init</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>car_mainboard_post_console_init</td></tr> -<tr bgcolor=#c0ffc0><td>Required</td><td>car_mainboard_pre_console_init</td></tr> -<tr bgcolor=#c0ffc0><td>Required</td><td>car_soc_post_console_init</td></tr> -<tr bgcolor=#c0ffc0><td>Required</td><td>car_soc_pre_console_init</td></tr> -<tr bgcolor=#c0ffc0><td>Required</td><td>car_stage_entry</td></tr> -<tr bgcolor=#c0ffc0><td>Required</td><td>cbfs_master_header_locator</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>cbmem_fail_resume</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>clear_recovery_mode_switch</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>cpu_smi_handler</td></tr> -<tr bgcolor=#c0ffc0><td>Required</td><td>fill_power_state</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>get_sw_write_protect_state</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>get_top_of_ram</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>gpio_acpi_path</td></tr> -<tr bgcolor=#c0ffc0><td>Required</td><td>init_timer</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>mainboard_add_dimm_info</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>mainboard_check_ec_image</td></tr> -<tr bgcolor=#ffc0c0><td>Required</td><td>mainboard_fill_spd_data</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>mainboard_io_trap_handler</td></tr> -<tr bgcolor=#ffc0c0><td>Required</td><td>mainboard_memory_init_params</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>mainboard_post</td></tr> -<tr bgcolor=#c0ffc0><td>Required</td><td>mainboard_romstage_entry</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>mainboard_save_dimm_info</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>mainboard_smi_apmc</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>mainboard_smi_gpi</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>mainboard_smi_sleep</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>map_oprom_vendev</td></tr> -<tr bgcolor=#ffc0c0><td>Required</td><td>migrate_power_state</td></tr> -<tr bgcolor=#ffc0c0><td>Required</td><td>mrc_cache_get_current_with_version</td></tr> -<tr bgcolor=#ffc0c0><td>Required</td><td>mrc_cache_stash_data_with_version</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>platform_prog_run</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>platform_segment_loaded</td></tr> -<tr bgcolor=#c0ffc0><td>Required</td><td>print_fsp_info</td></tr> -<tr bgcolor=#c0ffc0><td>Required</td><td>raminit</td></tr> -<tr bgcolor=#c0ffc0><td>Required</td><td>ramstage_cache_invalid</td></tr> -<tr bgcolor=#ffc0c0><td>Required</td><td>report_memory_config</td></tr> -<tr bgcolor=#c0ffc0><td>Required</td><td>romstage_common</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>save_chromeos_gpios</td></tr> -<tr bgcolor=#ffc0c0><td>Required</td><td>set_max_freq</td></tr> -<tr bgcolor=#c0ffc0><td>Required</td><td>setup_stack_and_mtrrs</td></tr> -<tr bgcolor=#ffc0c0><td>Required</td><td>smm_region</td></tr> -<tr bgcolor=#ffc0c0><td>Required</td><td>smm_region_size</td></tr> -<tr bgcolor=#c0ffc0><td>Required</td><td>soc_after_ram_init</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>soc_display_memory_init_params</td></tr> -<tr bgcolor=#c0ffc0><td>Required</td><td>soc_display_mtrrs</td></tr> -<tr bgcolor=#c0ffc0><td>Required</td><td>soc_get_variable_mtrr_count</td></tr> -<tr bgcolor=#c0ffc0><td>Required</td><td>soc_memory_init_params</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>soc_pre_ram_init</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>southbridge_smi_handler</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>stage_cache_add</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>stage_cache_load_stage</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>timestamp_get</td></tr> -<tr bgcolor=#c0ffc0><td>Required</td><td>tsc_freq_mhz</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>vb2ex_hwcrypto_digest_extend</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>vb2ex_hwcrypto_digest_finalize</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>vb2ex_hwcrypto_digest_init</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>vboot_platform_prepare_reboot</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>verstage_mainboard_init</td></tr> -</table> - </td> - <td width=5> </td> - <td> -<table border=1> -<tr><th colspan=2>ramstage: 55% Done</th></tr> -<tr><th>Type</th><th>Routine</td></tr> -<tr bgcolor=#ffc0c0><td>Required</td><td>acpi_create_serialio_ssdt</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>arch_segment_loaded</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>backup_top_of_ram</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>boot_device_init</td></tr> -<tr bgcolor=#c0ffc0><td>Required</td><td>cbfs_master_header_locator</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>cbmem_fail_resume</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>clear_recovery_mode_switch</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>cpu_smi_handler</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>fw_cfg_acpi_tables</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>get_sw_write_protect_state</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>get_top_of_ram</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>gpio_acpi_path</td></tr> -<tr bgcolor=#c0ffc0><td>Required</td><td>init_timer</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>lb_board</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>lb_framebuffer</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>mainboard_add_dimm_info</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>mainboard_io_trap_handler</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>mainboard_post</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>mainboard_silicon_init_params</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>mainboard_smi_apmc</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>mainboard_smi_gpi</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>mainboard_smi_sleep</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>mainboard_suspend_resume</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>map_oprom_vendev</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>mirror_payload</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>northbridge_smi_handler</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>nvm_mmio_to_flash_offset</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>platform_prog_run</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>platform_segment_loaded</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>save_chromeos_gpios</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>smbios_mainboard_bios_version</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>smbios_mainboard_manufacturer</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>smbios_mainboard_product_name</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>smbios_mainboard_serial_number</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>smbios_mainboard_set_uuid</td></tr> -<tr bgcolor=#c0ffc0><td>Required</td><td>smbios_mainboard_version</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>smm_disable_busmaster</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>soc_after_silicon_init</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>soc_display_silicon_init_params</td></tr> -<tr bgcolor=#ffc0c0><td>Required</td><td>soc_fill_acpi_wake</td></tr> -<tr bgcolor=#c0ffc0><td>Required</td><td>soc_silicon_init_params</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>soc_skip_ucode_update</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>southbridge_smi_handler</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>stage_cache_add</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>stage_cache_load_stage</td></tr> -<tr bgcolor=#ffc0c0><td>Required</td><td>timestamp_get</td></tr> -<tr bgcolor=#ffc0c0><td>Required</td><td>timestamp_tick_freq_mhz</td></tr> -<tr bgcolor=#c0ffc0><td>Required</td><td>tsc_freq_mhz</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>vb2ex_hwcrypto_digest_extend</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>vb2ex_hwcrypto_digest_finalize</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>vb2ex_hwcrypto_digest_init</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>wifi_regulatory_domain</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>write_smp_table</td></tr> -</table> - </td> - <td width=5> </td> - </tr> -</table> -</body> -</html> diff --git a/Documentation/Intel/Board/board.html b/Documentation/Intel/Board/board.html deleted file mode 100644 index 1b2d323..0000000 --- a/Documentation/Intel/Board/board.html +++ /dev/null @@ -1,240 +0,0 @@ -<!DOCTYPE html> -<html> - <head> - <title>Board</title> - </head> - <body> - -<h1>x86 Board Development</h1> -<p> - Board development requires System-on-a-Chip (SoC) support. - The combined steps are listed - <a target="_blank" href="../development.html">here</a>. - The development steps for the board are listed below: -</p> -<ol> - <li><a href="#RequiredFiles">Required Files</a></li> - <li>Enable <a href="#SerialOutput">Serial Output</a></li> - <li>Load the <a href="#SpdData">Memory Timing Data</a></li> - <li><a href="#DisablePciDevices">Disable</a> the PCI devices</li> - <li><a href="#AcpiTables">ACPI Tables</a></li> -</ol> - - -<hr> -<h1><a name="RequiredFiles">Required Files</a></h1> -<p> - Create the board directory as src/mainboard/<Vendor>/<Board>. -</p> - -<p> - The following files are required to build a new board: -</p> -<ol> - <li>Kconfig.name - Defines the Kconfig value for the board</li> - <li>Kconfig - <ol type="A"> - <li>Selects the SoC for the board and specifies the SPI flash size - <ol type="I"> - <li>BOARD_ROMSIZE_KB_<Size></li> - <li>SOC_<Vendor>_<Chip Family></li> - </ol> - </li> - <li>Declare the Kconfig values for: - <ol type="I"> - <li>MAINBOARD_DIR</li> - <li>MAINBOARD_PART_NUMBER</li> - <li>MAINBOARD_VENDOR</li> - </ol> - </li> - </ol> - </li> - <li>devicetree.cb - Enable root bridge and serial port - <ol type="A"> - <li>The first line must be "chip soc/Intel/<soc family>"; - this path is used by the generated static.c to include the chip.h - header file - </li> - </ol> - </li> - <li>romstage.c - <ol type="A"> - <li>Add routine mainboard_romstage_entry which calls romstage_common</li> - </ol> - </li> - <li>Configure coreboot build: - <ol type="A"> - <li>Set LOCALVERSION</li> - <li>Select vendor for the board</li> - <li>Select the board</li> - <li>CBFS_SIZE = 0x00100000</li> - <li>Set the CPU_MICROCODE_CBFS_LEN</li> - <li>Set the CPU_MICROCODE_CBFS_LOC</li> - <li>Set the FSP_IMAGE_ID_STRING</li> - <li>Set the FSP_LOC</li> - <li>Disable GOP_SUPPORT</li> - <li>No payload</li> - <li>Choose the default value for all other options</li> - </ol> - </li> -</ol> - - -<hr> -<h1><a name="SerialOutput">Enable Serial Output</a></h1> -<p> - Use the following steps to enable serial output: -</p> -<ol> - <li>Implement the car_mainboard_pre_console_init routine in the com_init.c - file: - <ol type="A"> - <li>Power on and enable the UART controller</li> - <li>Connect the UART receive and transmit data lines to the - appropriate SoC pins - </li> - </ol> - </li> - <li>Add Makefile.inc - <ol type="A"> - <li>Add com_init.c to romstage</li> - </ol> - </li> -</ol> - - -<hr> -<h1><a name="SpdData">Memory Timing Data</a></h1> -<p> - Memory timing data is located in the flash. This data is in the format of - <a target="_blank" href="https://en.wikipedia.org/wiki/Serial_presence_detect">serial presence detect</a> - (SPD) data. - Use the following steps to load the SPD data: -</p> -<ol> - <li>Edit Kconfig to add the DISPLAY_SPD_DATA" value which enables the - display of the SPD data being passed to MemoryInit - </li> - <li>Create an "spd" subdirectory</li> - <li>Create an spd/spd.c file for the SPD implementation - <ol type="A"> - <li>Implement the mainboard_fill_spd_data routine - <ol type="i"> - <li>Read the SPD data either from the spd.bin file or using I2C or SMBUS</li> - <li>Fill in the pei_data structure with SPD data for each of the DIMMs</li> - <li>Set the DIMM channel configuration</li> - </ol> - </li> - </ol> - </li> - <li>Add an .spd.hex file containing the memory timing data to the spd subdirectory</li> - <li>Create spd/Makefile.inc - <ol type="A"> - <li>Add spd.c to romstage</li> - <li>Add the .spd.hex file to SPD_SOURCES</li> - </ol> - </li> - <li>Edit Makefile.inc to add the spd subdirectory</li> - <li>Edit romstage.c - <ol type="A"> - <li>Call mainboard_fill_spd_data</li> - <li>Add mainboard_memory_init_params to copy the SPD and DRAM - configuration data from the pei_data structure into the UPDs - for MemoryInit - </li> - </ol> - </li> - <li>Edit devicetree.cb - <ol type="A"> - <li>Include the UPD parameters for MemoryInit except for: - <ul> - <li>Address of SPD data</li> - <li>DRAM configuration set above</li> - </ul> - </li> - </ol> - </li> - <li>A working FSP - <a target="_blank" href="../fsp1_1.html#MemoryInit">MemoryInit</a> - routine is required to complete debugging</li> - <li>Debug the result until port 0x80 outputs - <ol type="A"> - <li>0x34: - - Just after entering - <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/raminit.c;hb=HEAD#l67">raminit</a> - </li> - <li>0x36: - - Just before displaying the - <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/raminit.c;hb=HEAD#l106">UPD parameters</a> - for FSP MemoryInit - </li> - <li>0x92: <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l219">POST_FSP_MEMORY_INIT</a> - - Just before calling FSP - <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/raminit.c;hb=HEAD#l125">MemoryInit</a> - </li> - <li>0x37: - - Just after returning from FSP - <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/raminit.c;hb=HEAD#l127">MemoryInit</a> - </li> - </ol> - </li> - <li>Continue debugging with CONFIG_DISPLAY_HOBS enabled until TempRamExit is called</li> -</ol> - - - -<hr> -<h1><a name="DisablePciDevices">Disable PCI Devices</a></h1> -<p> - Ramstage's BS_DEV_ENUMERATE state displays the PCI vendor and device IDs for all - of the devices in the system. Edit the devicetree.cb file: -</p> -<ol> - <li>Edit the devicetree.cb file: - <ol type="A"> - <li>Add an entry for a PCI device.function and turn it off. The entry - should look similar to: -<pre><code>device pci 14.0 off end</code></pre> - </li> - <li>Turn on the devices for: - <ul> - <li>Memory Controller</li> - <li>Debug serial device</li> - </ul> - </li> - </ol> - </li> - <li>Debug until the BS_DEV_ENUMERATE state shows the proper state for all of the devices</li> -</ol> - - - -<hr> -<h1><a name="AcpiTables">ACPI Tables</a></h1> -<ol> - <li>Edit Kconfig - <ol type="A"> - <li>Add "select HAVE_ACPI_TABLES"</li> - </ol> - </li> - <li>Add the acpi_tables.c module: - <ol type="A"> - <li>Include soc/acpi.h</li> - <li>Add the acpi_create_fadt routine - <ol type="I"> - <li>fill in the ACPI header</li> - <li>Call the acpi_fill_in_fadt routine</li> - </ol> - </li> - </ol> - </li> - <li>Add the dsdt.asl module: - </li> -</ol> - - - -<hr> -<p>Modified: 20 February 2016</p> - </body> -</html> diff --git a/Documentation/Intel/Board/galileo.html b/Documentation/Intel/Board/galileo.html deleted file mode 100644 index cdc8fda..0000000 --- a/Documentation/Intel/Board/galileo.html +++ /dev/null @@ -1,114 +0,0 @@ -<!DOCTYPE html> -<html> - <head> - <title>Galileo</title> - </head> - <body> - -<h1>Intel® Galileo Development Board</h1> -<table> - <tr> - <td><a target="_blank" href="http://www.mouser.com/images/microsites/Intel_Galileo2_lrg.jpg"><img alt="Galileo Gen 2" src="http://www.mouser.com/images/microsites/Intel_Galileo2_lrg.jpg" width=500></a></td> - <td> - The Intel® Galileo Gen 2 mainboard code was developed along with the Intel® - <a target="_blank" href="../SoC/quark.html">Quark™</a> SoC: - <ul> - <li><a target="_blank" href="../development.html">Overall</a> development</li> - <li><a target="_blank" href="../SoC/soc.html">SoC</a> support</li> - <li><a target="_blank" href="../fsp1_1.html">FSP 1.1</a> integration</li> - <li><a target="_blank" href="board.html">Board</a> support</li> - <li><a target="_blank" href="Galileo_checklist.html">Implementation Checklist</a></li> - </ul> - </td> - </tr> -</table> - - - -<hr> -<h1>Galileo Board Documentation</h1> -<ul> - <li>Common Components - <ul> - <li>A/D: Texas Instruments <a target="_blank" href="http://www.ti.com/lit/ds/symlink/adc108s102.pdf">ADC108S102</a></li> - <li>Analog Switch: Texas Instruments <a target="_blank" href="http://www.ti.com/lit/ds/symlink/ts5a23159.pdf">TS5A23159</a></li> - <li>Ethernet (10/100 MB/S): Texas Instruments <a target="_blank" href="http://www.ti.com/lit/ds/symlink/dp83848-ep.pdf">DP83848</a></li> - <li>Load Switch: Texas Instruments <a target="_blank" href="http://www.ti.com/lit/ds/symlink/tps22920.pdf">TPS22920x</a></li> - <li>Memory (256 MiB): Micron <a target="_blank" href="https://www.micron.com/~/media/Documents/Products/Data%20Sheet/DRAM/DDR3/1Gb_1_35V_DDR3L.pdf">MT41K128M8</a></li> - <li>SoC: Intel® Quark™ <a target="_blank" href="../SoC/quark.html">X-1000</a></li> - <li>Serial EEPROM (1 KiB): ON Semiconductor® <a target="_blank" href="http://www.onsemi.com/pub_link/Collateral/CAT24C01-D.PDF">CAT24C08</a></li> - <li>SPI Flash (8 MiB): Winbond™ <a target="_blank" href="http://www.winbond-usa.com/resource-files/w25q64fv_revl1_100713.pdf">W25Q64FV</a></li> - <li>Step Down Converter: Texas Instruments <a target="_blank" href="http://www.ti.com/lit/ds/slvsag7c/slvsag7c.pdf">TPS62130</a></li> - <li>Step Down Converter: Texas Instruments <a target="_blank" href="http://www.ti.com/lit/ug/slvu570/slvu570.pdf">TPS652510</a></li> - <li>Termination Regulator: Texas Instruments <a target="_blank" href="http://www.ti.com/lit/ds/symlink/tps51200.pdf">TPS51200</a></li> - </ul> - </li> - <li>Make a bootable <a target="_blank" href="https://software.intel.com/en-us/get-started-galileo-linux-step1">micro SD card</a></li> -</ul> - -<h2>Galileo Gen 2 Board Documentation</h2> -<ul> - <li><a target="_blank" href="http://files.linuxgizmos.com/intel_galileo_gen2_blockdiagram.jpg">Block Diagram</a></li> - <li><a target="_blank" href="https://software.intel.com/en-us/iot/library/galileo-getting-started">Getting Started</a></li> - <li><a target="_blank" href="http://www.intel.com/content/www/us/en/embedded/products/galileo/galileo-overview.html">Overview</a></li> - <li><a target="_blank" href="http://files.linuxgizmos.com/intel_galileo_gen2_ports.jpg">Port Diagram</a></li> - <li><a target="_blank" href="http://download.intel.com/support/galileo/sb/intelgalileogen2prodbrief_330736_003.pdf">Product Brief</a></li> - <li><a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/documents/guides/galileo-g2-schematic.pdf">Schematic</a></li> - <li><a target="_blank" href="http://download.intel.com/support/galileo/sb/galileo_boarduserguide_330237_001.pdf">User Guide</a></li> - <li>Components - <ul> - <li>A/D: Texas Instruments <a target="_blank" href="http://www.ti.com/lit/ds/symlink/adc108s102.pdf">ADC108S102</a></li> - <li>I2C 16-channel, 12-bit PWM: NXP Semiconductors <a target="_blank" href="http://cache.nxp.com/documents/data_sheet/PCA9685.pdf">PCA9685</a></li> - <li>I2C I/O Ports: NXP Semiconductors <a target="_blank" href="http://www.nxp.com/documents/data_sheet/PCAL9535A.pdf">PCAL9535A</a></li> - <li>Octal Buffer/Driver: Texas Instruments <a target="_blank" href="http://www.ti.com/lit/ds/symlink/sn74lv541at.pdf">SN74LV541AT</a></li> - <li>Quadruple Bus Buffer: Texas Instruments <a target="_blank" href="http://www.ti.com/lit/ds/symlink/sn74lv125a.pdf">SN74LV125A</a></li> - <li>Quadruple Bus Buffer with 3-State Outputs: Texas Instruments <a target="_blank" href="http://www.ti.com/lit/ds/symlink/sn74lvc126a.pdf">SN74LVC126A</a></li> - <li>Serial EEPROM (1 KiB): ON Semiconductor® <a target="_blank" href="http://www.onsemi.com/pub_link/Collateral/CAT24C01-D.PDF">CAT24C08</a></li> - <li>Single 2-input multiplexer: NXP Semiconductors <a target="_blank" href="http://www.nxp.com/documents/data_sheet/74LVC1G157.pdf">74LVC1G157</a></li> - <li>Step Down Converter: Texas Instruments <a target="_blank" href="http://www.ti.com/lit/ds/slvsag7c/slvsag7c.pdf">TPS62130</a></li> - </ul> - </li> -</ul> - -<h2>Galileo Gen 1 Board Documentation</h2> -<ul> - <li><a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/documents/datasheets/galileo-g1-datasheet.pdf">Datasheet</a></li> - <li><a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/documents/guides/galileo-g1-schematic.pdf">Schematic</a></li> - <li>Components - <ul> - <li>A/D: Analog Devices <a target="_blank" href="http://www.analog.com/media/en/technical-documentation/data-sheets/AD7298-1.pdf">AD7298</a></li> - <li>Analog Switch, 2 channel: Texas Instruments <a target="_blank" href="http://www.ti.com.cn/cn/lit/ds/symlink/ts5a23159.pdf">TS5A23159</a></li> - <li>EEPROM & GPIO: Cypress <a target="_blank" href="http://www.cypress.com/file/37971/download">CY8C9540A</a></li> - <li>Power Distribution Switch: Texas Instruments <a target="_blank" href="http://www.ti.com/lit/ds/symlink/tps2044b.pdf">TPS2051BDBVR</a></li> - <li>RS232 Converter: Texas Instruments <a target="_blank" href="http://www.ti.com/lit/ds/symlink/max3232.pdf">MAX3232</a></li> - <li>Voltage-Level Translator: Texas Instruments<a target="_blank" href="http://www.ti.com/lit/ds/symlink/txs0108e.pdf">TXS0108E</a></li> - </ul> - </li> -</ul> - - - -<hr> -<h1>Debug Tools</h1> -<ul> - <li>Flash Programmer: - <ul> - <li>Dediprog <a target="_blank" href="http://www.dediprog.com/pd/spi-flash-solution/SF100">SF100</a> ISP IC Programmer</li> - </ul> - </li> - <li>JTAG Connector: <a target="_blank" href="https://www.google.com/webhp?sourceid=chrome-instant&ion=1&espv=2&ie=UTF-8#q=Olimex+ARM-JTAG-20-10">Olimex ARM-JTAG-20-10</a></li> - <li>JTAG Debugger: - <ul> - <li>Olimex LTD <a target="_blank" href="https://www.google.com/webhp?sourceid=chrome-instant&ion=1&espv=2&ie=UTF-8#q=Olimex+ARM-USB-OCD-H">ARM-USB-OCD-H</a></li> - <li>Tincan Tools <a target="_blank" href="https://www.tincantools.com/wiki/Flyswatter2">Flyswatter2</a></li> - </ul> - </li> - <li><a target="_blank" href="http://download.intel.com/support/processors/quark/sb/sourcedebugusingopenocd_quark_appnote_330015_003.pdf">Hardware Setup and Software Installation</a></li> - <li>USB Serial cable: FTDI <a target="_blank" href="https://www.google.com/webhp?sourceid=chrome-instant&ion=1&espv=2&ie=UTF-8#q=FTDI+TTL-232R-3V3">TTL-232R-3V3</a></li> -</ul> - - -<hr> -<p>Modified: 29 February 2016</p> - </body> -</html> diff --git a/Documentation/Intel/SoC/quark.html b/Documentation/Intel/SoC/quark.html deleted file mode 100644 index 61abebd..0000000 --- a/Documentation/Intel/SoC/quark.html +++ /dev/null @@ -1,179 +0,0 @@ -<!DOCTYPE html> -<html> - <head> - <title>Quark™ SoC</title> - </head> - <body> - -<h1>Intel® Quark™ SoC</h1> -<table> - <tr> - <td><a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/images/embedded/16x9/edc-quark-block-diagram-16x9.png"><img alt="Quark Block Diagram" src="http://www.intel.com/content/dam/www/public/us/en/images/embedded/16x9/edc-quark-block-diagram-16x9.png" width=500></a></td> - <td> - The Quark™ SoC code was developed using the - <a target="_blank" href="../Board/galileo.html">Galileo Gen 2</a> - board: - <ul> - <li><a target="_blank" href="../development.html">Overall</a> development</li> - <li><a target="_blank" href="soc.html">SoC</a> support</li> - <li><a target="_blank" href="../fsp1_1.html">FSP 1.1</a> integration</li> - <li><a target="_blank" href="../Board/board.html">Board</a> support</li> - <li><a target="_blank" href="#QuarkFsp">Quark™ FSP</a></li> - <li><a target="_blank" href="#CorebootPayloadPkg">CorebootPayloadPkg</a></li> - </ul> - </td> - </tr> -</table> - - - -<hr> -<h1>Quark™ Documentation</h1> -<ul> - <li><a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/images/embedded/16x9/edc-quark-block-diagram-16x9.png">Block Diagram</a></li> - <li><a target="_blank" href="http://www.intel.com/content/www/us/en/embedded/products/quark/specifications.html">Specifications</a>: - <ul> - <li><a target="_blank" href="http://ark.intel.com/products/79084/Intel-Quark-SoC-X1000-16K-Cache-400-MHz">X1000</a> - - <a target="_blank" href="http://www.intel.com/content/www/us/en/search.html?keyword=X1000">Documentation</a>: - <ul> - <li><a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/documents/datasheets/quark-x1000-datasheet.pdf">Datasheet</a></li> - <li><a target="_blank" href="http://www.intel.com/content/dam/support/us/en/documents/processors/quark/sb/intelquarkcore_devman_001.pdf">Developer's Manual</a></li> - <li><a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/documents/product-briefs/intel-quark-product-brief-v3.pdf">Product Brief</a></li> - </ul> - </li> - </ul> - </li> - <li><a target="_blank" href="../index.html#Documentation">More documentation</a></li> -</ul> - - - -<hr> -<h1><a name="CorebootPayloadPkg">Quark™ EDK2 CorebootPayloadPkg</a></h1> -<p> -Build Instructions: -</p> -<ol> - <li>Set up <a href="#BuildEnvironment">build environment</a></li> - <li>Linux (assumes GCC48): -<pre><code>build -p CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc -a IA32 \ - -t GCC48 -b DEBUG -DDEBUG_PROPERTY_MASK=0x27 \ - -DDEBUG_PRINT_ERROR_LEVEL=0x80000042 -DSHELL_TYPE=BUILD_SHELL \ - -DMAX_LOGICAL_PROCESSORS=1 -ls Build/CorebootPayloadPkgIA32/DEBUG_GCC48/FV/UEFIPAYLOAD.fd -</code></pre> - </li> - <li>Windows (assumes Visual Studio 2015): -<pre><code>build -p CorebootPayloadPkg\CorebootPayloadPkgIa32.dsc -a IA32 -t VS2015x86 -b DEBUG -DDEBUG_PROPERTY_MASK=0x27 -DDEBUG_PRINT_ERROR_LEVEL=0x80000042 -DSHELL_TYPE=BUILD_SHELL -DMAX_LOGICAL_PROCESSORS=1 -dir Build\CorebootPayloadPkgIA32\DEBUG_VS2015x86\FV\UEFIPAYLOAD.fd -</code></pre> - </li> - <li>In the .config for coreboot, set the following Kconfig values: - <ul> - <li>CONFIG_PAYLOAD_ELF=y</li> - <li>CONFIG_PAYLOAD_FILE="path to UEFIPAYLOAD.fd"</li> - </ul> - </li> - <li>Build coreboot</li> - <li>Copy the image build/coreboot.rom into flash</li> -</ol> - - - -<hr> -<h1><a name="BuildEnvironment">Quark™ EDK2 Build Environment</a></h1> -<p> - Use the following steps to setup a build environment: -</p> -<ol> - <li>Get the EDK2 sources: - <ol type="A"> - <li>EDK2: git clone <a target="_blank" href="https://github.com/tianocore/edk2.git">https://github.com/tianocore/edk2.git</a></li> - <li>EDK2-non-osi: git clone <a target="_blank" href="https://github.com/tianocore/edk2-non-osi.git">https://github.com/tianocore/edk2-non-osi.git</a></li> - <li>Win32 BaseTools: git clone <a target="_blank" href="https://github.com/tianocore/edk2-BaseTools-win32.git">https://github.com/tianocore/edk2-BaseTools-win32.git</a></li> - </ol> - </li> - <li>Set up a build window: - <ul> - <li>Linux: -<pre><code>export WORKSPACE=$PWD -export PACKAGES_PATH="$PWD/edk2:$PWD/edk2-non-osi" -cd edk2 -export WORKSPACE=$PWD -. edksetup.sh -</code></pre> - </li> - <li>Windows: -<pre><code>set WORKSPACE=%CD% -set PACKAGES_PATH=%WORKSPACE%\edk2;%WORKSPACE%\edk2-non-osi -set EDK_TOOLS_BIN=%WORKSPACE%\edk2-BaseTools-win32 -cd edk2 -edksetup.bat -</code></pre> - </li> - </ul> - </li> -</ol> - - - -<hr> -<h1><a name="QuarkFsp">Quark™ FSP</a></h1> -<p> -Getting the Quark FSP source: -</p> -<ol> - <li>Set up an EDK-II <a href="#BuildEnvironment">Build Environment</a></li> - <li>cd edk2</li> - <li>mkdir QuarkFspPkg</li> - <li>cd QuarkFspPkg</li> - <li>Use git to clone <a target="_blank" href="https://review.gerrithub.io/#/admin/projects/LeeLeahy/quarkfsp">QuarkFspPkg</a> into the QuarkFpsPkg directory (.)</li> -</ol> - -<p> -Building QuarkFspPkg: -</p> -<ul> - <li>Linux: QuarkFspPkg/BuildFsp.sh -d32</li> - <li>Windows: QuarkFspPkg/BuildFsp.bat -d32</li> -</ul> - - - -<hr> -<h1>Quark™ EDK2 BIOS</h1> -<p> -Build Instructions: -</p> -<ol> - <li>Set up <a href="#BuildEnvironment">build environment</a></li> - <li>Build the image: - <ul> - <li>Linux: -<pre><code>build -p QuarkPlatformPkg/Quark.dsc -a IA32 -t GCC48 -b DEBUG -DDEBUG_PROPERTY_MASK=0x27 -DDEBUG_PRINT_ERROR_LEVEL=0x80000042 -ls Build/Quark/DEBUG_GCC48/FV/Quark.fd -</code></pre> - </li> - <li>Windows: -<pre><code>build -p QuarkPlatformPkg/Quark.dsc -a IA32 -t VS2012x86 -b DEBUG -DDEBUG_PROPERTY_MASK=0x27 -DDEBUG_PRINT_ERROR_LEVEL=0x80000042 -dir Build\Quark\DEBUG_VS2012x86\FV\Quark.fd -</code></pre> - </li> - </ul> - </li> -</ol> - -<p> -Documentation: -</p> -<ul> - <li><a target="_blank" href="https://github.com/tianocore/edk2/tree/master/QuarkPlatformPkg">EDK II firmware for Intel® Quark™ SoC X1000 based platforms</a></li> - <li>Intel® Quark™ SoC X1000 <a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/documents/guides/quark-x1000-uefi-firmware-writers-guide.pdf">UEFI Firmware Writer's Guide</a></li> -</ul> - - - -<hr> -<p>Modified: 17 May 2016</p> - </body> -</html> diff --git a/Documentation/Intel/SoC/soc.html b/Documentation/Intel/SoC/soc.html deleted file mode 100644 index 8f1d75c..0000000 --- a/Documentation/Intel/SoC/soc.html +++ /dev/null @@ -1,734 +0,0 @@ -<!DOCTYPE html> -<html> - <head> - <title>SoC</title> - </head> - <body> - -<h1>x86 System on a Chip (SoC) Development</h1> -<p> - SoC development is best done in parallel with development for a specific - board. The combined steps are listed - <a target="_blank" href="../development.html">here</a>. - The development steps for the SoC are listed below: -</p> -<ol> - <li><a target="_blank" href="../fsp1_1.html#RequiredFiles">FSP 1.1</a> required files</li> - <li>SoC <a href="#RequiredFiles">Required Files</a></li> - <li><a href="#Descriptor">Start Booting</a></li> - <li><a href="#EarlyDebug">Early Debug</a></li> - <li><a href="#Bootblock">Bootblock</a></li> - <li><a href="#TempRamInit">TempRamInit</a></li> - <li><a href="#Romstage">Romstage</a> - <ol type="A"> - <li>Enable <a href="#SerialOutput">Serial Output"</a></li> - <li>Get the <a href="#PreviousSleepState">Previous Sleep State</a></li> - <li>Add the <a href="#MemoryInit">MemoryInit</a> Support</li> - <li>Disable the <a href="#DisableShadowRom">Shadow ROM</a></li> - </ol> - </li> - <li><a href="#Ramstage">Ramstage</a> - <ol type="A"> - <li><a href="#DeviceTree">Start Device Tree Processing</a></li> - <li>Set up the <a href="#MemoryMap">Memory Map"</a></li> - </ol> - </li> - <li><a href="#AcpiTables">ACPI Tables</a></li> - <li><a href="#LegacyHardware">Legacy Hardware</a></li> -</ol> - - -<hr> -<h1><a name="RequiredFiles">Required Files</a></h1> -<p> - Create the directory as src/soc/<Vendor>/<Chip Family>. -</p> - -<p> - The following files are required to build a new SoC: -</p> -<ul> - <li>Include files - <ul> - <li>include/soc/pei_data.h</li> - <li>include/soc/pm.h</li> - </ul> - </li> - <li>Kconfig - Defines the Kconfig value for the SoC and selects the tool - chains for the various stages: - <ul> - <li>select ARCH_BOOTBLOCK_<Tool Chain></li> - <li>select ARCH_RAMSTAGE_<Tool Chain></li> - <li>select ARCH_ROMSTAGE_<Tool Chain></li> - <li>select ARCH_VERSTAGE_<Tool Chain></li> - </ul> - </li> - <li>Makefile.inc - Specify the include paths</li> - <li>memmap.c - Top of usable RAM</li> -</ul> - - -<hr> -<h1><a name="Descriptor">Start Booting</a></h1> -<p> - Some SoC parts require additional firmware components in the flash. - This section describes how to add those pieces. -</p> - -<h2>Intel Firmware Descriptor</h2> -<p> - The Intel Firmware Descriptor (IFD) is located at the base of the flash part. - The following command overwrites the base of the flash image with the Intel - Firmware Descriptor: -</p> -<pre><code>dd if=descriptor.bin of=build/coreboot.rom conv=notrunc >/dev/null 2>&1</code></pre> - - -<h2><a name="MEB">Management Engine Binary</a></h2> -<p> - Some SoC parts contain and require that the Management Engine (ME) be running - before it is possible to bring the x86 processor out of reset. A binary file - containing the management engine code must be added to the firmware using the - ifdtool. The following commands add this binary blob: -</p> -<pre><code>util/ifdtool/ifdtool -i ME:me.bin build/coreboot.rom -mv build/coreboot.rom.new build/coreboot.rom -</code></pre> - - -<h2><a name="EarlyDebug">Early Debug</a></h2> -<p> - Early debugging between the reset vector and the time the serial port is enabled - is most easily done by writing values to port 0x80. -</p> - - -<h2>Success</h2> -<p> - When the reset vector is successfully invoked, port 0x80 will output the following value: -</p> -<ul> - <li>0x01: <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l45">POST_RESET_VECTOR_CORRECT</a> - - Bootblock successfully executed the - <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/16bit/reset16.inc;hb=HEAD#l4">reset vector</a> - and entered the 16-bit code at - <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/16bit/entry16.inc;hb=HEAD#l35">_start</a> - </li> -</ul> - - -<hr> -<h1><a name="Bootblock">Bootblock</a></h1> -<p> - Implement the bootblock using the following steps: -</p> -<ol> - <li>Create the directory as src/soc/<Vendor>/<Chip Family>/bootblock</li> - <li>Add the timestamp.inc file which initializes the floating point registers and saves - the initial timestamp. - </li> - <li>Add the bootblock.c file which: - <ol type="A"> - <li>Enables memory-mapped PCI config access</li> - <li>Updates the microcode by calling intel_update_microcode_from_cbfs</li> - <li>Enable ROM caching</li> - </ol> - </li> - <li>Edit the src/soc/<Vendor>/<Chip Family>/Kconfig file - <ol type="A"> - <li>Add the BOOTBLOCK_CPU_INIT value to point to the bootblock.c file</li> - <li>Add the CHIPSET_BOOTBLOCK_INCLUDE value to point to the timestamp.inc file</li> - </ol> - </li> - <li>Edit the src/soc/<Vendor>/<Chip Family>/Makefile.inc file - <ol type="A"> - <li>Add the bootblock subdirectory</li> - </ol> - </li> - <li>Edit the src/soc/<Vendor>/<Chip Family>/memmap.c file - <ol type="A"> - <li>Add the fsp/memmap.h include file</li> - <li>Add the mmap_region_granularity routine</li> - </ol> - </li> - <li>Add the necessary .h files to define the necessary values and structures</li> - <li>When successful port 0x80 will output the following values: - <ol type="A"> - <li>0x01: <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l45">POST_RESET_VECTOR_CORRECT</a> - - Bootblock successfully executed the - <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/16bit/reset16.inc;hb=HEAD#l4">reset vector</a> - and entered the 16-bit code at - <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/16bit/entry16.inc;hb=HEAD#l35">_start</a> - </li> - <li>0x10: <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l53">POST_ENTER_PROTECTED_MODE</a> - - Bootblock executing in - <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/32bit/entry32.inc;hb=HEAD#l55">32-bit mode</a> - </li> - <li>0x10 - Verstage/romstage reached 32-bit mode</li> - </ol> - </li> -</ol> - -<p> - <b>Build Note:</b> The following files are included into the default bootblock image: -</p> -<ul> - <li><a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/bootblock_romcc.S;hb=HEAD">src/arch/x86/bootblock_romcc.S</a> - added by <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/Makefile.inc;hb=HEAD#l133">src/arch/x86/Makefile.inc</a> - and includes the following files: - <ul> - <li><a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/prologue.inc">src/arch/x86/prologue.inc</a></li> - <li><a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/16bit/reset16.inc">src/cpu/x86/16bit/reset16.inc</a></li> - <li><a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/16bit/entry16.inc">src/cpu/x86/16bit/entry16.inc</a></li> - <li><a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/32bit/entry32.inc">src/cpu/x86/32bit/entry32.inc</a></li> - <li>The code in - <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/bootblock_romcc.S">src/arch/x86/bootblock_romcc.S</a> - includes src/soc/<Vendor>/<Chip Family>/bootblock/timestamp.inc using the - CONFIG_CHIPSET_BOOTBLOCK_INCLUDE value set above - </li> - <li><a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/sse_enable.inc">src/cpu/x86/sse_enable.inc</a></li> - <li>The code in - <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/Makefile.inc;hb=HEAD#l156">src/arch/x86/Makefile.inc</a> - invokes the ROMCC tool to convert the following "C" code into assembler as bootblock.inc: - <ul> - <li><a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/include/arch/bootblock_romcc.h">src/arch/x86/include/arch/bootblock_romcc.h</a></li> - <li><a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/lapic/boot_cpu.c">src/cpu/x86/lapic/boot_cpu.c</a></li> - <li>The CONFIG_BOOTBLOCK_CPU_INIT value set above typically points to the code in - src/soc/<Vendor>/<Chip Family>/bootblock/bootblock.c - </li> - </ul> - </li> - </ul> - </li> - <li><a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/id.S">src/arch/x86/id.S</a> - added by <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/Makefile.inc;hb=HEAD#l110">src/arch/x86/Makefile.inc</a> - </li> - <li><a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/intel/fit/fit.S">src/cpu/intel/fit/fit.S</a> - added by <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/intel/fit/Makefile.inc;hb=HEAD">src/cpu/intel/fit/Makefile.inc</a> - </li> - <li><a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/walkcbfs.S">src/arch/x86/walkcbfs.S</a> - added by <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/Makefile.inc;hb=HEAD#l137">src/arch/x86/Makefile.inc</a> - </li> -</ul> - - -<hr> -<h1><a name="TempRamInit">TempRamInit</a></h1> -<p> - Enable the call to TempRamInit in two stages: -</p> -<ol> - <li>Finding the FSP binary in the read-only CBFS region</li> - <li>Call TempRamInit</li> -</ol> - - -<h2>Find FSP Binary</h2> -<p> -Use the following steps to locate the FSP binary: -</p> -<ol> - <li>Edit the src/soc/<Vendor>/<Chip Family>/Kconfig file - <ol type="A"> - <li>Add "select USE_GENERIC_FSP_CAR_INC" to enable the use of - <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/cache_as_ram.inc">src/drivers/intel/fsp1_1/cache_as_ram.inc</a> - </li> - <li>Add "select SOC_INTEL_COMMON" to enable the use of the files from src/soc/intel/common - specifically building - <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/soc/intel/common/util.c">util.c</a> - </li> - </ol> - </li> - <li>Debug the result until port 0x80 outputs - <ol type="A"> - <li>0x90: <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l205">POST_FSP_TEMP_RAM_INIT</a> - - Just before calling - <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/cache_as_ram.inc;hb=HEAD#l73">TempRamInit</a> - </li> - <li>Alternating 0xba and 0x01 - The FSP image was not found</li> - </ol> - </li> - <li>Add the <a target="_blank" href="../fsp1_1.html#FspBinary">FSP binary file</a> to the flash image</li> - <li>Set the following Kconfig values: - <ul> - <li>CONFIG_FSP_LOC to the FSP base address specified in the previous step</li> - <li>CONFIG_FSP_IMAGE_ID_STRING</li> - </ul> - </li> - <li>Debug the result until port 0x80 outputs - <ol type="A"> - <li>0x90: <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l205">POST_FSP_TEMP_RAM_INIT</a> - - Just before calling - <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/cache_as_ram.inc;hb=HEAD#l73">TempRamInit</a> - </li> - <li>Alternating 0xbb and 0x02 - TempRamInit executed, no CPU microcode update found</li> - </ol> - </li> -</ol> - - -<h2>Calling TempRamInit</h2> -<p> -Use the following steps to debug the call to TempRamInit: -</p> -<ol> - <li>Add the CPU microcode update file - <ol type="A"> - <li>Add the microcode file with the following command -<pre><code>util/cbfstool/cbfstool build/coreboot.rom add -t microcode -n cpu_microcode_blob.bin -b <base address> -f cpu_microcode_blob.bin</code></pre> - </li> - <li>Set the Kconfig values - <ul> - <li>CONFIG_CPU_MICROCODE_CBFS_LOC set to the value from the previous step</li> - <li>CONFIG_CPU_MICROCODE_CBFS_LEN</li> - </ul> - </li> - </ol> - </li> - <li>Debug the result until port 0x80 outputs - <ol type="A"> - <li>0x90: <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l205">POST_FSP_TEMP_RAM_INIT</a> - - Just before calling - <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/cache_as_ram.inc;hb=HEAD#l73">TempRamInit</a> - </li> - <li>0x2A - Just before calling - <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/cache_as_ram.inc;hb=HEAD#l151">cache_as_ram_main</a> - which is the start of the verstage code which may be part of romstage - </li> - </ol> - </li> -</ol> - - -<hr> -<h1><a name="Romstage">Romstage</a></h1> - -<h2><a name="SerialOutput">Serial Output</a></h2> -<p> - The following steps add the serial output support for romstage: -</p> -<ol> - <li>Create the romstage subdirectory</li> - <li>Add romstage/romstage.c - <ol type="A"> - <li>Program the necessary base addresses</li> - <li>Disable the TCO</li> - </ol> - </li> - <li>Add romstage/Makefile.inc - <ol type="A"> - <li>Add romstage.c to romstage</li> - </ol> - </li> - <li>Add gpio configuration support if necessary</li> - <li>Add the necessary .h files to support the build</li> - <li>Update Makefile.inc - <ol type="A"> - <li>Add the romstage subdirectory</li> - <li>Add the gpio configuration support file to romstage</li> - </ol> - </li> - <li>Set the necessary Kconfig values to enable serial output: - <ul> - <li>CONFIG_DRIVERS_UART_<driver>=y</li> - <li>CONFIG_CONSOLE_SERIAL=y</li> - <li>CONFIG_UART_FOR_CONSOLE=<port></li> - <li>CONFIG_CONSOLE_SERIAL_115200=y</li> - </ul> - </li> -</ol> - - -<h2><a name="PreviousSleepState">Determine Previous Sleep State</a></h2> -<p> - The following steps implement the code to get the previous sleep state: -</p> -<ol> - <li>Implement the fill_power_state routine which determines the previous sleep state</li> - <li>Debug the result until port 0x80 outputs - <ol type="A"> - <li>0x32: - - Just after entering - <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/romstage.c;hb=HEAD#l99">romstage_common</a> - </li> - <li>0x33 - Just after calling - <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/romstage.c;hb=HEAD#l113">soc_pre_ram_init</a> - </li> - <li>0x34: - - Just after entering - <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/raminit.c;hb=HEAD#l67">raminit</a> - </li> - </ol> -</ol> - - -<h2><a name="MemoryInit">MemoryInit Support</a></h2> -<p> - The following steps implement the code to support the FSP MemoryInit call: -</p> -<ol> - <li>Add the chip.h header file to define the UPD values which get passed - to MemoryInit. Skip the values containing SPD addresses and DRAM - configuration data which is determined by the board. - <p> - <b>Build Note</b>: The src/mainboard/<Vendor>/<Board>/devicetree.cb - file specifies the default values for these parameters. The build - process creates the static.c module which contains the config data - structure containing these values. - </p> - </li> - <li>Edit romstage/romstage.c - <ol type="A"> - <li>Implement the romstage/romstage.c/soc_memory_init_params routine to - copy the values from the config structure into the UPD structure - </li> - <li>Implement the soc_display_memory_init_params routine to display - the updated UPD parameters by calling fsp_display_upd_value - </li> - </ol> - </li> -</ol> - - -<h2><a name="DisableShadowRom">Disable Shadow ROM</a></h2> -<p> - A shadow of the SPI flash part is mapped from 0x000e0000 to 0x000fffff. - This shadow needs to be disabled to allow RAM to properly respond to - this address range. -</p> -<ol> - <li>Edit romstage/romstage.c and add the soc_after_ram_init routine</li> -</ol> - - -<hr> -<h1><a name="Ramstage">Ramstage</a></h1> - -<h2><a name="DeviceTree">Start Device Tree Processing</a></h2> -<p> - The src/mainboard/<Vendor>/<Board>/devicetree.cb file drives the - execution during ramstage. This file is processed by the util/sconfig utility - to generate build/mainboard/<Vendor>/<Board>/static.c. The various - state routines in - src/lib/<a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/lib/hardwaremain.c;hb=HEAD#l128">hardwaremain.c</a> - call dev_* routines which use the tables in static.c to locate operation tables - associated with the various chips and devices. After location the operation - tables, the state routines call one or more functions depending upon the - state of the state machine. -</p> - -<h3><a name="ChipOperations">Chip Operations</a></h3> -<p> - Kick-starting the ramstage state machine requires creating the operation table - for the chip listed in devicetree.cb: -</p> -<ol> - <li>Edit src/soc/<SoC Vendor>/<SoC Family>/chip.c: - <ol type="A"> - <li> - This chip's operation table has the name - soc_<SoC Vendor>_<SoC Family>_ops which is derived from the - chip path specified in the devicetree.cb file. - </li> - <li>Use the CHIP_NAME macro to specify the name for the chip</li> - <li>For FSP 1.1, specify a .init routine which calls intel_silicon_init</li> - </ol> - </li> - <li>Edit src/soc/<SoC Vendor>/<SoC Family>/Makefile.inc and add chip.c to ramstage</li> -</ol> - -<h3>Domain Operations</h3> -<p> - coreboot uses the domain operation table to initiate operations on all of the - devices in the domain. By default coreboot enables all PCI devices which it - finds. Listing a device in devicetree.cb gives the board vendor control over - the device state. Non-PCI devices may also be listed under PCI device such as - the LPC bus or SMbus devices. -</p> -<ol> - <li>Edit src/soc/<SoC Vendor>/<SoC Family>/chip.c: - <ol type="A"> - <li> - The domain operation table is typically placed in - src/soc/<SoC Vendor>/<SoC Family>/chip.c. - The table typically looks like the following: -<pre><code>static struct device_operations pci_domain_ops = { - .read_resources = pci_domain_read_resources, - .set_resources = pci_domain_set_resources, - .scan_bus = pci_domain_scan_bus, - .ops_pci_bus = pci_bus_default_ops, -}; -</code></pre> - </li> - <li> - Create a .enable_dev entry in the chip operations table which points to a - routine which sets the domain table for the device with the DEVICE_PATH_DOMAIN. -<pre><code> if (dev->path.type == DEVICE_PATH_DOMAIN) { - dev->ops = &pci_domain_ops; - } -</code></pre> - </li> - <li> - During the BS_DEV_ENUMERATE state, ramstage now display the device IDs - for the PCI devices on the bus. - </li> - </ol> - </li> - <li>Set CONFIG_DEBUG_BOOT_STATE=y in the .config file</li> - <li> - Debug the result until the PCI vendor and device IDs are displayed - during the BS_DEV_ENUMERATE state. - </li> -</ol> - - -<h2><a name="DeviceDrivers">PCI Device Drivers</a></h2> -<p> - PCI device drivers consist of a ".c" file which contains a "pci_driver" data - structure at the end of the file with the attribute tag "__pci_driver". This - attribute tag places an entry into a link time table listing the various - coreboot device drivers. -</p> -<p> - Specify the following fields in the table: -</p> -<ol> - <li>.vendor - PCI vendor ID value of the device</li> - <li>.device - PCI device ID value of the device or<br> - .devices - Address of a zero terminated array of PCI device IDs - </li> - <li>.ops - Operations table for the device. This is the address - of a "static struct device_operations" data structure specifying - the routines to execute during the different states and sub-states - of ramstage's processing. - </li> - <li>Turn on the device in mainboard/<Vendor>/<Board>/devicetree.cb</li> - <li> - Debug until the device is on and properly configured in coreboot and - usable by the payload - </li> -</ol> - -<h3><a name="SubsystemIds">Subsystem IDs</a></h3> -<p> - PCI subsystem IDs are assigned during the BS_DEV_ENABLE state. The device - driver may use the common mechanism to assign subsystem IDs by adding - the ".ops_pci" to the pci_driver data structure. This field points to - a "struct pci_operations" that specifies a routine to set the subsystem - IDs for the device. The routine might look something like this: -</p> -<pre><code>static void pci_set_subsystem(device_t dev, unsigned vendor, unsigned device) -{ - if (!vendor || !device) { - vendor = pci_read_config32(dev, PCI_VENDOR_ID); - device = vendor >> 16; - } - printk(BIOS_SPEW, - "PCI: %02x:%02x:%d subsystem vendor: 0x%04x, device: 0x%04x\n", - 0, PCI_SLOT(dev->path.pci.devfn), PCI_FUNC(dev->path.pci.devfn), - vendor & 0xffff, device); - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); -} -</code></pre> - - - -<h2>Set up the <a name="MemoryMap">Memory Map</a></h2> -<p> - The memory map is built by the various PCI device drivers during the - BS_DEV_RESOURCES state of ramstage. The northcluster driver will typically - specify the DRAM resources while the other drivers will typically specify - the IO resources. These resources are hung off the device_t data structure by - src/device/device_util.c/<a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/device/device_util.c;hb=HEAD#l448">new_resource</a>. -</p> -<p> - During the BS_WRITE_TABLES state, coreboot collects these resources and - places them into a data structure identified by LB_MEM_TABLE. -</p> -<p> - Edit the device driver file: -</p> -<ol> - <li> - Implement a read_resources routine which calls macros defined in - src/include/device/<a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/device/device.h;hb=HEAD#l237">device.h</a> - like: - <ul> - <li>ram_resource</li> - <li>reserved_ram_resource</li> - <li>bad_ram_resource</li> - <li>uma_resource</li> - <li>mmio_resource</li> - </ul> - </li> -</ol> - -<p> - Testing: Verify that the resources are properly displayed by coreboot during the BS_WRITE_TABLES state. -</p> - - - -<hr> -<h1><a name="AcpiTables">ACPI Tables</a></h1> -<p> - One of the payloads that needs ACPI tables is the EDK2 <a target="_blank" href="quark.html#CorebootPayloadPkg">CorebootPayloadPkg</a>. -</p> - -<h2>FADT</h2> -<p> - The EDK2 module - CorebootModulePkg/Library/CbParseLib/<a target="_blank" href="https://github.com/tianocore/edk2/blob/master/CorebootModulePkg/Library/CbParseLib/CbParseLib.c#l450">CbParseLib.c</a> - requires that the FADT contains the values in the table below. - These values are placed into a HOB identified by - <a target="_blank" href="https://github.com/tianocore/edk2/blob/master/CorebootModulePkg/CorebootModulePkg.dec#l36">gUefiAcpiBoardInfoGuid</a> - by routine - CorebootModulePkg/CbSupportPei/CbSupportPei/<a target="_blank" href="https://github.com/tianocore/edk2/blob/master/CorebootModulePkg/CbSupportPei/CbSupportPei.c#l364">CbPeiEntryPoint</a>. -</p> -<table border="1"> - <tr bgcolor="#c0ffc0"> - <td>Coreboot Field</td> - <td>EDK2 Field</td> - <td>gUefiAcpiBoardInfoGuid</td> - <td>Use</li> - <td> - <a target="_blank" href="http://www.uefi.org/sites/default/files/resources/ACPI_6.0.pdf">ACPI Spec.</a> - Section - </td> - </tr> - <tr> - <td>gpe0_blk<br>gpe0_blk_len</td> - <td>Gpe0Blk<br>Gpe0BlkLen</td> - <td> - <a target="_blank" href="https://github.com/tianocore/edk2/blob/master/CorebootModulePkg/Library/CbParseLib/CbParseLib.c#l477">PmGpeEnBase</a> - </td> - <td><a target="_blank" href="https://github.com/tianocore/edk2/blob/master/CorebootPayloadPkg/Library/ResetSystemLib/ResetSystemLib.c#l129">Shutdown</a></td> - <td>4.8.4.1</td> - </tr> - <tr> - <td>pm1a_cnt_blk</td> - <td>Pm1aCntBlk</td> - <td>PmCtrlRegBase</td> - <td> - <a target="_blank" href="https://github.com/tianocore/edk2/blob/master/CorebootPayloadPkg/Library/ResetSystemLib/ResetSystemLib.c#l139">Shutdown</a><br> - <a target="_blank" href="https://github.com/tianocore/edk2/blob/master/CorebootPayloadPkg/Library/ResetSystemLib/ResetSystemLib.c#l40">Suspend</a> - </td> - <td>4.8.3.2.1</td> - </tr> - <tr> - <td>pm1a_evt_blk</td> - <td>Pm1aEvtBlk</td> - <td>PmEvtBase</td> - <td><a target="_blank" href="https://github.com/tianocore/edk2/blob/master/CorebootPayloadPkg/Library/ResetSystemLib/ResetSystemLib.c#l134">Shutdown</a></td> - <td>4.8.3.1.1</td> - </tr> - <tr> - <td>pm_tmr_blk</td> - <td>PmTmrBlk</td> - <td>PmTimerRegBase</td> - <td> - <a target="_blank" href="https://github.com/tianocore/edk2/blob/master/CorebootPayloadPkg/Library/AcpiTimerLib/AcpiTimerLib.c#l55">Timer</a> - </td> - <td>4.8.3.3</td> - </tr> - <tr> - <td>reset_reg.</td> - <td>ResetReg.Address</td> - <td>ResetRegAddress</td> - <td> - <a target="_blank" href="https://github.com/tianocore/edk2/blob/master/CorebootPayloadPkg/Library/ResetSystemLib/ResetSystemLib.c#l71">Cold</a> - and - <a target="_blank" href="https://github.com/tianocore/edk2/blob/master/CorebootPayloadPkg/Library/ResetSystemLib/ResetSystemLib.c#l98">Warm</a> - resets - </td> - <td>4.3.3.6</td> - </tr> - <tr> - <td>reset_value</td> - <td>ResetValue</td> - <td>ResetValue</td> - <td> - <a target="_blank" href="https://github.com/tianocore/edk2/blob/master/CorebootPayloadPkg/Library/ResetSystemLib/ResetSystemLib.c#l71">Cold</a> - and - <a target="_blank" href="https://github.com/tianocore/edk2/blob/master/CorebootPayloadPkg/Library/ResetSystemLib/ResetSystemLib.c#l98">Warm</a> - resets - </td> - <td>4.8.3.6</td> - </tr> -</table> -<p> - The EDK2 data structure is defined in - MdeModulePkg/Include/IndustryStandard/<a target="_blank" href="https://github.com/tianocore/edk2/blob/master/MdePkg/Include/IndustryStandard/Acpi61.h#l111">Acpi61.h</a> - The coreboot data structure is defined in - src/arch/x86/include/arch/<a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/include/arch/acpi.h;hb=HEAD#l237">acpi.h</a> -</p> - -<ol> - <li> - Select <a target="_blank" href="../Board/board.html#AcpiTables">HAVE_ACPI_TABLES</a> - in the board's Kconfig file - </li> - <li>Create a acpi.c module: - <ol type="A"> - <li>Add the acpi_fill_in_fadt routine and initialize the values above</li> - </ol> - </li> -</ol> - - - -<hr> -<h1><a name="LegacyHardware">Legacy Hardware</a></h1> -<p> - One of the payloads that needs legacy hardare is the EDK2 <a target="_blank" href="quark.html#CorebootPayloadPkg">CorebootPayloadPkg</a>. -</p> - -<table border="1"> - <tr bgcolor="c0ffc0"> - <th>Peripheral</th> - <th>Use</th> - <th>8259 Interrupt Vector</th> - <th>IDT Base Offset</th> - <th>Interrupt Handler</th> - </tr> - <tr> - <td> - <a target="_blank" href="http://www.scs.stanford.edu/10wi-cs140/pintos/specs/8254.pdf">8254</a> - Programmable Interval Timer - </td> - <td> - EDK2: PcAtChipsetPkg/8254TimerDxe/<a target="_blank" href="https://github.com/tianocore/edk2/blob/master/PcAtChipsetPkg/8254TimerDxe/Timer.c">Timer.c</a> - </td> - <td>0</td> - <td>0x340</td> - <td> - <a target="_blank" href="https://github.com/tianocore/edk2/blob/master/PcAtChipsetPkg/8254TimerDxe/Timer.c#l71">TimerInterruptHandler</a> - </td> - </tr> - <tr> - <td> - <a target="_blank" href="https://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=1&cad=rja&uact=8&ved=0ahUKEwibxYKU3ZDLAhVOzWMKHfuqB40QFggcMAA&url=http%3A%2F%2Fbochs.sourceforge.net%2Ftechspec%2Fintel-8259a-pic.pdf.gz&usg=AFQjCNF1NT0OQ6ys1Pn6Iv9sv6cKRzZbGg&sig2=HfBszp9xTVO_fajjPWCsJw">8259</a> - Programmable Interrupt Controller - </td> - <td> - EDK2: PcAtChipsetPkg/8259InterruptControllerDxe/<a target="_blank" href="https://github.com/tianocore/edk2/blob/master/PcAtChipsetPkg/8259InterruptControllerDxe/8259.c">8259.c</a> - </td> - <td> - Master interrupts: 0, 2 - 7<br> - Slave interrupts: 8 - 15<br> - Interrupt vector 1 is never generated, the cascaded input generates interrupts 8 - 15 - </td> - <td> - Master: 0x340, 0x350 - 0x378<br> - Slave: 0x380 - 0x3b8<br> - Interrupt descriptors are 8 bytes each - </td> - <td> </td> - </tr> -</table> - -<hr> -<p>Modified: 4 March 2016</p> - </body> -</html> \ No newline at end of file diff --git a/Documentation/Intel/development.html b/Documentation/Intel/development.html deleted file mode 100644 index a2ba278..0000000 --- a/Documentation/Intel/development.html +++ /dev/null @@ -1,377 +0,0 @@ -<!DOCTYPE html> -<html> - <head> - <title>Development</title> - </head> - <body> - -<h1>Intel® x86 coreboot/FSP Development Process</h1> -<p> - The x86 development process for coreboot is broken into the following components: -</p> -<ul> - <li>coreboot <a target="_blank" href="SoC/soc.html">SoC</a> development</li> - <li>coreboot <a target="_blank" href="Board/board.html">mainboard</a> development</li> - <li><a target="_blank" href="fsp1_1.html">FSP 1.1</a> integration</li> -</ul> -<p> - The development process has two main phases: -</p> -<ol> - <li>Minimal coreboot; This phase is single threaded</li> - <li>Adding coreboot features</li> -</ol> - -<h2>Minimal coreboot</h2> -<p> - The combined steps below describe how to bring up a minimal coreboot for a - system-on-a-chip (SoC) and a development board: -</p> -<table> - <tr bgcolor="#ffffc0"> - <td>The initial coreboot steps are single threaded! - The initial minimal FSP development is also single threaded. - Progress can speed up by adding more developers after the minimal coreboot/FSP - implementation reaches the payload. - </td> - </tr> -</table> -<ol> - <li>Get the necessary tools: - <ul> - <li>Linux: Use your package manager to install m4 bison flex and the libcurses development - package. - <ul> - <li>Ubuntu or other Linux distribution that use apt, run: -<pre><code>sudo apt-get install m4 bison flex libncurses5-dev -</code></pre> - </li> - </ul> - </li> - </ul> - </li> - <li>Build the cross tools for i386: - <ul> - <li>Linux: -<pre><code>make crossgcc-i386</code></pre> - To use multiple processors for the toolchain build (which takes a long time), use: -<pre><code>make crossgcc-i386 CPUS=N</code></pre> - where N is the number of cores to use for the build. - </li> - </ul> - </li> - <li>Get something to build: - <ol type="A"> - <li><a target="_blank" href="fsp1_1.html#RequiredFiles">FSP 1.1</a> required files</li> - <li><a target="_blank" href="SoC/soc.html#RequiredFiles">SoC</a> required files</li> - <li><a target="_blank" href="Board/board.html#RequiredFiles">Board</a> required files</li> - </ol> - </li> - <li>Get result to start <a target="_blank" href="SoC/soc.html#Descriptor">booting</a></li> - <li><a target="_blank" href="SoC/soc.html#EarlyDebug">Early Debug</a></li> - <li>Implement and debug the <a target="_blank" href="SoC/soc.html#Bootblock">bootblock</a> code</li> - <li>Implement and debug the call to <a target="_blank" href="SoC/soc.html#TempRamInit">TempRamInit</a></li> - <li>Enable the serial port - <ol type="A"> - <li>Power on, enable and configure GPIOs for the - <a target="_blank" href="Board/board.html#SerialOutput">debug serial UART</a> - </li> - <li>Add the <a target="_blank" href="SoC/soc.html#SerialOutput">serial outupt</a> - support to romstage - </li> - </ol> - </li> - <li>Enable <a target="_blank" href="fsp1_1.html#corebootFspDebugging">coreboot/FSP</a> debugging</li> - <li>Determine the <a target="_blank" href="SoC/soc.html#PreviousSleepState">Previous Sleep State</a></li> - <li>Enable DRAM: - <ol type="A"> - <li>Implement the SoC - <a target="_blank" href="SoC/soc.html#MemoryInit">MemoryInit</a> - Support - </li> - <li>Implement the board support to read the - <a target="_blank" href="Board/board.html#SpdData">Memory Timing Data</a> - </li> - </ol> - </li> - <li>Disable the - <a target="_blank" href="SoC/soc.html#DisableShadowRom">Shadow ROM</a> - </li> - <li>Enable CONFIG_DISPLAY_MTRRS to verify the MTRR configuration</li> - <li> - Implement the .init routine for the - <a target="_blank" href="SoC/soc.html#ChipOperations">chip operations</a> - structure which calls FSP SiliconInit - </li> - <li> - Start ramstage's - <a target="_blank" href="SoC/soc.html#DeviceTree">device tree processing</a> - to display the PCI vendor and device IDs - </li> - <li> - Disable the - <a target="_blank" href="Board/board.html#DisablePciDevices">PCI devices</a> - </li> - <li> - Implement the - <a target="_blank" href="SoC/soc.html#MemoryMap">memory map</a> - </li> - <li>coreboot should now attempt to load the payload</li> -</ol> - - - -<h2>Add coreboot Features</h2> -<p> - Most of the coreboot development gets done in this phase. Implementation tasks in this - phase are easily done in parallel. -</p> -<ul> - <li>Payload and OS Features: - <ul> - <li><a target="_blank" href="SoC/soc.html#AcpiTables">ACPI Tables</a></li> - <li><a target="_blank" href="SoC/soc.html#LegacyHardware">Legacy hardware</a> support</li> - </ul> - </li> -</ul> - - - -<hr> -<table border="1"> - <tr bgcolor="#c0ffc0"> - <th colspan=3><h1>Features</h1></th> - </tr> - <tr bgcolor="#c0ffc0"> - <th>SoC</th> - <th>Where</th> - <th>Testing</th> - </tr> - <tr> - <td>8254 Programmable Interval Timer</td> - <td><a target="_blank" href="SoC/soc.html#LegacyHardware">Legacy hardware</a> support</td> - <td><a target="_blank" href="SoC/quark.html#CorebootPayloadPkg">CorebootPayloadPkg</a> gets to shell prompt</td> - </tr> - <tr> - <td>8259 Programmable Interrupt Controller</td> - <td><a target="_blank" href="SoC/soc.html#LegacyHardware">Legacy hardware</a> support</td> - <td><a target="_blank" href="SoC/quark.html#CorebootPayloadPkg">CorebootPayloadPkg</a> gets to shell prompt</td> - </tr> - <tr> - <td>Cache-as-RAM</td> - <td> - <a target="_blank" href="SoC/soc.html#TempRamInit">Find</a> - FSP binary: - <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/cache_as_ram.inc;hb=HEAD#l38">cache_as_ram.inc</a><br> - Enable: FSP 1.1 <a target="_blank" href="SoC/soc.html#TempRamInit">TempRamInit</a> - called from - <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/cache_as_ram.inc;hb=HEAD#l73">cache_as_ram.inc</a><br> - Disable: FSP 1.1 TempRamExit called from - <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/after_raminit.S;hb=HEAD#l41">after_raminit.S</a><br> - </td> - <td>FindFSP: POST code 0x90 - (<a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l205">POST_FSP_TEMP_RAM_INIT</a>) - is displayed<br> - Enable: POST code - <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/cache_as_ram.inc;hb=HEAD#l151">0x2A</a> - is displayed<br> - Disable: CONFIG_DISPLAY_MTRRS=y, MTRRs displayed after call to TempRamExit - </td> - </tr> - <tr> - <td>Memory Map</td> - <td> - Implement a device driver for the - <a target="_blank" href="SoC/soc.html#MemoryMap">north cluster</a> - </td> - <td>coreboot displays the memory map correctly during the BS_WRITE_TABLES state</td> - </tr> - <tr> - <td>MTRRs</td> - <td> - Set values: src/drivers/intel/fsp1_1/stack.c/<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/stack.c;hb=HEAD#l42">setup_stack_and_mtrrs</a><br> - Load values: src/drivers/intel/fsp1_1/<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/after_raminit.S;hb=HEAD#l71">after_raminit.S</a> - </td> - <td>Set: Post code 0x91 - (<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l213">POST_FSP_TEMP_RAM_EXIT</a>) - is displayed by - <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/after_raminit.S;hb=HEAD#l41">after_raminit.S</a><br> - Load: Post code 0x3C is displayed by - <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/after_raminit.S;hb=HEAD#l152">after_raminit.S</a><br> - and CONFIG_DISPLAY_MTRRS=y displays the correct memory regions</td> - </tr> - <tr> - <td>PCI Device Support</td> - <td>Implement a PCI <a target="_blank" href="SoC/soc.html#DeviceDrivers">device driver</a></td> - <td>The device is detected by coreboot and usable by the payload</td> - </tr> - <tr> - <td>Ramstage state machine</td> - <td> - Implement the chip and domain operations to start the - <a target="_blank" href="SoC/soc.html#DeviceTree">device tree</a> - processing - </td> - <td> - During the BS_DEV_ENUMERATE state, ramstage now display the device IDs - for the PCI devices on the bus. - </td> - </tr> - <tr> - <td>ROM Shadow<br>0x000E0000 - 0x000FFFFF</td> - <td> - Disable: src/soc/<Vendor>/<Chip Family>/romstage/romstage.c/<a target="_blank" href="SoC/soc.html#DisableShadowRom">soc_after_ram_init routine</a> - </td> - <td>Operates as RAM: Writes followed by a read to the 0x000E0000 - 0x000FFFFF region returns the value written</td> - </tr> - - - <tr bgcolor="#c0ffc0"> - <th>Board</th> - <th>Where</th> - <th>Testing</th> - </tr> - <tr> - <td>Device Tree</td> - <td> - <a target="_blank" href="SoC/soc.html#DeviceTree">List</a> PCI vendor and device IDs by starting - the device tree processing<br> - <a target="_blank" href="Board/board.html#DisablePciDevices">Disable</a> PCI devices<br> - Enable: Implement a PCI <a target="_blank" href="SoC/soc.html#DeviceDrivers">device driver</a> - <td> - List: BS_DEV_ENUMERATE state displays PCI vendor and device IDs<br> - Disable: BS_DEV_ENUMERATE state shows the devices as disabled<br> - Enable: BS_DEV_ENUMERATE state shows the device as on and the device works for the payload - </td> - </tr> - <tr> - <td>DRAM</td> - <td> - Load SPD data: src/soc/mainboard/<Vendor>/<Board>/spd/<a target="_blank" href="Board/board.html#SpdData">spd.c</a><br> - UPD Setup: - <ul> - <li>src/soc<Vendor>//<Chip Family>/romstage/<a target="_blank" href="SoC/soc.html#MemoryInit">romstage.c</a></li> - <li>src/mainboard/<Vendor>/<Board>/<a target="_blank" href="Board/board.html#SpdData">romstage.c</a></li> - </ul> - FSP 1.1 MemoryInit called from src/drivers/intel/fsp1_1/<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/raminit.c;hb=HEAD#l126">raminit.c</a> - </td> - <td>Select the following Kconfig values - <ul> - <li>DISPLAY_HOBS</li> - <li>DISPLAY_UPD_DATA</li> - </ul> - Testing successful if: - <ul> - <li>MemoryInit UPD values are correct</li> - <li>MemoryInit returns 0 (success) and</li> - <li>The the message "ERROR - coreboot's requirements not met by FSP binary!" - is not displayed - </li> - </ul> - </td> - </tr> - <tr> - <td>Serial Port</td> - <td> - SoC <a target="_blank" href="SoC/soc.html#SerialOutput">Support</a><br> - Enable: src/soc/mainboard/<Board>/com_init.c/<a target="_blank" href="Board/board.html#SerialOutput">car_mainboard_pre_console_init</a> - </td> - <td>Debug serial output works</td> - </tr> - - - <tr bgcolor="#c0ffc0"> - <th>Payload</th> - <th>Where</th> - <th>Testing</th> - </tr> - <tr> - <td>ACPI Tables</td> - <td> - SoC <a target="_blank" href="SoC/soc.html#AcpiTables">Support</a><br> - </td> - <td>Verified by payload or OS</td> - </tr> - - - <tr bgcolor="#c0ffc0"> - <th>FSP</th> - <th>Where</th> - <th>Testing</th> - </tr> - <tr> - <td>TempRamInit</td> - <td>FSP <a target="_blank" href="SoC/soc.html#TempRamInit">TempRamInit</a></td> - <td>FSP binary found: POST code 0x90 - (<a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l205">POST_FSP_TEMP_RAM_INIT</a>) - is displayed<br> - TempRamInit successful: POST code - <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/cache_as_ram.inc;hb=HEAD#l151">0x2A</a> - is displayed<br> - </td> - </tr> - <tr> - <td>MemoryInit</td> - <td><a target="_blank" href="SoC/soc.html#MemoryInit">SoC</a> support<br> - <a target="_blank" href="Board/board.html#SpdData">Board</a> support<br> - </td> - <td>Select the following Kconfig values - <ul> - <li>DISPLAY_HOBS</li> - <li>DISPLAY_UPD_DATA</li> - </ul> - Testing successful if: - <ul> - <li>MemoryInit UPD values are correct</li> - <li>MemoryInit returns 0 (success) and</li> - <li>The the message "ERROR - coreboot's requirements not met by FSP binary!" - is not displayed - </li> - </ul> - </td> - </tr> - <tr> - <td>TempRamExit</td> - <td>src/drivers/intel/fsp1_1/<a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/after_raminit.S;hb=HEAD#l51">after_raminit.S</a></td> - <td>Post code 0x91 - (<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l212">POST_FSP_TEMP_RAM_EXIT</a>) - is displayed before calling TempRamExit by - <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/after_raminit.S;hb=HEAD#l141">after_raminit.S</a>, - CONFIG_DISPLAY_MTRRS=y displays the correct memory regions and - Post code 0x39 is displayed by - <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/after_raminit.S;hb=HEAD#l141">after_raminit.S</a><br> - </td> - </tr> - <tr> - <td>SiliconInit</td> - <td> - Implement the .init routine for the - <a target="_blank" href="SoC/soc.html#ChipOperations">chip operations</a> structure - </td> - <td>During BS_DEV_INIT_CHIPS state, SiliconInit gets called and returns 0x00000000</td> - </tr> - <tr> - <td>FspNotify</td> - <td> - The code which calls FspNotify is located in - src/drivers/intel/fsp1_1/<a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/fsp_util.c;hb=HEAD#l182">fsp_util.c</a>. - The fsp_notify_boot_state_callback routine is called three times as specified - by the BOOT_STATE_INIT_ENTRY macros below the routine. - </td> - <td> - The FspNotify routines are called during: - <ul> - <li>BS_DEV_RESOURCES - on exit</li> - <li>BS_PAYLOAD_LOAD - on exit</li> - <li>BS_OS_RESUME - on entry (S3 resume)</li> - </ul> - </td> - </tr> -</table> - - - -<hr> -<p>Modified: 4 March 2016</p> - </body> -</html> \ No newline at end of file diff --git a/Documentation/Intel/fsp1_1.html b/Documentation/Intel/fsp1_1.html deleted file mode 100644 index 1e1e88f..0000000 --- a/Documentation/Intel/fsp1_1.html +++ /dev/null @@ -1,77 +0,0 @@ -<!DOCTYPE html> -<html> - <head> - <title>FSP 1.1</title> - </head> - <body> - -<h1>x86 FSP 1.1 Integration</h1> -<p> - Firmware Support Package (FSP) integration requires System-on-a-Chip (SoC) - and board support. The combined steps are listed - <a target="_blank" href="development.html">here</a>. - The development steps for FSP are listed below: -</p> -<ol> - <li><a href="#RequiredFiles">Required Files</a></li> - <li>Add the <a href="#FspBinary">FSP Binary File</a> to the coreboot File System</li> - <li>Enable <a href="#corebootFspDebugging">coreboot/FSP Debugging</a></li> -</ol> - -<p> - FSP Documentation: -</p> -<ul> - <li>Intel® Firmware Support Package External Architecture Specification <a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/fsp-architecture-spec-v1-1.pdf">V1.1</a></li> -</ul> - -<hr> -<h1><a name="RequiredFiles">Required Files</a></h1> -<h2><a name="corebootRequiredFiles">coreboot Required Files</a></h2> -<ol> - <li>Create the following directories if they do not already exist: - <ul> - <li>src/vendorcode/intel/fsp/fsp1_1/<Chip Family></li> - <li>3rdparty/blobs/mainboard/<Board Vendor>/<Board Name></li> - </ul> - </li> - <li> - The following files may need to be copied from the FSP build or release into the - directories above if they are not present or are out of date: - <ul> - <li>FspUpdVpd.h: src/vendorcode/intel/fsp/fsp1_1/<Chip Family>/FspUpdVpd.h</li> - <li>FSP.bin: 3rdparty/blobs/mainboard/<Board Vendor>/<Board Name>/fsp.bin</li> - </ul> - </li> -</ol> - - -<hr> -<h1><a name="FspBinary">Add the FSP Binary File to coreboot File System</a></h1> -<p> - Add the FSP binary to the coreboot flash image using the following command: -</p> -<pre><code>util/cbfstool/cbfstool build/coreboot.rom add -t fsp -n fsp.bin -b <base address> -f fsp.bin</code></pre> -<p> - This command relocates the FSP binary to the 4K byte aligned location in CBFS so that the - FSP code for TempRamInit may be executed in place. -</p> - - -<hr> -<h1><a name="corebootFspDebugging">Enable coreboot/FSP Debugging</a></h1> -<p> - Set the following Kconfig values: -</p> -<ul> - <li>CONFIG_DISPLAY_FSP_ENTRY_POINTS - Display the FSP entry points in romstage</li> - <li>CONFIG_DISPLAY_HOBS - Display and verify the hand-off-blocks (HOBs) returned by MemoryInit</li> - <li>CONFIG_DISPLAY_VBT - Display Video BIOS Table (VBT) used for GOP</li> - <li>CONFIG_DISPLAY_UPD_DATA - Display the user specified product data passed to MemoryInit and SiliconInit</li> -</ul> - - -<hr> -<p>Modified: 17 May 2016</p> - </body> -</html> diff --git a/Documentation/Intel/index.html b/Documentation/Intel/index.html deleted file mode 100644 index cabcbff..0000000 --- a/Documentation/Intel/index.html +++ /dev/null @@ -1,86 +0,0 @@ -<!DOCTYPE html> -<html> - <head> - <title>Intel® x86</title> - </head> - <body> - -<h1>Intel® x86 Boards</h1> -<ul> - <li><a target="_blank" href="Board/galileo.html">Galileo</a></li> - <li><a target="_blank" href="http://wiki.minnowboard.org/Coreboot">MinnowBoard MAX</a></li> -</ul> - - - -<h1>Intel® x86 SoCs</h1> -<ul> - <li><a target="_blank" href="SoC/quark.html">Quark™</a></li> -</ul> - - - -<hr> -<h1>x86 coreboot Development</h1> -<ul> - <li>Get the <a target="_blank" href="https://www.coreboot.org/Git">coreboot source</li> - <li><a target="_blank" href="development.html">Overall</a> development</li> - <li><a target="_blank" href="fsp1_1.html">FSP 1.1</a> integration - </li> - <li><a target="_blank" href="SoC/soc.html">SoC</a> support</li> - <li><a target="_blank" href="Board/board.html">Board</a> support</li> -</ul> - - - -<hr> -<h1>Payload Development</h1> -<ul> - <li><a target="_blank" href="SoC/quark.html#CorebootPayloadPkg">CorebootPayloadPkg</a> - <ul> - <li><a target="_blank" href="https://github.com/tianocore/tianocore.github.io/wiki/EDK-II-Development-Process">EDK II Development Process</a></li> - <li>EDK II <a target="_blank" href="https://github.com/tianocore/tianocore.github.io/wiki/EDK%20II%20White%20papers">White Papers</a></li> - <li><a target="_blank" href="https://github.com/tianocore/tianocore.github.io/wiki/SourceForge-to-Github-Quick-Start">SourceForge to Github Quick Start</a></li> - <li>UEFI <a target="_blank" href="http://www.uefi.org/sites/default/files/resources/UEFI%20Spec%202_5_Errata_A.PDF">2.5 Errata A</a></li> - </ul> - </li> -</ul> - - - -<hr> -<h1><a name="Documentation">Documentation</a></h1> -<ul> - <li><a target="_blank" href="http://www.uefi.org/specifications">ACPI Specifications</a></li> - <li>Intel® 64 and IA-32 Architectures <a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-manual-325462.pdf">Software Developer Manual</a></li> - <li><a target="_blank" href="http://www.uefi.org/specifications">UEFI Specifications</a></li> -</ul> - -<h2><a name="Edk2Documentation">EDK-II Documentation</a></h2> -<ul> - <li>Build <a target="_blank" href="https://github.com/tianocore-docs/Docs/raw/master/Specifications/Build_Spec_1_26.pdf">V1.26</a></li> - <li>Coding Standards <a target="_blank" href="https://github.com/tianocore-docs/Docs/raw/master/Specifications/CCS_2_1_Draft.pdf">V2.1</a></li> - <li>DEC <a target="_blank" href="https://github.com/tianocore-docs/Docs/raw/master/Specifications/DEC_Spec_1_25.pdf">V1.25</a></li> - <li>DSC <a target="_blank" href="https://github.com/tianocore-docs/Docs/raw/master/Specifications/DSC_Spec_1_26.pdf">V1.26</a></li> - <li><a target="_blank" href="https://github.com/tianocore/tianocore.github.io/wiki/UEFI-Driver-Writer's-Guide">Driver Writer's Guide</a></li> - <li>Expression Syntax <a target="_blank" href="https://github.com/tianocore-docs/Docs/raw/master/Specifications/ExpressionSyntax_1.1.pdf">V1.1</a></li> - <li>FDF <a target="_blank" href="https://github.com/tianocore-docs/Docs/raw/master/Specifications/FDF_Spec_1_26.pdf">V1.26</a></li> - <li>INF <a target="_blank" href="https://github.com/tianocore-docs/Docs/raw/master/Specifications/INF_Spec_1_25.pdf">V1.25</a></li> - <li>PCD <a target="_blank" href="https://github.com/tianocore-docs/Docs/raw/master/Specifications/PCD_Infrastructure.pdf">PCD</a>V0.55</li> - <li>UNI <a target="_blank" href="https://github.com/tianocore-docs/Docs/raw/master/Specifications/UNI_File_Spec_v1_2_Errata_A.pdf">V1.2 Errata A</a></li> - <li>VRF <a target="_blank" href="https://github.com/tianocore-docs/Docs/raw/master/Specifications/VFR_1_9.pdf">V1.9</a></li> -</ul> - -<h2><a name="FspDocumentation">FSP Documentation</a></h2> -<ul> - <li>Intel® Firmware Support Package External Architecture Specification <a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/fsp-architecture-spec-v2.pdf">V2.0</a></li> - <li>Intel® Firmware Support Package External Architecture Specification <a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/fsp-architecture-spec-v1-1.pdf">V1.1</a></li> - <li>Intel® Firmware Support Package External Architecture Specification <a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/fsp-architecture-spec.pdf">V1.0</a></li> -</ul> - - - -<hr> -<p>Modified: 17 May 2016</p> - </body> -</html> diff --git a/Documentation/Kconfig.tex b/Documentation/Kconfig.tex deleted file mode 100644 index 2b2bf7f..0000000 --- a/Documentation/Kconfig.tex +++ /dev/null @@ -1,480 +0,0 @@ -\documentclass[10pt,letterpaper]{article} -\usepackage[latin1]{inputenc} -\usepackage{amsmath} -\usepackage{amsfonts} -\usepackage{amssymb} -\author{Ron Minnich} -\title{Kconfig usage in coreboot v2} -\begin{document} -\section{Introduction} -This document describes how to use Kconfig in v2. We describe our usage of Kconfig files, Makefile.inc files, when and where to use them, how to use them, and, interestingly, when and where not to use them. -\section{Kconfig variations} -Most Kconfig files set variables, which can be set as part of the Kconfig dialog. Not all Kconfig variables are set by the user, however; some are too dangerous. These are merely enabled by the mainboard. - -For variables set by the user, see src/console/Kconfig. - -For variables not set by the user, see src/mainboard/amd/serengeti\_cheetah/Kconfig. Users should never set such variables as the cache as ram base. These are highly mainboard dependent. - -Kconfig files use the source command to include subdirectories. In most cases, save for limited cases described below, subdirectories have Kconfig files. They are always sourced unconditionally. - -\section{Makefile and Makefile.inc} -There is only one Makefile, at the top level. All other makefiles are included as Makefile.inc. All the next-level Makefile.inc files are selected in the top level Makefile. Directories that are platform-independent are in BUILD-y; platform-dependent (e.g. Makefile.inc's that depend on architecture) are included in PLATFORM-y. - -Make is not recursive. There is only one make process. -\subsection{subdirs usage} -Further includes of Makefile.inc, if needed, are done via subdirs-y commands. As in Linux, the subdirs can be conditional or unconditional. Conditional includes are done via subdirs-\$(CONFIG\_VARIABLE) usage; unconditional are done via subdirs-y. - -We define the common rules for which variation to use below. -\subsection{object file specification} -There are several different types of objects specified in the tree. They are: -\begin{description} -\item[obj]objects for the ram part of the code -\item[driver]drivers for the ram part. Drivers are not represented in the device tree but do have a driver struct attached in the driver section. -\item[initobj]seperately-compiled code for the ROM section of coreboot -\end{description} -These items are specified via the -y syntax as well. Conditional object inclusion is done via the -\$(CONFIG\_VARIABLE) syntax. - -\section{Example: AMD serengeti cheetah} -\subsection{mainboard/Kconfig} -Defines Vendor variables. Currently defined variables are: -Sources all Kconfig files in the vendor directories. -\input{ mainboardkconfig.tex} -\subsection{mainboard/Makefile.inc} -There is none at this time. -\subsection{mainboard/$<$vendor$>$/Kconfig} -We use the amd as a model. The only action currently taken is to source all Kconfig's in the -subdirectories. -\subsection{mainboard/$<$vendor$>$/Makefile.inc} -We use amd as a model. There is currently no Makefile.inc at this level. -\subsection{mainboard/$<$vendor$>$/$<$board$>$/Kconfig} -The mainboard Kconfig and Makefile.inc are designed to be the heart of the build. The defines -and rules in here determine everything about how a mainboard target is built. -We will use serengeti\_cheetah as a model. It defines these variables. -\input{ mainboardkconfig.tex} -\subsection{mainboard/$<$vendor$>$/$<$board$>$/Makefile.inc} -This is a fairly complex Makefile.inc. Because this is such a critical component, we are going to excerpt and take it piece by piece. -Note that this is the mainboard as of August, 2009, and it may change over time. -\subsubsection{objects} -We define objects in the first part. The mainbard itself is a driver and included unconditionally. Other objects are conditional: -\begin{verbatim} -driver-y += mainboard.o - -#needed by irq_tables and mptable and acpi_tables -obj-y += get_bus_conf.o -obj-$(CONFIG_HAVE_MP_TABLE) += mptable.o -obj-$(CONFIG_HAVE_PIRQ_TABLE) += irq_tables.o -obj-$(CONFIG_HAVE_ACPI_TABLES) += dsdt.o -obj-$(CONFIG_HAVE_ACPI_TABLES) += acpi_tables.o -obj-$(CONFIG_HAVE_ACPI_TABLES) += fadt.o - -#./ssdt.o is in northbridge/amd/amdk8/Config.lb -obj-$(CONFIG_ACPI_SSDTX_NUM) += ssdt2.o -obj-$(CONFIG_ACPI_SSDTX_NUM) += ssdt3.o -obj-$(CONFIG_HAVE_ACPI_TABLES) += ssdt4.o -driver-y += ../../../drivers/i2c/i2cmux/i2cmux.o - -# This is part of the conversion to init-obj and away from included code. - -initobj-y += crt0.o -\end{verbatim} -\subsubsection{romcc legacy support} -We hope to move away from romcc soon, but for now, if one is using romcc, the Makefile.inc must define -crt0 include files (assembly code for startup, usually); and several ldscripts. These are taken directly from the -old Config.lb. Note that these use the -y syntax and can use the ability to be included conditionally. -\begin{verbatim} -crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc -crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc -crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc -crt0-y += ../../../../src/arch/i386/lib/id.inc -crt0-y += ../../../../src/cpu/amd/car/cache_as_ram.inc -crt0-y += auto.inc - -ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb -ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds -ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds -ldscript-y += ../../../../src/arch/i386/lib/id.lds -ldscript-y += ../../../../src/arch/i386/lib/failover.lds - -\end{verbatim} -\subsubsection{POST\_EVALUATION} -POST\_EVALUATION rules should be placed after this section: -\begin{verbatim} -ifdef POST_EVALUATION -\end{verbatim} -to ensure that the values of variables are correct. -Here are the post-evaluation rules for this mainboard: -\begin{verbatim} -$(obj)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl - iasl -p dsdt -tc $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl - mv dsdt.hex $@ - -$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/dsdt.c - $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $< -o $@ - -$(obj)/ssdt2.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci2.asl - iasl -p $(CURDIR)/pci2 -tc $(CONFIG_MAINBOARD)/dx/pci2.asl - perl -pi -e 's/AmlCode/AmlCode_ssdt2/g' pci2.hex - mv pci2.hex ssdt2.c - -$(obj)/ssdt3.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci3.asl" - iasl -p $(CURDIR)/pci3 -tc $(CONFIG_MAINBOARD)/ - perl -pi -e 's/AmlCode/AmlCode_ssdt3/g' pci3.hex - mv pci3.hex ssdt3.c - -$(obj)/ssdt4.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci4.asl" - iasl -p $(CURDIR)/pci4 -tc $(CONFIG_MAINBOARD)/dx/pci4.asl - perl -pi -e 's/AmlCode/AmlCode_ssdt4/g' pci4.hex - mv pci4.hex ssdt4.c - -$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/rom.c $(obj)/option_table.h - $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/rom.c -o $@ - perl -e 's/\.rodata/.rom.data/g' -pi $@ - perl -e 's/\.text/.section .rom.text/g' -pi $@ - -\end{verbatim} -The last rule is for romcc, and, again, we hope to eliminate romcc usage and this rule soon. The first set of rules concern ACPI tables. -\subsubsection{devicetree.cb} -Most of the old Config.lb is gone, but one piece remains: the device tree specification. This tree is still required to build a mainboard -properly, as it defines topology and chips that can be defined no other way. -Let's go through the tree. -\begin{verbatim} -chip northbridge/amd/amdk8/root_complex - device cpu_cluster 0 on - chip cpu/amd/socket_F - device lapic 0 on end - end - end -\end{verbatim} -This topology is always somewhat confusing to newcomers, and even to coreboot veterans. - -We root the tree at the pci-e {\it root complex}. There is always the question of how and where to root the tree. Over the years we -have found that the one part that never goes away is the root complex. CPU sockets may be empty or full; but there is always a northbridge -somewhere, since it runs memory. - - -What is the APIC? Northbridges always have an Advanced Programmable Interrupt Controller, and that {\it APIC cluster} is a topological connection to the -CPU socket. So the tree is rooted at the northbridge, which has a link to a CPU cluster, and then the CPU. The CPU contains -its own APIC, and will define any parameters needed. In this case, we have a northbridge of type -{\it northbridge/amd/amdk8/root\_complex}, with its own cpu\_cluster device which we turn on, -which connects to a {\it cpu/amd/socket\_F}, -which has a local apic, which is on. - -Note that we do not enumerate all CPUs, even on this SMP mainboard. The reason is they may not all be there. The CPU we define here -is the so-called Boot Strap Processor, or BSP; the other CPUs will come along later, as the are discovered. We do not require (unlike many -BIOSes) that the BSP be CPU 0; any CPU will do. -\begin{verbatim} - device domain 0 on - chip northbridge/amd/amdk8 - device pci 18.0 on # northbridge - # devices on link 0, link 0 == LDT 0 -\end{verbatim} -Here begins the pci domain, which usually starts with 0. Then there is the northbridge, which bridges to the PCI bus. On -Opterons, certain CPU control registers are managed in PCI config space in device 18.0 (BSP), 19.0 (AP), and up. -\begin{verbatim} - chip southbridge/amd/amd8132 - # the on/off keyword is mandatory - device pci 0.0 on end - device pci 0.1 on end - device pci 1.0 on end - device pci 1.1 on end - end -\end{verbatim} -This is the 8132, a bridge to a secondary PCI bus. -\begin{verbatim} - chip southbridge/amd/amd8111 - # this "device pci 0.0" is the parent the next one - # PCI bridge - device pci 0.0 on - device pci 0.0 on end - device pci 0.1 on end - device pci 0.2 off end - device pci 1.0 off end - end -\end{verbatim} -The 8111 is a bridge to other busses and to the legacy ISA devices such as superio. -\begin{verbatim} - device pci 1.0 on - chip superio/winbond/w83627hf - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.6 off # CIR - io 0x60 = 0x100 - end - device pnp 2e.7 off # GAME_MIDI_GIPO1 - io 0x60 = 0x220 - io 0x62 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.8 off end # GPIO2 - device pnp 2e.9 off end # GPIO3 - device pnp 2e.a off end # ACPI - device pnp 2e.b on # HW Monitor - io 0x60 = 0x290 - irq 0x70 = 5 - end - end - end -\end{verbatim} -The pnp refers to the many Plug N Play devices on a superio. 2e refers to the base I/O address of the superio, and the number following the -2e (i.e. 2e.1) is the Logical Device Number, or LDN. Each LDN has a common configuration (base, irq, etc.) and these are set by the statements under the LDN. -\begin{verbatim} - device pci 1.1 on end - device pci 1.2 on end -\end{verbatim} -More devices. These statements set up placeholders in the device tree. -\begin{verbatim} - device pci 1.3 on - chip drivers/i2c/i2cmux # pca9556 smbus mux - device i2c 18 on #0 pca9516 1 - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic #dimm 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic #dimm 0-1-1 - device i2c 53 on end - end - end - device i2c 18 on #1 pca9516 2 - chip drivers/generic/generic #dimm 1-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 1-0-1 - device i2c 51 on end - end - chip drivers/generic/generic #dimm 1-1-0 - device i2c 52 on end - end - chip drivers/generic/generic #dimm 1-1-1 - device i2c 53 on end - end - chip drivers/generic/generic #dimm 1-2-0 - device i2c 54 on end - end - chip drivers/generic/generic #dimm 1-2-1 - device i2c 55 on end - end - chip drivers/generic/generic #dimm 1-3-0 - device i2c 56 on end - end - chip drivers/generic/generic #dimm 1-3-1 - device i2c 57 on end - end - end - end - end # acpi -\end{verbatim} -These are the i2c devices. -\begin{verbatim} - device pci 1.5 off end - device pci 1.6 off end -\end{verbatim} -More placeholders. -\begin{verbatim} - register "ide0_enable" = "1" - register "ide1_enable" = "1" - end - end # device pci 18.0 - -\end{verbatim} -These "register" commands set controls in the southbridge. -\begin{verbatim} - device pci 18.0 on end - device pci 18.0 on end -\end{verbatim} -These are the other two hypertransport links. -\begin{verbatim} - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end -\end{verbatim} -The 18.1 devices are, again, northbridge control for various k8 functions. -\begin{verbatim} - end - \end{verbatim} -That's it for the BSP I/O and HT busses. Now we begin the AP busses. Not much here. -\begin{verbatim} - chip northbridge/amd/amdk8 - device pci 19.0 on # northbridge - chip southbridge/amd/amd8151 - # the on/off keyword is mandatory - device pci 0.0 on end - device pci 1.0 on end - end - end # device pci 19.0 - - device pci 19.0 on end - device pci 19.0 on end - device pci 19.1 on end - device pci 19.2 on end - device pci 19.3 on end - end - - -\end{verbatim} - -\subsection{cpu socket} -The CPU socket is the key link from mainboard to its CPUs. Since many models of CPU can go in a socket, the mainboard mentions only -the socket, and the socket, in turn, references the various model CPUs which can be plugged into it. The socket is thus the focus -of all defines and Makefile controls for building the CPU components of a board. - -\subsubsection{ cpu/Kconfig} -Defines variables. Current variables are: -\input{cpukconfig.tex} -Sources all Kconfig files in the vendor directories. -\subsubsection{ cpu/Makefile.inc} -Unconditionally sources all Makefile.inc in the vendor directories. - -\subsection{cpu/$<$vendor$>$/Kconfig} -The only action currently taken is to source all Kconfig's in the -subdirectories. -\subsection{cpu/$<$vendor$>$/Makefile.inc} -{\em Conditionally} source the socket directories. -Example: -\begin{verbatim} -subdirs-$(CONFIG_CPU_AMD_SOCKET_F) += socket_F -\end{verbatim} -. -CONFIG\_CPU\_AMD\_SOCKET\_F is set in a mainboard file. - -\subsection{cpu/$<$vendor$>$/$<$socket$>$/Kconfig} -Set variables that relate to this {\em socket}, and {\em any models that plug into this socket}. Note that -the socket, as much as possible, should control the models, because the models may plug into many sockets. -Socket\_F currently sets: -\input{socketfkconfig.tex} - -It sources only those Kconfigs that relate to this particular socket, i.e. not all possible models are sourced. - -\subsection{cpu/$<$vendor$>$/$<$model$>$/Kconfig} -CPU Model Kconfigs only set variables, We do not expect that they will source any other Kconfig. The socket Kconfig should do that -if needed. -\subsection{cpu/$<$vendor$>$/$<$model$>$/Makefile.inc} -The Makefile.inc {\em unconditionally} specifies drivers and objects to be included in the build. There is no conditional -compilation at this point. IF a socket is included, it includes the models. If a model is included, it should include {em all} -objects, because it is not possible to determine at build time what options may be needed for a given model CPU. -This Makefile.inc includes no other Makefile.inc files; any inclusion should be done in the socket Makefile.inc. - -\subsection{northbridge} -\subsubsection{northbridge/Kconfig} -No variables. Source all vendor directory Kconfigs. -\subsubsection{northbridge/Makefile.inc} -No variables. unconditionally include all vendor Makefile.inc -\subsubsection{northbridge/$<$vendor$>$/Kconfig} -No variables. Source all chip directory Kconfigs. -\subsubsection{northbridge/$<$vendor$>$/Makefile.inc} -No variables. {\em Conditionally} include all chipset Makefile.inc. The variable -is the name of the part, e.g. -\begin{verbatim} -subdirs-$(CONFIG_NORTHBRIDGE_AMD_AMDK8) += amdk8 -\end{verbatim} -. -\subsubsection{northbridge/$<$vendor$>$/$<$chip$>$/Kconfig} -Typically a small number of variables. One defines the part name. Here is an example -of the variables defined for the K8. -\begin{verbatim} -config NORTHBRIDGE_AMD_AMDK8 - bool - default n - -config AGP_APERTURE_SIZE - hex - default 0x4000000 -\end{verbatim} -\subsubsection{northbridge/$<$vendor$>$/$<$chip$>$/Makefile.inc} -Typically very small set of rules, and very simple. -Since this file is already conditionally included, -we don't need to test for the chipset CONFIG variable. We -can therefore test other variables (which is part of the reason -we set up conditional inclusion of this file, instead -of unconditionally including it). Here is an example from AMD K8. -Note that we can make a variable conditional on the ACPI tables. -\begin{verbatim} -driver-y += northbridge.o -driver-y += misc_control.o -obj-y += get_sblk_pci1234.o -obj-$(CONFIG_HAVE_ACPI_TABLES) += amdk8_acpi.o -\end{verbatim} - -\subsection{southbridge} -\subsubsection{southbridge/Kconfig} -No variables. Source all vendor directory Kconfigs. -\subsubsection{southbridge/Makefile.inc} -No variables. {\em Unconditionally} include all vendor Makefile.inc -\subsubsection{southbridge/$<$vendor$>$/Kconfig} -No variables. Source all chip directory Kconfigs. -\subsubsection{southbridge/$<$vendor$>$/Makefile.inc} -No variables. {\em Conditionally} include all chipset Makefile.inc. The variable -is the name of the part, e.g. -\begin{verbatim} -subdirs-$(CONFIG_SOUTHBRIDGE_AMD_AMD8111) += amd8111 -\end{verbatim} -. -\subsubsection{southbridge/$<$vendor$>$/$<$chip$>$/Kconfig} -Typically a small number of variables. One defines the part name. Here is an example -of the variables defined for the K8. -\begin{verbatim} -config SOUTHBRIDGE_AMD_AMD8111 - bool - default n - -\end{verbatim} -\subsubsection{southbridge/$<$vendor$>$/$<$chip$>$/Makefile.inc} -Typically very small set of rules, and very simple. -Since this file is already conditionally included, -we don't need to test for the chipset CONFIG variable. We -can therefore test other variables (which is part of the reason -we set up conditional inclusion of this file, instead -of unconditionally including it). Here is an example from AMD 8111. -No conditionals in this one yet. -\begin{verbatim} -driver-y += amd8111.o -driver-y += amd8111_usb.o -driver-y += amd8111_lpc.o -driver-y += amd8111_ide.o -driver-y += amd8111_acpi.o -driver-y += amd8111_usb2.o -driver-y += amd8111_ac97.o -driver-y += amd8111_nic.o -driver-y += amd8111_pci.o -driver-y += amd8111_smbus.o -obj-y += amd8111_reset.o -\end{verbatim} - -\subsubsection{vendor and part} -\subsection{southbridge} -\subsubsection{vendor and part} -\subsection{superio} -\subsection{drivers/i2c} -This is a rather special case. There are no Kconfig files or Makefile.inc files here. They are not needed. -To compile in one of these files, name the .o directory. E.g. in serengeti\_cheetah we have: -\begin{verbatim} -\end{verbatim} - -\subsubsection{vendor and part} - -\end{document} diff --git a/Documentation/Makefile b/Documentation/Makefile deleted file mode 100644 index 96b66a9..0000000 --- a/Documentation/Makefile +++ /dev/null @@ -1,70 +0,0 @@ -# -# Makefile for coreboot paper. -# hacked together by Stefan Reinauer <stepan@openbios.org> -# - -PDFLATEX=pdflatex -t a4 - -FIGS=codeflow.pdf hypertransport.pdf - -all: CorebootPortingGuide.pdf Kconfig.pdf - -SVG2PDF=$(shell which svg2pdf) -INKSCAPE=$(shell which inkscape) -CONVERT=$(shell which convert) - -codeflow.pdf: codeflow.svg -ifneq ($(strip $(SVG2PDF)),) - svg2pdf $< $@ -else ifneq ($(strip $(INKSCAPE)),) - inkscape $< --export-pdf=$@ -else ifneq ($(strip $(CONVERT)),) - convert $< $@ -endif - -hypertransport.pdf: hypertransport.svg -ifneq ($(strip $(SVG2PDF)),) - svg2pdf $< $@ -else ifneq ($(strip $(INKSCAPE)),) - inkscape $< --export-pdf=$@ -else ifneq ($(strip $(CONVERT)),) - convert $< $@ -endif - -CorebootPortingGuide.toc: $(FIGS) CorebootBuildingGuide.tex - # 2 times to make sure we have a current toc. - $(PDFLATEX) CorebootBuildingGuide.tex - $(PDFLATEX) CorebootBuildingGuide.tex - -CorebootPortingGuide.pdf: $(FIGS) CorebootBuildingGuide.tex CorebootPortingGuide.toc - $(PDFLATEX) CorebootBuildingGuide.tex - -Kconfig.pdf: Kconfig.tex mainboardkconfig.tex cpukconfig.tex socketfkconfig.tex - $(PDFLATEX) $< - -# quick, somebody! make me a macro! -mainboardkconfig.tex: ../src/mainboard/Kconfig - cat beginverbatim.tex > $@ - grep '^config' $< | awk '{print $2}' >>$@ - cat endverbatim.tex >> $@ - -skconfig.tex: ../src/mainboard/amd/serengeti_cheetah/Kconfig - cat beginverbatim.tex > $@ - grep '^config' $< | awk '{print $2}' >>$@ - cat endverbatim.tex >> $@ - -cpukconfig.tex: ../src/cpu/Kconfig - cat beginverbatim.tex > $@ - grep '^config' $< | awk '{print $2}' >>$@ - cat endverbatim.tex >> $@ - -socketfkconfig.tex: ../src/cpu/amd/socket_F/Kconfig - cat beginverbatim.tex > $@ - grep '^config' $< | awk '{print $2}' >>$@ - cat endverbatim.tex >> $@ - -clean: - rm -f *.aux *.idx *.log *.toc *.out $(FIGS) mainboardkconfig.tex skconfig.tex cpukconfig.tex socketfkconfig.tex - -distclean: clean - rm -f CorebootPortingGuide.pdf Kconfig.pdf diff --git a/Documentation/POSTCODES b/Documentation/POSTCODES deleted file mode 100644 index 5d337b6..0000000 --- a/Documentation/POSTCODES +++ /dev/null @@ -1,25 +0,0 @@ -------------------------------------------------------------------------------- -coreboot POST Codes -------------------------------------------------------------------------------- - -This is an (incomplete) list of POST codes emitted by coreboot v4. - -0x10 Entry into protected mode -0x01 Entry into 'crt0.s' reset code jumps to here -0x11 Start copying coreboot to RAM with decompression if compressed -0x12 Copy/decompression finished jumping to RAM -0x80 Entry into coreboot in RAM -0x13 Entry into c_start -0xfe Pre call to hardwaremain() -0x39 Console is initialized -0x40 Console boot message succeeded -0x66 Devices have been enumerated -0x88 Devices have been configured -0x89 Devices have been enabled -0xf8 Entry into elf boot -0xf3 Jumping to payload - -Errors (used in several places): - -0xee Not supposed to get here -0xff Elfload fail or die() called diff --git a/Documentation/RFC/chip.tex b/Documentation/RFC/chip.tex deleted file mode 100644 index 5e366b8..0000000 --- a/Documentation/RFC/chip.tex +++ /dev/null @@ -1,266 +0,0 @@ - RFC for the chip specification architecture - -\begin{abstract} -At the end of this document is the original message that motivated the -change. -\end{abstract} - -\section{Scope} -This document defines how LinuxBIOS programmers can specify chips that -are used, specified, and initalized. The current scope is for superio -chips, but the architecture should allow for specification of other chips such -as southbridges. Multiple chips of same or different type are supported. - -\section{Goals} -The goals of the new chip architecture are these: -\begin{itemize} -\item seperate implementation details from specification in the Config file -(translation: no more C code in Config files) -\item make the specification easier for people to use and understand -\item remove private details of a given chip to the chip file as much -as possible -\item allow unique register-set-specifiers for each chip -\end{itemize} - -\section{Specification in the Config file} -The specification looks like this: -\begin{verbatim} -chip <name> [path=<path>] ["<configuration>"] -\end{verbatim} -The name is in the standard LinuxBIOS form of type/vendor/name, e.g. -"southbridge/intel/piix4e" or "superio/ite/it8671f". The class of the -chip is derived from the first pathname component of the name, and the chip -configuration is derived from the following components. - -The path defines the access mechanism to the chip. -It is optional. If present, it overrides the default path to the chip. - -The configuration defines chip-specific configuration details, and is also -optional. Note that an empty configuration will leave the chip with -no enabled resources. This may be desirable in some cases. - -\section{Results of specifying a chip} - -When one or more chips are specified, the data about the chips -is saved until the entire file is parsed. At this point, the config tool -creates a file in the build directory called chip.c This file contains -a common struct containing information about -each individual chip and an array of pointers to these structures. - -For each chip, there are two structures. The structures contain control -information for the chip, and register initialization information. The -names of the structures are derived by ``flattening'' the chip name, -as in the current linuxbios. For example, superio/ite/xyz uses -two structs, one called superio_ite_xyz_control and one called -superio_ite_xyz_init. The control struct is initialized from the -chip name and path information, and has a pointer to the -config struct. The config struct is initialized from the quote string - -\begin{verbatim} -From rminnich@lanl.gov Fri May 16 10:34:13 2003 -Date: Tue, 13 May 2003 08:11:46 -0600 (MDT) -From: ron minnich <rminnich@lanl.gov> -To: linuxbios@clustermatic.org -Subject: RFC:new superio proposal - -Abstract: - The superio architecture for linuxbios has worked for the last 2 -years but is being stretched to the limit by the changes in superio chips. -The architecture depended on superio resources being relatively constant -between chips, but this assumption no longer holds. In this document we -propose several alternatives and solicit comments. - -Overview: -The superio architecture in linuxbios was developed over time, and -modified as circumstances required. In the beginning it was relatively -simple and assumed only one superio per mainboard. The latest version -allows an arbitrary number of superios per mainboard, and allows complete -specification of the superio base I/O address along with the specification -of reasonable default valures for both the base I/O address and the -superio parameters such as serial enable, baud rate, and so on. - -Specification of superio control parameters is done by a configuration -line such as: - -nsuperio sis/950 com1={1} floppy=1 lpt=1 - -This fragment sets the superio type to sis/950; sets com1, floppy, and lpt -to enabled; and leaves the defaults to com1 (baud rate, etc.) to the -default values. - -While it is not obvious, these configuration parameters are fragments of a -C initializer. The initializers are used to build a statically initialized -structure of this type: - -struct superio { - struct superio_control *super; // the ops for the device. - unsigned int port; // if non-zero, overrides the default port - // com ports. This is not done as an array (yet). - // We think it's easier to set up from python if it is not an - // array. - struct com_ports com1, com2, com3, com4; - // DMA, if it exists. - struct lpt_ports lpt1, lpt2; - /* flags for each device type. Unsigned int. */ - // low order bit ALWAYS means enable. Next bit means to enable - // LPT is in transition, so we leave this here for the moment. - // The winbond chips really stretched the way this works. - // so many functions! - unsigned int ide, floppy, lpt; - unsigned int keyboard, cir, game; - unsigned int gpio1, gpio2, gpio3; - unsigned int acpi,hwmonitor; -}; - -These structures are, in turn, created and statically initialized by a -config-tool-generated structure that defines all the superios. This file -is called nsuperio.c, is created for each mainboard you build, only -appears in the build directory, and looks like this: - -=== -extern struct superio_control superio_winbond_w83627hf_control; - -struct superio superio_winbond_w83627hf= { - &superio_winbond_w83627hf_control, - .com1={1}, .com2={1}, .floppy=1, .lpt=1, .keyboard=1, .hwmonitor=1}; - -struct superio *all_superio[] = {&superio_winbond_w83627hf, -}; - -unsigned long nsuperio = 1; -=== - -This example shows a board with one superio (nsuperio). The superio -consists of a winbond w83627hf, with com1, com2, floppy, lpt, keyboard, -and hwmonitor enabled. Note that this structure also allows for -over-riding the default superio base, although that capability is rarely -used. - -The control structure is used to define how to access the superio for -purposes of control. It looks like this: -=== -struct superio_control { - void (*pre_pci_init)(struct superio *s); - void (*init)(struct superio *s); - void (*finishup)(struct superio *s); - unsigned int defaultport; /* the defaultport. Can be overridden - * by commands in config - */ - // This is the print name for debugging - char *name; -}; -=== - -There are three methods for stages of hardwaremain. First is pre_pci_init -(for chips like the acer southbridge that require you to enable some -resources BEFORE pci scan); init, called during the 'middle' phase of -hardwaremain; and finishup, called before the payload is loaded. - -This approach was inspired by and borrows heavily on the Plan 9 kernel -configuration tools. - -The problem: - -When the first version of the superio structure came out it was much -smaller. It has grown and in the limit this structure is the union of all -possibly superio chips. Obviously, in the long term, this is not -practical: we can not anticipate all possible superio chips for all time. - -The common PC BIOS solution to this type of problem is to continue with -binary structures but add version numbers to them, so that all code that -uses a given structure has to check the version number. Personally, I find -this grotesque and would rather not work this way. - -Using textual strings for configuration is something I find far more -attractive. Plan 9 has shown that this approach has no real limits and -suffices for configuration tasks. The Linux kernel does more limited use -of strings for configuration, but still depends on them. Strings are -easier to read and work with than binary structures, and more important, a -lot easier to deal with when things start going wrong. - -The proposed solution: - -What follows are three possible ideas for specifying superio resources and -their settings. - -A common part of the new idea is to eliminate the common superio -structure, due to the many variations in chips, and make it invisible -outside a given superio source file -- the superio structure is now -private to a given superio. Thus, sis/950/superio.c would contain its own -superio structure definitions, and also might contain more than once -instance of these structures (consider a board with 2 sis 950 chips). - -The control structure would change as follows: -struct superio_control { - int (*create)(struct superio *s); - void (*pre_pci_init)(struct superio *s); - void (*init)(struct superio *s); - void (*finishup)(struct superio *s); - unsigned int defaultport; /* the defaultport. Can be overridden - * by commands in config - */ - // This is the print name for debugging - char *name; -}; - -I.e. we add a new function for creating the superio. - -Communication of superio settings from linuxbios to the superio would be -via textual strings. The superio structure becomes this: - -struct superio { - struct superio_control *super; // the ops for the device. - unsigned int port; // if non-zero, overrides the default port - struct configuration *config; -}; - - -So now the question becomes, what is the configuration structure? -There are several choices. The simplest, from my point of view, are -keyword-value pairs: -struct configuration { - const char *keyword; - const char *value; -}; - -These get filled in by the config tool as before. The linuxbios libary can -then provide a generic parsing function for the superios to use. - -The remaining question is how should the superio command look in -freebios2? - -superio sis/950 "com1=115200,8n1 lpt=1 com2=9600" - -or - -superio sis/950 "com1baud=115200 lpt=1 com1chars=8n1" - -or - -superio sis/950 ((com1 115200 8n1) (lpt 1)) - -So, my questions: - -1. Does this new scheme look workable. If not, what needs to change? -2. What should the 'struct configuration' be? does keyword/value work? -3. what should the superio command look like? - -Comments welcome. - -I'd like to adopt this "RFC" approach for freebios2 as much as we can. -There was a lot of give-and-take in the early days of linuxbios about -structure and it proved useful. There's a lot that will start happening in -freebios2 now, and we need to try to make sure it will work for everyone. - -Those of you who are doing mainboards, please look at freebios2 and see -how it looks for you. There's a lot of good work that has been done (not -by me so far, thanks Eric and Stefan), and more that needs to be done. -Consider trying out romcc as an "assembly code killer". See how it fits -together and if you can work with it or need changes. Bring comments back -to this list. - -thanks - -ron - -\end{verbatim} diff --git a/Documentation/RFC/config.tex b/Documentation/RFC/config.tex deleted file mode 100644 index 696ab7a..0000000 --- a/Documentation/RFC/config.tex +++ /dev/null @@ -1,290 +0,0 @@ - New config language for LinuxBIOS - -\begin{abstract} -We describe the new configuration language for LinuxBIOS. -\end{abstract} - -\section{Scope} -This document defines the new configuration language for LinuxBIOS. - -\section{Goals} -The goals of the new language are these: -\begin{itemize} -\item Simplified Makefiles so people can see what is set -\item Move from the regular-expression-based language to something -a bit more comprehensible and flexible -\item make the specification easier for people to use and understand -\item allow unique register-set-specifiers for each chip -\item allow generic register-set-specifiers for each chip -\item generate static initialization code, as needed, for the -specifiers. -\end{itemize} - -\section{Language} -Here is the new language. It is very similar to the old one, differing -in only a few respects. It borrows heavily from Greg Watson's suggestions. - -I am presenting it in a pseudo-BNF in the hopes it will be easier. Things -in '' are keywords; things in ``'' are strings in the actual text. -\begin{verbatim} -#exprs are composed of factor or factor + factor etc. -expr ::= factor ( ``+'' factor | ``-'' factor | )* -#factors are term or term * term or term / term or ... -factor ::= term ( ``*'' term | ``/'' term | ... )* -# -unary-op ::= ``!'' ID -# term is a number, hexnumber, ID, unary-op, or a full-blown expression -term ::= NUM | XNUM | ID | unary-op | ``(`` expr ``)'' - -# Option command. Can be an expression or quote-string. -# Options are used in the config tool itself (in expressions and 'if') -# and are also passed to the C compiler when building linuxbios. -# It is an error to have two option commands in a file. -# It is an error to have an option command after the ID has been used -# in an expression (i.e. 'set after used' is an error) -option ::= 'option' ID '=' (``value'' | term) - -# Default command. The ID is set to this value if no option command -# is scanned. -# Multiple defaults for an ID will produce warning, but not errors. -# It is OK to scan a default command after use of an ID. -# Options always over-ride defaults. -default ::= 'default' ID '=' (``value'' | term) - -# the mainboard, southbridge, northbridge commands -# cause sourcing of Config.lb files as in the old config tool -# as parts are sourced, a device tree is built. The structure -# of the tree is determined by the structure of the components -# as they are specified. To attach a superio to a southbridge, for -# example, one would do this: -# southbridge acer/5432 -# superio nsc/123 -# end -# end -# the tool generates static initializers for this hierarchy. - -# add C code to the current component (motherboard, etc. ) -# to initialise the component-INDEPENDENT structure members -init ::= 'init' ``CODE'' - -# add C code to the current component (motherboard, etc. ) -# to initialise the component-DEPENDENT structure members -register ::= 'register' ``CODE'' - - -# mainboard command -# statements in this block will set variables controlling the mainboard, -# and will also place components (northbridge etc.) in the device tree -# under this mainboard -mainboard ::= 'mainboard' PATH (statements)* 'end' - -# standard linuxbios commands -southbridge ::= 'southbridge' PATH (statemnts)* 'end' -northbridge ::= 'northbridge' PATH (statemnts)* 'end' -superio ::= 'superio PATH (statemnts)* 'end' -cpu ::= 'cpu' PATH (statemnts)* 'end' -arch ::= 'arch' PATH (statemnts)* 'end' - -# files for building linuxbios -# include a file in crt0.S -mainboardinit ::= 'mainboardinit' PATH - -# object file -object ::= 'object' PATH -# driver objects are just built into the image in a different way -driver ::= 'driver' PATH - -# Use the Config.lb file in the PATH -dir ::= 'dir' PATH - -# add a file to the set of ldscript files -ldscript ::= 'ldscript' PATH - -# dependencies or actions for the makerule command -dep ::= 'dep' ``dependency-string'' -act ::= 'act' ``actions'' -depsacts ::= (dep | act)* -# set up a makerule -# -makerule ::= 'makerule' PATH depsacts - -#defines for use in makefiles only -# note usable in the config tool, not passed to cc -makedefine ::= 'makedefine' ``RAWTEXT'' - -# add an action to an existing make rule -addaction ::= 'addaction' PATH ``ACTION'' - -# statements -statement ::= - option - | default - | cpu - | arch - | northbridge - | southbridge - | superio - | object - | driver - | mainboardinit - | makerule - | makedefine - | addaction - | init - | register - | iif - | dir - | ldscript - -statements ::= (statement)* - -# target directory specification -target ::= 'target' PATH - -# and the whole thing -board ::= target (option)* mainboard - -\end{verbatim} - -\subsubsection{Command definitions} -\subsubsubsection{option} -\subsubsubsection{default} -\subsubsubsection{cpu} -\subsubsubsection{arch} -\subsubsubsection{northbridge} -\subsubsubsection{southbridge} -\subsubsubsection{superio} -\subsubsubsection{object} -\subsubsubsection{driver} -\subsubsubsection{mainboardinit} -\subsubsubsection{makerule} -\subsubsubsection{makedefine} -\subsubsubsection{addaction} -\subsubsubsection{init} -\subsubsubsection{register} -\subsubsubsection{iif} -\subsubsubsection{dir} -\subsubsubsection{ldscript} - - -A sample file: - -\begin{verbatim} -target x - -# over-ride the default rom size in the mainboard file -option CONFIG_ROM_SIZE=1024*1024 -mainboard amd/solo -end - -\end{verbatim} - -Sample mainboard file -\begin{verbatim} -# -### -### Set all of the defaults for an x86 architecture -### -arch i386 end -cpu k8 end -# -option CONFIG_DEBUG=1 -default CONFIG_USE_FALLBACK_IMAGE=1 -option A=(1+2) -option B=0xa -# -### -### Build our 16 bit and 32 bit linuxBIOS entry code -### -mainboardinit cpu/i386/entry16.inc -mainboardinit cpu/i386/entry32.inc -ldscript cpu/i386/entry16.lds -ldscript cpu/i386/entry32.lds -# -### -### Build our reset vector (This is where linuxBIOS is entered) -### -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/i386/reset16.inc - ldscript cpu/i386/reset16.lds -else - mainboardinit cpu/i386/reset32.inc - ldscript cpu/i386/reset32.lds -end -. -. -. -if CONFIG_USE_FALLBACK_IMAGE mainboardinit arch/i386/lib/noop_failover.inc end -# -### -### Romcc output -### -#makerule ./failover.E dep "$(CONFIG_MAINBOARD)/failover.c" act "$(CPP) -I$(TOP)/src $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c > ./failever.E" -#makerule ./failover.inc dep "./romcc ./failover.E" act "./romcc -O ./failover.E > failover.inc" -#mainboardinit ./failover.inc -makerule ./auto.E dep "$(CONFIG_MAINBOARD)/auto.c" act "$(CPP) -I$(TOP)/src -$(ROMCCPPFLAGS) $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c > ./auto.E" -makerule ./auto.inc dep "./romcc ./auto.E" act "./romcc -O ./auto.E > auto.inc" -mainboardinit ./auto.inc -# -### -### Include the secondary Configuration files -### -northbridge amd/amdk8 -end -southbridge amd/amd8111 -end -#mainboardinit arch/i386/smp/secondary.inc -superio nsc/pc87360 - register "com1={1} com2={0} floppy=1 lpt=1 keyboard=1" -end -dir /pc80 -##dir /src/superio/winbond/w83627hf -cpu p5 end -cpu p6 end -cpu k7 end -cpu k8 end -# -### -### Build the objects we have code for in this directory. -### -##object mainboard.o -driver mainboard.o -object static_devices.o -if CONFIG_HAVE_MP_TABLE object mptable.o end -if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end -### Location of the DIMM EEPROMS on the SMBUS -### This is fixed into a narrow range by the DIMM package standard. -### -option SMBUS_MEM_DEVICE_START=(0xa << 3) -option SMBUS_MEM_DEVICE_END=(SMBUS_MEM_DEVICE_START +1) -option SMBUS_MEM_DEVICE_INC=1 -# -### The linuxBIOS bootloader. -### -option CONFIG_PAYLOAD_SIZE = (CONFIG_ROM_SECTION_SIZE - CONFIG_ROM_IMAGE_SIZE) -option CONFIG_ROM_PAYLOAD_START = (0xffffffff - CONFIG_ROM_SIZE + CONFIG_ROM_SECTION_OFFSET + 1) -# - -\end{verbatim} - -I've found the output of the new tool to be easier to -handle. Makefile.settings looks like this, for example: -\begin{verbatim} -TOP:=/home/rminnich/src/yapps2/freebios2 -TARGET_DIR:=x -export CONFIG_MAINBOARD:=/home/rminnich/src/yapps2/freebios2/src/mainboard/amd/solo -export CONFIG_ARCH:=i386 -export CONFIG_RAMBASE:=0x4000 -export CONFIG_ROM_IMAGE_SIZE:=65535 -export CONFIG_PAYLOAD_SIZE:=131073 -export CONFIG_MAX_CPUS:=1 -export CONFIG_HEAP_SIZE:=8192 -export CONFIG_STACK_SIZE:=8192 -export CONFIG_MEMORY_HOLE:=0 -export COREBOOT_VERSION:=1.1.0 -export CC:=$(CONFIG_CROSS_COMPILE)gcc - -\end{verbatim} - -In other words, instead of expressions, we see the values. It's easier to -deal with. diff --git a/Documentation/abi-data-consumption.txt b/Documentation/abi-data-consumption.txt deleted file mode 100644 index 81442e7..0000000 --- a/Documentation/abi-data-consumption.txt +++ /dev/null @@ -1,22 +0,0 @@ -This text describes the ABI coreboot presents to downstream users. Such -users are payloads and/or operating systems. Therefore, this text serves -at what can be relied on for downstream consumption. Anything not explicitly -listed as consumable is subject to change without notice. - -Background and Usage - -coreboot passes information to downstream users using coreboot tables. These -table definitions can be found in src/include/boot/coreboot_tables.h and -payloads/libpayload/include/coreboot_tables.h respectively within coreboot -and libpayload. One of the most vital and important pieces of information -found within these tables is the memory map of the system indicating -available and reserved memory. - -In 2009 cbmem was added to coreboot. The "CBMEM high table memory manager" -serves a way for coreboot to bookkeep its own internal data. While some -of this data may be exposed through the coreboot tables the data structures -used to manage the data within the cbmem area is subject to change. - -Provided the above, if one needs a piece of data exposed to the OS -or payload it should reside within the coreboot tables. If it isn't there -then a code change will be required to add it to the coreboot tables. diff --git a/Documentation/backup-docs/index.md b/Documentation/backup-docs/index.md new file mode 100644 index 0000000..0c7ee73 --- /dev/null +++ b/Documentation/backup-docs/index.md @@ -0,0 +1,10 @@ +--- +date: 2016-03-08T21:07:13+01:00 +title: The Project +type: index +weight: 0 +--- + +## Introduction + +Welcome to coreboot diff --git a/Documentation/backup-docs/old/AMD-S3.txt b/Documentation/backup-docs/old/AMD-S3.txt new file mode 100644 index 0000000..48d4c8f --- /dev/null +++ b/Documentation/backup-docs/old/AMD-S3.txt @@ -0,0 +1,153 @@ + _____ ____ _____ ______ ____ ____ ____ _______ + / ____/ __ \| __ \| ____| _ \ / __ \ / __ \__ __| + | | | | | | |__) | |__ | |_) | | | | | | | | | + | | | | | | _ /| __| | _ <| | | | | | | | | + | |___| |__| | | \ \| |____| |_) | |__| | |__| | | | + \_____\____/|_| \_\______|____/ \____/ \____/ |_| + + __ __ _____ _____ ____ + /\ | \/ | __ \ / ____| |___ \ + / \ | \ / | | | | | (___ __) | + / /\ \ | |\/| | | | | \___ \ |__ < + / ____ \| | | | |__| | ____) | ___) | + /_/ \_\_| |_|_____/ |_____/ |____/ + + + S3 in Coreboot (V 1.2) +---------------------------------------- + Zheng Bao + <zheng.bao@amd.com> + <fishbaozi@gmail.com> + +Introduction +============ +This document is about how the feature S3 is implemented on coreboot, +specifically on AMD platform. This topic deals with ACPI spec, hardware, +BIOS, OS. We try to help coreboot users to realize their own S3. + +S3 in a nutshell +================ +The S3 sleeping state is a low wake latency sleeping state where all +system context is lost except system memory. [1]. S3 is a ACPI +definition. +To enter S3, write 3 in SLP_TYPx and set the SLP_EN bit (See ACPI +registers). But if you do that, board can not resume at where it +sleeps, because you don't save the context. More often than not, we +make the board go into S3 by the tools which OSes provide. For +windows, click Start->sleep. For linux, some distribution provide a +tools called pm-suspend, which can make the system goto S3. If +pm-suspend is not available, we can run "echo mem > /sys/power/state", +but this way may not save all the needed context. +In S3 state, the power is off. So when the power button is pressed, +BIOS runs as it does in cold boot. If BIOS didn't detect whether +board boots or resumes, it would go the same way as boot. It is not +what we expect. BIOS detects the SLP_TYPx. If it is 3, it means BIOS +are waking up. +BIOS is responsible for restore the machine state as it is before +sleep. It needs restore the memory controller, not overwriting memory +which is not marked as reserved. For the peripheral which loses its +registers, BIOS needs to write the original value. +When everything is done, BIOS needs to find out the wakeup vector +provided by OSes and jump there. OSes also have work to do. We can go +to linux kernel or some other open source projects to find out how they +handle S3 resume. + +ACPI registers +============== +ACPI specification defines a group of registers. OSes handle all these +registers to read and write status to all the platform. +On AMD platform, these registers are provided by southbridge. For +example, Hudson uses PMIO 60:6F to define ACPI registers. +OSes don't have any specific driver to know where these registers +are. BIOS has the responsibility to allocated the IO resources and +write all these address to FADT, a ACPI defined table. + +Memory Layout +============= +Restoring memory is the most important job done by BIOS. When the +power is off, the memory is maintained by standby power. BIOS need to +make sure that when flow goes to OS, everything in memory should be +the same as it was. + +The chip vendor will provide a way, or code, to wake up the memory +from sleeping. In AGESA 2008 arch, it is called AmdInitResume. + +The BIOS itself needs some memory to run. Either, BIOS marks the erea +as reserved in e820, or BIOS saves the content into reserved space. + +Here is the address Map for S3 Resume. Assumingly the total memory is 1GB. +00000000 --- 00100000 BIOS Reserved area. +00100000 --- 00200000 Free +00200000 --- 01000000 Coreboot ramstage area. +01000000 --- 2e160000 Free +2e160000 --- 2e170000 ACPI table +2e170000 --- 2ef70000 OSRAM +2ef70000 --- 2efe0000 Stack in highmem +2efe0000 --- 2f000000 heap in highmem +2f000000 TOM + +AMD requirements in S3 +====================== +Chip vendor like AMD will provide bunch of routines to restore the +board.[2] + * AmdS3Save: It is called in cold boot, save required register into + non-volatile storage. Currently, we use SPI flash to store the data. + * AmdInitResume: Restore the memory controller. + * AmdS3LateRestore: Called after AmdInitResume, restore other + register that memory. + * (SouthBridge)InitS3EarlyRestore, (SouthBridge)InitS3LateRestore: + Provided by Southbridge vendor code. Early is called before PCI + enumeration, and Late is called after that. + +Lifecycle of booting, sleeping and waking Coreboot and Ubuntu +============================================================= +1. Cold boot. +For a system with S3 feature, the BIOS needs to save some data to +non-volatile storage at cold boot stage. What data need to be save are +provided by AmdS3Save. After the wrapper calls the AmdS3Save, it gets +the VolatileStorage and NvStorage, which are where the data are +located. It is the wrappers's responsibility to save the data.[3][4] +Currently, the wrappers allocate a CBFS modules in BIOS image. To do +that, the wrapper needs to have the ability to write flash chips. It +is not as comprehensive as flashrom. But for the SST chip on Parmer, +MX chip on Thather, coreboot works well.[5] + +2. OS goes in S3. +For Linux, besides the kernel needs to do some saving, most distributions +run some scripts. For Ubuntu, scripts are located at /usr/lib/pm-utils/sleep.d. + # ls /usr/lib/pm-utils/sleep.d + 000kernel-change 49bluetooth 90clock 95led + 00logging 55NetworkManager 94cpufreq 98video-quirk-db-handler + 00powersave 60_wpa_supplicant 95anacron 99video + 01PulseAudio 75modules 95hdparm-apm +The script with lower prefix runs before the one with higher prefix. +99video is the last one. +Those scripts have hooks called hibernate, suspend, thaw, resume. For +each script, suspend is called when system sleeps and wakeup is called +when system wakeups. + +3. Firmware detects S3 wakeup +As we mentioned, Firmware detects the SLP_TYPx to find out if the board +wakes up. In romstage.c, AmdInitReset and AmdInitEarly are called +as they are during cold boot. AmdInitResume and AmdS3LateRestore are +called only during resume. For whole ramstage, Coreboot goes through +almost the same way as cold boot, other than not calling the AmdInitMid, +AmdInitLate and AmdS3Save, and restoring all the MTRRs. +At last step of coreboot stage, coreboot finds out the wakeup vector in FADT, +written by OS, and jump. + +4. OS resumes. +When Linux resumes, all the sleeping scripts call their resume +hooks. If we are more lucky, all the scripts can go through. More +chances that the 99video hangs or fails to get the display +back. Sometimes it can fixed if CONFIG_S3_VGA_ROM_RUN is unset in +Coreboot/Kconfig. That needs more troubleshooting. + + +Reference +========= +[1] ACPI40a, http://www.acpi.info/spec40a.htm +[2] Coreboot Vendorcode, {top}/src/vendorcode/amd/agesa/{family}/Proc/Common/ +[3] Coreboot AGESA wrapper, {top}/src/mainboard/amd/parmer/agesawrapper.c +[4] Coreboot AGESA wrapper, {top}/src/cpu/amd/agesa/s3_resume.c +[5] Coreboot Southbridge, {top}/src/southbridge/amd/agesa/hudson/spi.c diff --git a/Documentation/backup-docs/old/CorebootBuildingGuide.tex b/Documentation/backup-docs/old/CorebootBuildingGuide.tex new file mode 100644 index 0000000..dac031a --- /dev/null +++ b/Documentation/backup-docs/old/CorebootBuildingGuide.tex @@ -0,0 +1,671 @@ +% +% This document is released under the GPL +% Initially written by Stefan Reinauer, <stepan@coresystems.de> +% + +\documentclass[titlepage,12pt]{article} +\usepackage{a4} +\usepackage{graphicx} +\usepackage{epsfig} +\usepackage{epstopdf} +\usepackage{url} +\usepackage{color} +% \usepackage{geometry} +\usepackage[pdftex]{hyperref} +% \usepackage{makeidx} +% \makeindex +% \geometry{left=2cm,right=2cm,top=2cm,bottom=2cm} + +\hypersetup{ + urlbordercolor={1 1 1}, + menubordercolor={1 1 1}, + linkbordercolor={1 1 1}, + colorlinks=false, + % pdfpagemode=None, % PDF-Viewer starts without TOC + % pdfstartview=FitH, + pdftitle={Coreboot Porting Guide}, + pdfauthor={Zheng Bao}, + pdfsubject={coreboot configuration and build process}, + pdfkeywords={coreboot, AMD, configuration, Build} +} + +\setlength{\parindent}{0pt} +\setlength{\hoffset}{0pt} + +\title{Coreboot from Scratch} +\author{Stefan Reinauer $<$stepan@coresystems.de$>$\and Zheng Bao $<$zheng.bao@amd.com$>$} +\date{Dec 4th, 2013} + +\begin{document} + +\maketitle + +\thispagestyle{empty} + +\tableofcontents + +\newpage + +\section{What is Coreboot} +coreboot aims to replace the normal BIOS found on x86, AMD64, PPC, +Alpha, and other machines with a Linux kernel that can boot Linux from a cold +start. The startup code of an average coreboot port is about 500 lines of +assembly and 5000 lines of C. It executes 16 instructions to get into 32bit +protected mode and then performs DRAM and other hardware initializations +required before Linux can take over. + +The projects primary motivation initially was maintenance of large +clusters. Not surprisingly interest and contributions have come from +people with varying backgrounds. Nowadays a large and growing number of +Systems can be booted with coreboot, including embedded systems, +Desktop PCs and Servers. + +This document is used to build, modify, and port the CoreBoot code +base on the AMD platform. + + +\section{Changes} + + \begin{itemize} + \item 2013/12/20 Add Git, Gerrit, toolchains building. + \item 2009/04/19 replace LinuxBIOS with coreboot + \item 2004/06/02 url and language fixes from Ken Fuchs $<$kfuchs@winternet.com$>$ + \item 2004/02/10 acpi and option rom updates + \item 2003/11/18 initial release + \end{itemize} + +% +% Build Requirements +% + +\section{Build Requirements} +To build coreboot for AMD64 from the sources you need a recent Linux. +SUSE Linux 11.2, CentOS release 6.3, Fedora Core 16, Cygwin, FreeBSD, +NetBSD are known to work fine. + +To build the toolchain, you need following host compilers: + + \begin{itemize} + \item GNUtar + \item GNUpatch + \item GNUmake + \item GCC + \item binutils + \item bison + \item flex + \item m4 + \item wget + \end{itemize} + +Besides the tools above, after the toolchains are built, you also need the following +tools to build the source. + + \begin{itemize} + \item git: Get the source code from repository + \item libncurses-dev (or ncursesw, ncurses, curses, pdcursesw, pdcurses): for menuconfig + \item python: Optional for gdb. + \item perl: Optional for gdb. + \end{itemize} + +% +% Getting Coreboot +% + +\section{Getting Coreboot} +The latest coreboot sources are available via GIT. +For users who doesn't need to change and commit the code: +{ \small +\begin{verbatim} +$ git clone http://review.coreboot.org/p/coreboot +\end{verbatim} +} +For developers, you need to get a gerrit account which you can register +at \url{http://review.coreboot.org}. Please refer section ~\ref{sec:gerrit} +{ \small +\begin{verbatim} +$ git clone ssh://<username>@review.coreboot.org:29418/coreboot +$ git clone http://[<username>:<password>@]review.coreboot.org/coreboot.git +\end{verbatim} +} + +Checks out a sub-repository in the 3rdparty directory. +{ \small +\begin{verbatim} +$ git submodule update --init --checkout +\end{verbatim} +} + +% +% Building the toolchain +% + +\section{Building the toolchain} +Coreboot recommends and guarantees the toolchain integrated with Coreboot. +Linux distributions usually modify their compilers in ways incompatible with Coreboot. + +{ \small +\begin{verbatim} +$ cd coreboot +$ make crossgcc +\end{verbatim} +} + +or + +{ \small +\begin{verbatim} +$ cd util/crossgcc +$ buildgcc +\end{verbatim} +} + +The buildgcc will try to get packages from website. You need to make sure you can +get access the internet. Or you can get the source.tar.gz and put it in util/crossgcc/tarballs. + +{ \small +\textcolor{blue} {Welcome to the} \textcolor{red} {coreboot} \textcolor{blue} {cross toolchain builder v1.23 (September 20th, 2013)} + +Target arch is now i386-elf + +Will skip GDB ... ok + +Downloading tar balls ... + + * gmp-5.1.2.tar.bz2 (cached) + + * mpfr-3.1.2.tar.bz2 (cached) + + * mpc-1.0.1.tar.gz (cached) + + * libelf-0.8.13.tar.gz (cached) + + * gcc-4.7.3.tar.bz2 (cached) + + * binutils-2.23.2.tar.bz2 (cached) + + * acpica-unix-20130626.tar.gz (cached) + +Downloaded tar balls ... \textcolor {green}{ok} + +Unpacking and patching ... + + * gmp-5.1.2.tar.bz2 + + * mpfr-3.1.2.tar.bz2 + + * mpc-1.0.1.tar.gz + + * libelf-0.8.13.tar.gz + + * gcc-4.7.3.tar.bz2 + + * binutils-2.23.2.tar.bz2 + + o binutils-2.23.2\_arv7a.patch + + o binutils-2.23.2\_no-bfd-doc.patch + + * acpica-unix-20130626.tar.gz + +Unpacked and patched ... \textcolor {green}{ok} + +Building GMP 5.1.2 ... \textcolor {green}{ok} + +Building MPFR 3.1.2 ... \textcolor {green}{ok} + +Building MPC 1.0.1 ... \textcolor {green}{ok} + +Building libelf 0.8.13 ... \textcolor {green}{ok} + +Building binutils 2.23.2 ... \textcolor {green}{ok} + +Building GCC 4.7.3 ... ok + +Skipping Expat (Python scripting not enabled) + +Skipping Python (Python scripting not enabled) + +Skipping GDB (GDB support not enabled) + +Building IASL 20130626 ... \textcolor {green}{ok} + +Cleaning up... \textcolor {green}{ok} + +\textcolor {green}{You can now run your i386-elf cross toolchain from /home/baozheng/x86/coreboot-gerrit/util/crossgcc/xgcc.} +} +If you are lucky, you can get toolchains located in util/crossgcc/xgcc. + +% +% Build Coreboot +% + +\section{Building Coreboot} +\subsection{Build main module of Coreboot} +{ \small +\begin{verbatim} +$ cd coreboot +$ make menuconfig +.config - coreboot v4.0-4895-gc5025a4-dirty Configuration ++------------------------ coreboot Configuration -------------------------+ +| Arrow keys navigate the menu. <Enter> selects submenus --->. | +| Highlighted letters are hotkeys. Pressing <Y> includes, <N> excludes, | +| <M> modularizes features. Press <Esc><Esc> to exit, <?> for Help, </> | +| for Search. Legend: [*] built-in [ ] excluded <M> module < > | +| +---------------------------------------------------------------------+ | +| | General setup ---> | | +| | Mainboard ---> | | +| | Architecture (x86) ---> | | +| | Chipset ---> | | +| | Devices ---> | | +| | VGA BIOS ---> | | +| | Display ---> | | +| | PXE ROM ---> | | +| | Generic Drivers ---> | | +| | Console ---> | | +| | [ ] Relocatable Modules | | +| | System tables ---> | | +| | Payload ---> | | +| | Debugging ---> | | +| | --- | | +| +----v(+)-------------------------------------------------------------+ | ++-------------------------------------------------------------------------+ +| <Select> < Exit > < Help > | ++------------------------------------------------------------------------- +\end{verbatim} +} +Select Mainboard -$>$ Mainboard Vendor -$>$ AMD + -$>$ Mainboard Model -$>$ Olive Hill + +Then save, exit and run make. + +{ \small +\begin{verbatim} +$ make +\end{verbatim} +} +The built image, coreboot.rom, is located at folder build. + +\section{Programming coreboot to flash memory} +The image resulting from a coreboot build can be directly programmed to +a flash device, either using an external flash programmers, e.g., Dediprog SF100, or by using the +Linux flash utility, flashrom. + + +\subsection{Add modules and payload} + +\subsubsection{VGA BIOS} +There is a big Chance that you need to get a VGA BIOS. +{ \small +\begin{verbatim} +.config - coreboot v4.0 Configuration +------------------------------------------------------------------------------ ++-------------------------------- VGA BIOS --------------------------------+ +| Arrow keys navigate the menu. <Enter> selects submenus --->. | +| Highlighted letters are hotkeys. Pressing <Y> includes, <N> excludes, | +| <M> modularizes features. Press <Esc><Esc> to exit, <?> for Help, </> | +| for Search. Legend: [*] built-in [ ] excluded <M> module < > module | +| +----------------------------------------------------------------------+ | +| | [*] Add a VGA BIOS image | | +| | (vgabios.bin) VGA BIOS path and filename | | +| | (1002,1306) VGA device PCI IDs | | +| | | | +| | | | +| | | | +| | | | +| | | | +| | | | +| +----------------------------------------------------------------------+ | ++--------------------------------------------------------------------------+ +| <Select> < Exit > < Help > | ++--------------------------------------------------------------------------+ +\end{verbatim} +} +Select VGA BIOS. ``The VGA device PCI IDs'' should be the same as your device. Get the +Option ROM from Vendor's website. + +\subsubsection{Payload} +coreboot in itself is "only" minimal code for initializing a mainboard +with peripherals. After the initialization, it jumps to a payload. + +Currently, SeaBIOS is the most widely used payload. The best way to integrate SeaBIOS +is setting it in menuconfig. +{ \small +\begin{verbatim} ++------------------------------- Payload ---------------------------------+ +| Arrow keys navigate the menu. <Enter> selects submenus --->. | +| Highlighted letters are hotkeys. Pressing <Y> includes, <N> excludes, | +| <M> modularizes features. Press <Esc><Esc> to exit, <?> for Help, </> | +| for Search. Legend: [*] built-in [ ] excluded <M> module < > module | +| +----------------------------------------------------------------------+ | +| | Add a payload (SeaBIOS) ---> | | +| | SeaBIOS version (1.7.2.1) ---> | | +| | [*] Use LZMA compression for payloads (NEW) | | +| | | | +| | | | +| | | | +| | | | +| | | | +| | | | +| +----------------------------------------------------------------------+ | ++--------------------------------------------------------------------------+ +| <Select> < Exit > < Help > | ++--------------------------------------------------------------------------+ +\end{verbatim} +The script in Makefile will automatically checkout, config, build the SeaBIOS source, +and integrat the binary into the final image. + +% +% Working with Git +% + +\section{Working with Git} +\subsection{Configuration of Git} +Inside the checkout you should install a commit-msg hook that adds a +Change-Id into commit messages, which uniquely identifies the logical +change in Gerrit even across multiple iterations of the commit. The +hook only needs to be installed once per clone, and installation can +be done with: +{ \small +\begin{verbatim} +$ cd coreboot +$ cp ./util/gitconfig/* .git/hooks +\end{verbatim} +} +configure your name and email in git. +{ \small +\begin{verbatim} +$ git config --global user.name "Your Name Comes Here" +$ git config --global user.email your.email@example.com' +\end{verbatim} +} +The name~\ref{user name} and email~\ref{Contact Information} should be the same the settings in gerrit. +Otherwise you can not push you code to community. + +Then run the following command once, to tell git that by default you +want to submit all commits in the currently checked-out branch for +review on gerrit: +{ \small +\begin{verbatim} +$ git config remote.origin.push HEAD:refs/for/master +\end{verbatim} +} + +The above configurations for git has been integrated into Makefile. You can run +{ \small +\begin{verbatim} +$ make gitconfig +\end{verbatim} +} + +\subsection{Work flow} + +It is recommended that you make a new branch when you start to work, not pushing changes to master. +{ \small +\begin{verbatim} +$ git checkout master -b mybranch +\end{verbatim} +} +After you have done your changes, run: +{ \small +\begin{verbatim} +$ git add file_need_to_submit.c +$ git commit -m "my first change." +\end{verbatim} +} + +% Does anyone have a better word to describe the phylosophy of spliting changes to patches? +You need to realize that the changes you have made should be well devided into +several commits. Each of them has one and only one meaning. You could use git rebase -i to +split, squash, remove, rewrite you comment. + +Here is an example of a well-formatted commit message: + +{ \small +\begin{verbatim} +examplecomponent: Refactor duplicated setup into a function + +Setting up the demo device correctly requires the exact same register +values to be written into each of the PCI device functions. Moving the +writes into a function allows also otherexamplecomponent to use them. + +Signed-off-by: Joe Hacker joe@hacker.email +\end{verbatim} +} + +Then you can push the code. +{ \small +\begin{verbatim} +$ git push +\end{verbatim} +} + +You can go to the ~\ref{sec:gerrit} gerrit to see if your changes is successfully pushed. + +Often it might happen that the patch you sent for approval is not good +enough from the first attempt. Gerrit and git make it easy to track +patch evolution during the review process until patches meet our +quality standards and are ready for approval. + +You can easily modify a patch sent to gerrit by you or even by someone +else. Just apply it locally using one of the possible ways to do it, +make a new local commit that fixes the issues reported by the +reviewers, then rebase the change by preserving the same Change-ID. We +recommend you to use the git rebase command in interactive mode, + +Once your patch gets a +2 comment, your patch can be merged (cherry-pick, actually) to origin/master. + +% +% Working with Gerrit +% + +\section{Working with Gerrit} +\label{sec:gerrit} +If you are a coreboot user, not planning to contribute, you can skip this section. +\subsection{Get gerrit account} +You need to get an OpenID first. Currently Google account give you an OpenID. It means, if you have a gmail account, you have an OpenID. You can try to signed in. +click \url{http://review.coreboot.org%7D + +%\includegraphics[width=6.00in,height=1.00in]{gerrit_signin.png} +{ \small +\begin{verbatim} ++-----------------------------------------------------------+ +|All Projects Documentation Register Sign In | +|Open Merged Abandoned | +|Search for status:open | ++-----------------------------------------------------------+ +|Subject Status Owner Project Branch Updated CR V | +|cpu: Rename.. Alexandru coreboot master 1:20 PM +1 | +|cpu: Only a.. Alexandru coreboot master 1:17 PM X | +|arch/x86: D.. Alexandru coreboot master 1:09 PM | +| | +| Next -> | +|Press '?' to view keyboard shortcuts | Powered by Gerrit | ++-----------------------------------------------------------+ +\end{verbatim} +} +Click ``Sign In'', You will get + +%\includegraphics[width=6.00in,height=4.00in]{openid.png} + +You will be redirected to Google to get logging in. + +% \includegraphics[width=6.00in,height=1.50in]{login.png} +{ \small +\begin{verbatim} +Sign In to Gerrit Code Review at review.coreboot.org ++--------------------------------------------------+ ++--------------------------------------------------+ +[] Remember me +Sign In Cancel +Sign in with a Google Account +Sign in with a Yahoo! ID +What is OpenID? + +OpenID provides secure single-sign-on, without revealing your passwords to this website. + +There are many OpenID providers available. You may already be member of one! + +Get OpenID +\end{verbatim} +} + +\subsection{Configure account} +Click the dropdown button near the user name and click ``Settings'' + +% \includegraphics[width=6.00in,height=4.00in]{settings} +% \epsfig{figure=keystroke_left} +% \epstopdf {file=settings.eps} +% \epsfig{file=settings.eps} + +\label{user name} In ``profile'' section, type the user name for git. This probably can be changed only once. +{ \small +\begin{verbatim} +Profile Username zbao +Preferences Full Name Zheng Bao +Watched Projects Email Address zheng.bao@amd.com +Contact Information Registered Jun 28, 2011 4:33 PM +SSH Public Keys Account ID 1000034 +HTTP Password +Identities +Groups +\end{verbatim} +} + +\label{Contact Information} In ``Contact Information'', enter you full name and your Email, which should be configured in your .gitconfig +{ \small +\begin{verbatim} + Full Name __________________________________ +Preferred Email ______________ Registered Email + +Save Changes +\end{verbatim} +} + +In ``SSH Public Keys'' section, upload your public key. +{ \small +\begin{verbatim} +Status Algorithm Key Comment + +Delete +Add SSH Public Key + > How to Generate an SSH Key ++--------------------------+ +| | +| | +| | +| | +| | +| | +| | +| | +| | ++--------------------------+ +clear Add Close +\end{verbatim} +} + +Click ``Add Key ...'' +Go back to you linux command line and type: +{ \small +\begin{verbatim} +$ ssh-keygen +Generating public/private rsa key pair. +Enter file in which to save the key (/home/zhengbao/.ssh/id_rsa): +Enter passphrase (empty for no passphrase): +Enter same passphrase again: +Your identification has been saved in /home/zhengbao/.ssh/id_rsa. +Your public key has been saved in /home/zhengbao/.ssh/id_rsa.pub. +The key fingerprint is: +xx:xx:xx:xx:xx:xx:xx:xx:xx:xx:xx:xx:xx:xx:xx:xx zhengb@host.domain +The key's randomart image is: ++--[ RSA 2048]----+ +| | +| | +| | +| | +| | +| | +| | +| | +| | ++-----------------+ +\end{verbatim} +} +The data in ~/.ssh/id_rsa.pub is your public key. Copy them to the box in the page of ``SSH Public Keys'' and click add. + +In ``HTTP Password'' section, click button ``Generate Password''. You will get the password for http checkout. +{ \small +\begin{verbatim} +Username XXX +Password XXXXXXXXXXXX + +Generate Password Clear Password + +\end{verbatim} +} + +\subsection{Reviewing Changes} +For each listed changes in Gerrit, you can review, comment, evaluate, +cherry-pick, and even re-submit them. For you own patches, only you can +abandon them. Click in the file and commit message, you can add in-line comment. + +% +% 14 Glossary +% + +\section{Glossary} +\begin{itemize} +\item payload + +coreboot only cares about low level machine initialization, but also has +very simple mechanisms to boot a file either from FLASHROM or IDE. That +file, possibly a Linux Kernel, a boot loader or Etherboot, are called +payload, since it is the first software executed that does not cope with +pure initialization. + +\item flash device + +Flash devices are commonly used in all different computers since unlike +ROMs they can be electronically erased and reprogrammed. + +\item Gerrit + +Gerrit is a web based code review system, facilitating online code +reviews for projects using the Git version control system. + +Gerrit makes reviews easier by showing changes in a side-by-side +display, and allowing inline comments to be added by any reviewer. + +Gerrit simplifies Git based project maintainership by permitting any +authorized user to submit changes to the master Git repository, rather +than requiring all approved changes to be merged in by hand by the +project maintainer. This functionality enables a more centralized +usage of Git. + +\end{itemize} + +\newpage + +% +% 14 Bibliography +% + +\section{Bibliography} +\subsection{Additional Papers on coreboot} + +\begin{itemize} + \item + \textit{\url{http://www.coreboot.org/Documentation%7D%7D +\end{itemize} + +\subsection {Links} + +\begin{itemize} + \item Etherboot: \textit{\url{http://www.etherboot.org/%7D%7D + \item OpenBIOS: \textit{\url{http://www.openbios.org/%7D%7D + \item Flashrom: \textit{\url{http://www.flashrom.org/%7D%7D + \item Seabios: \textit{\url{http://www.seabios.org/%7D%7D +\end{itemize} + + +\end{document} diff --git a/Documentation/backup-docs/old/Doxyfile.coreboot b/Documentation/backup-docs/old/Doxyfile.coreboot new file mode 100644 index 0000000..e6c06fe --- /dev/null +++ b/Documentation/backup-docs/old/Doxyfile.coreboot @@ -0,0 +1,1639 @@ +# Doxyfile 1.7.1 + +# This file describes the settings to be used by the documentation system +# doxygen (www.doxygen.org) for a project +# +# All text after a hash (#) is considered a comment and will be ignored +# The format is: +# TAG = value [value, ...] +# For lists items can also be appended using: +# TAG += value [value, ...] +# Values that contain spaces should be placed between quotes (" ") + +#--------------------------------------------------------------------------- +# Project related configuration options +#--------------------------------------------------------------------------- + +# This tag specifies the encoding used for all characters in the config file +# that follow. The default is UTF-8 which is also the encoding used for all +# text before the first occurrence of this tag. Doxygen uses libiconv (or the +# iconv built into libc) for the transcoding. See +# http://www.gnu.org/software/libiconv for the list of possible encodings. + +DOXYFILE_ENCODING = UTF-8 + +# The PROJECT_NAME tag is a single word (or a sequence of words surrounded +# by quotes) that should identify the project. + +PROJECT_NAME = coreboot + +# The PROJECT_NUMBER tag can be used to enter a project or revision number. +# This could be handy for archiving the generated documentation or +# if some version control system is used. + +PROJECT_NUMBER = + +# The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute) +# base path where the generated documentation will be put. +# If a relative path is entered, it will be relative to the location +# where doxygen was started. If left blank the current directory will be used. + +OUTPUT_DIRECTORY = doxygen + +# If the CREATE_SUBDIRS tag is set to YES, then doxygen will create +# 4096 sub-directories (in 2 levels) under the output directory of each output +# format and will distribute the generated files over these directories. +# Enabling this option can be useful when feeding doxygen a huge amount of +# source files, where putting all generated files in the same directory would +# otherwise cause performance problems for the file system. + +CREATE_SUBDIRS = NO + +# The OUTPUT_LANGUAGE tag is used to specify the language in which all +# documentation generated by doxygen is written. Doxygen will use this +# information to generate all constant output in the proper language. +# The default language is English, other supported languages are: +# Afrikaans, Arabic, Brazilian, Catalan, Chinese, Chinese-Traditional, +# Croatian, Czech, Danish, Dutch, Esperanto, Farsi, Finnish, French, German, +# Greek, Hungarian, Italian, Japanese, Japanese-en (Japanese with English +# messages), Korean, Korean-en, Lithuanian, Norwegian, Macedonian, Persian, +# Polish, Portuguese, Romanian, Russian, Serbian, Serbian-Cyrilic, Slovak, +# Slovene, Spanish, Swedish, Ukrainian, and Vietnamese. + +OUTPUT_LANGUAGE = English + +# If the BRIEF_MEMBER_DESC tag is set to YES (the default) Doxygen will +# include brief member descriptions after the members that are listed in +# the file and class documentation (similar to JavaDoc). +# Set to NO to disable this. + +BRIEF_MEMBER_DESC = YES + +# If the REPEAT_BRIEF tag is set to YES (the default) Doxygen will prepend +# the brief description of a member or function before the detailed description. +# Note: if both HIDE_UNDOC_MEMBERS and BRIEF_MEMBER_DESC are set to NO, the +# brief descriptions will be completely suppressed. + +REPEAT_BRIEF = YES + +# This tag implements a quasi-intelligent brief description abbreviator +# that is used to form the text in various listings. Each string +# in this list, if found as the leading text of the brief description, will be +# stripped from the text and the result after processing the whole list, is +# used as the annotated text. Otherwise, the brief description is used as-is. +# If left blank, the following values are used ("$name" is automatically +# replaced with the name of the entity): "The $name class" "The $name widget" +# "The $name file" "is" "provides" "specifies" "contains" +# "represents" "a" "an" "the" + +ABBREVIATE_BRIEF = + +# If the ALWAYS_DETAILED_SEC and REPEAT_BRIEF tags are both set to YES then +# Doxygen will generate a detailed section even if there is only a brief +# description. + +ALWAYS_DETAILED_SEC = YES + +# If the INLINE_INHERITED_MEMB tag is set to YES, doxygen will show all +# inherited members of a class in the documentation of that class as if those +# members were ordinary class members. Constructors, destructors and assignment +# operators of the base classes will not be shown. + +INLINE_INHERITED_MEMB = NO + +# If the FULL_PATH_NAMES tag is set to YES then Doxygen will prepend the full +# path before files name in the file list and in the header files. If set +# to NO the shortest path that makes the file name unique will be used. + +FULL_PATH_NAMES = YES + +# If the FULL_PATH_NAMES tag is set to YES then the STRIP_FROM_PATH tag +# can be used to strip a user-defined part of the path. Stripping is +# only done if one of the specified strings matches the left-hand part of +# the path. The tag can be used to show relative paths in the file list. +# If left blank the directory from which doxygen is run is used as the +# path to strip. + +STRIP_FROM_PATH = + +# The STRIP_FROM_INC_PATH tag can be used to strip a user-defined part of +# the path mentioned in the documentation of a class, which tells +# the reader which header file to include in order to use a class. +# If left blank only the name of the header file containing the class +# definition is used. Otherwise one should specify the include paths that +# are normally passed to the compiler using the -I flag. + +STRIP_FROM_INC_PATH = + +# If the SHORT_NAMES tag is set to YES, doxygen will generate much shorter +# (but less readable) file names. This can be useful is your file systems +# doesn't support long names like on DOS, Mac, or CD-ROM. + +SHORT_NAMES = NO + +# If the JAVADOC_AUTOBRIEF tag is set to YES then Doxygen +# will interpret the first line (until the first dot) of a JavaDoc-style +# comment as the brief description. If set to NO, the JavaDoc +# comments will behave just like regular Qt-style comments +# (thus requiring an explicit @brief command for a brief description.) + +JAVADOC_AUTOBRIEF = YES + +# If the QT_AUTOBRIEF tag is set to YES then Doxygen will +# interpret the first line (until the first dot) of a Qt-style +# comment as the brief description. If set to NO, the comments +# will behave just like regular Qt-style comments (thus requiring +# an explicit \brief command for a brief description.) + +QT_AUTOBRIEF = NO + +# The MULTILINE_CPP_IS_BRIEF tag can be set to YES to make Doxygen +# treat a multi-line C++ special comment block (i.e. a block of //! or /// +# comments) as a brief description. This used to be the default behaviour. +# The new default is to treat a multi-line C++ comment block as a detailed +# description. Set this tag to YES if you prefer the old behaviour instead. + +MULTILINE_CPP_IS_BRIEF = NO + +# If the INHERIT_DOCS tag is set to YES (the default) then an undocumented +# member inherits the documentation from any documented member that it +# re-implements. + +INHERIT_DOCS = YES + +# If the SEPARATE_MEMBER_PAGES tag is set to YES, then doxygen will produce +# a new page for each member. If set to NO, the documentation of a member will +# be part of the file/class/namespace that contains it. + +SEPARATE_MEMBER_PAGES = NO + +# The TAB_SIZE tag can be used to set the number of spaces in a tab. +# Doxygen uses this value to replace tabs by spaces in code fragments. + +TAB_SIZE = 8 + +# This tag can be used to specify a number of aliases that acts +# as commands in the documentation. An alias has the form "name=value". +# For example adding "sideeffect=\par Side Effects:\n" will allow you to +# put the command \sideeffect (or @sideeffect) in the documentation, which +# will result in a user-defined paragraph with heading "Side Effects:". +# You can put \n's in the value part of an alias to insert newlines. + +ALIASES = + +# Set the OPTIMIZE_OUTPUT_FOR_C tag to YES if your project consists of C +# sources only. Doxygen will then generate output that is more tailored for C. +# For instance, some of the names that are used will be different. The list +# of all members will be omitted, etc. + +OPTIMIZE_OUTPUT_FOR_C = YES + +# Set the OPTIMIZE_OUTPUT_JAVA tag to YES if your project consists of Java +# sources only. Doxygen will then generate output that is more tailored for +# Java. For instance, namespaces will be presented as packages, qualified +# scopes will look different, etc. + +OPTIMIZE_OUTPUT_JAVA = NO + +# Set the OPTIMIZE_FOR_FORTRAN tag to YES if your project consists of Fortran +# sources only. Doxygen will then generate output that is more tailored for +# Fortran. + +OPTIMIZE_FOR_FORTRAN = NO + +# Set the OPTIMIZE_OUTPUT_VHDL tag to YES if your project consists of VHDL +# sources. Doxygen will then generate output that is tailored for +# VHDL. + +OPTIMIZE_OUTPUT_VHDL = NO + +# Doxygen selects the parser to use depending on the extension of the files it +# parses. With this tag you can assign which parser to use for a given extension. +# Doxygen has a built-in mapping, but you can override or extend it using this +# tag. The format is ext=language, where ext is a file extension, and language +# is one of the parsers supported by doxygen: IDL, Java, Javascript, CSharp, C, +# C++, D, PHP, Objective-C, Python, Fortran, VHDL, C, C++. For instance to make +# doxygen treat .inc files as Fortran files (default is PHP), and .f files as C +# (default is Fortran), use: inc=Fortran f=C. Note that for custom extensions +# you also need to set FILE_PATTERNS otherwise the files are not read by doxygen. + +EXTENSION_MAPPING = + +# If you use STL classes (i.e. std::string, std::vector, etc.) but do not want +# to include (a tag file for) the STL sources as input, then you should +# set this tag to YES in order to let doxygen match functions declarations and +# definitions whose arguments contain STL classes (e.g. func(std::string); v.s. +# func(std::string) {}). This also make the inheritance and collaboration +# diagrams that involve STL classes more complete and accurate. + +BUILTIN_STL_SUPPORT = NO + +# If you use Microsoft's C++/CLI language, you should set this option to YES to +# enable parsing support. + +CPP_CLI_SUPPORT = NO + +# Set the SIP_SUPPORT tag to YES if your project consists of sip sources only. +# Doxygen will parse them like normal C++ but will assume all classes use public +# instead of private inheritance when no explicit protection keyword is present. + +SIP_SUPPORT = NO + +# For Microsoft's IDL there are propget and propput attributes to indicate getter +# and setter methods for a property. Setting this option to YES (the default) +# will make doxygen to replace the get and set methods by a property in the +# documentation. This will only work if the methods are indeed getting or +# setting a simple type. If this is not the case, or you want to show the +# methods anyway, you should set this option to NO. + +IDL_PROPERTY_SUPPORT = YES + +# If member grouping is used in the documentation and the DISTRIBUTE_GROUP_DOC +# tag is set to YES, then doxygen will reuse the documentation of the first +# member in the group (if any) for the other members of the group. By default +# all members of a group must be documented explicitly. + +DISTRIBUTE_GROUP_DOC = NO + +# Set the SUBGROUPING tag to YES (the default) to allow class member groups of +# the same type (for instance a group of public functions) to be put as a +# subgroup of that type (e.g. under the Public Functions section). Set it to +# NO to prevent subgrouping. Alternatively, this can be done per class using +# the \nosubgrouping command. + +SUBGROUPING = YES + +# When TYPEDEF_HIDES_STRUCT is enabled, a typedef of a struct, union, or enum +# is documented as struct, union, or enum with the name of the typedef. So +# typedef struct TypeS {} TypeT, will appear in the documentation as a struct +# with name TypeT. When disabled the typedef will appear as a member of a file, +# namespace, or class. And the struct will be named TypeS. This can typically +# be useful for C code in case the coding convention dictates that all compound +# types are typedef'ed and only the typedef is referenced, never the tag name. + +TYPEDEF_HIDES_STRUCT = NO + +# The SYMBOL_CACHE_SIZE determines the size of the internal cache use to +# determine which symbols to keep in memory and which to flush to disk. +# When the cache is full, less often used symbols will be written to disk. +# For small to medium size projects (<1000 input files) the default value is +# probably good enough. For larger projects a too small cache size can cause +# doxygen to be busy swapping symbols to and from disk most of the time +# causing a significant performance penality. +# If the system has enough physical memory increasing the cache will improve the +# performance by keeping more symbols in memory. Note that the value works on +# a logarithmic scale so increasing the size by one will rougly double the +# memory usage. The cache size is given by this formula: +# 2^(16+SYMBOL_CACHE_SIZE). The valid range is 0..9, the default is 0, +# corresponding to a cache size of 2^16 = 65536 symbols + +SYMBOL_CACHE_SIZE = 0 + +#--------------------------------------------------------------------------- +# Build related configuration options +#--------------------------------------------------------------------------- + +# If the EXTRACT_ALL tag is set to YES doxygen will assume all entities in +# documentation are documented, even if no documentation was available. +# Private class members and static file members will be hidden unless +# the EXTRACT_PRIVATE and EXTRACT_STATIC tags are set to YES + +EXTRACT_ALL = YES + +# If the EXTRACT_PRIVATE tag is set to YES all private members of a class +# will be included in the documentation. + +EXTRACT_PRIVATE = NO + +# If the EXTRACT_STATIC tag is set to YES all static members of a file +# will be included in the documentation. + +EXTRACT_STATIC = YES + +# If the EXTRACT_LOCAL_CLASSES tag is set to YES classes (and structs) +# defined locally in source files will be included in the documentation. +# If set to NO only classes defined in header files are included. + +EXTRACT_LOCAL_CLASSES = YES + +# This flag is only useful for Objective-C code. When set to YES local +# methods, which are defined in the implementation section but not in +# the interface are included in the documentation. +# If set to NO (the default) only methods in the interface are included. + +EXTRACT_LOCAL_METHODS = NO + +# If this flag is set to YES, the members of anonymous namespaces will be +# extracted and appear in the documentation as a namespace called +# 'anonymous_namespace{file}', where file will be replaced with the base +# name of the file that contains the anonymous namespace. By default +# anonymous namespace are hidden. + +EXTRACT_ANON_NSPACES = NO + +# If the HIDE_UNDOC_MEMBERS tag is set to YES, Doxygen will hide all +# undocumented members of documented classes, files or namespaces. +# If set to NO (the default) these members will be included in the +# various overviews, but no documentation section is generated. +# This option has no effect if EXTRACT_ALL is enabled. + +HIDE_UNDOC_MEMBERS = NO + +# If the HIDE_UNDOC_CLASSES tag is set to YES, Doxygen will hide all +# undocumented classes that are normally visible in the class hierarchy. +# If set to NO (the default) these classes will be included in the various +# overviews. This option has no effect if EXTRACT_ALL is enabled. + +HIDE_UNDOC_CLASSES = NO + +# If the HIDE_FRIEND_COMPOUNDS tag is set to YES, Doxygen will hide all +# friend (class|struct|union) declarations. +# If set to NO (the default) these declarations will be included in the +# documentation. + +HIDE_FRIEND_COMPOUNDS = NO + +# If the HIDE_IN_BODY_DOCS tag is set to YES, Doxygen will hide any +# documentation blocks found inside the body of a function. +# If set to NO (the default) these blocks will be appended to the +# function's detailed documentation block. + +HIDE_IN_BODY_DOCS = NO + +# The INTERNAL_DOCS tag determines if documentation +# that is typed after a \internal command is included. If the tag is set +# to NO (the default) then the documentation will be excluded. +# Set it to YES to include the internal documentation. + +INTERNAL_DOCS = NO + +# If the CASE_SENSE_NAMES tag is set to NO then Doxygen will only generate +# file names in lower-case letters. If set to YES upper-case letters are also +# allowed. This is useful if you have classes or files whose names only differ +# in case and if your file system supports case sensitive file names. Windows +# and Mac users are advised to set this option to NO. + +CASE_SENSE_NAMES = YES + +# If the HIDE_SCOPE_NAMES tag is set to NO (the default) then Doxygen +# will show members with their full class and namespace scopes in the +# documentation. If set to YES the scope will be hidden. + +HIDE_SCOPE_NAMES = NO + +# If the SHOW_INCLUDE_FILES tag is set to YES (the default) then Doxygen +# will put a list of the files that are included by a file in the documentation +# of that file. + +SHOW_INCLUDE_FILES = YES + +# If the FORCE_LOCAL_INCLUDES tag is set to YES then Doxygen +# will list include files with double quotes in the documentation +# rather than with sharp brackets. + +FORCE_LOCAL_INCLUDES = NO + +# If the INLINE_INFO tag is set to YES (the default) then a tag [inline] +# is inserted in the documentation for inline members. + +INLINE_INFO = YES + +# If the SORT_MEMBER_DOCS tag is set to YES (the default) then doxygen +# will sort the (detailed) documentation of file and class members +# alphabetically by member name. If set to NO the members will appear in +# declaration order. + +SORT_MEMBER_DOCS = YES + +# If the SORT_BRIEF_DOCS tag is set to YES then doxygen will sort the +# brief documentation of file, namespace and class members alphabetically +# by member name. If set to NO (the default) the members will appear in +# declaration order. + +SORT_BRIEF_DOCS = NO + +# If the SORT_MEMBERS_CTORS_1ST tag is set to YES then doxygen +# will sort the (brief and detailed) documentation of class members so that +# constructors and destructors are listed first. If set to NO (the default) +# the constructors will appear in the respective orders defined by +# SORT_MEMBER_DOCS and SORT_BRIEF_DOCS. +# This tag will be ignored for brief docs if SORT_BRIEF_DOCS is set to NO +# and ignored for detailed docs if SORT_MEMBER_DOCS is set to NO. + +SORT_MEMBERS_CTORS_1ST = NO + +# If the SORT_GROUP_NAMES tag is set to YES then doxygen will sort the +# hierarchy of group names into alphabetical order. If set to NO (the default) +# the group names will appear in their defined order. + +SORT_GROUP_NAMES = NO + +# If the SORT_BY_SCOPE_NAME tag is set to YES, the class list will be +# sorted by fully-qualified names, including namespaces. If set to +# NO (the default), the class list will be sorted only by class name, +# not including the namespace part. +# Note: This option is not very useful if HIDE_SCOPE_NAMES is set to YES. +# Note: This option applies only to the class list, not to the +# alphabetical list. + +SORT_BY_SCOPE_NAME = NO + +# The GENERATE_TODOLIST tag can be used to enable (YES) or +# disable (NO) the todo list. This list is created by putting \todo +# commands in the documentation. + +GENERATE_TODOLIST = YES + +# The GENERATE_TESTLIST tag can be used to enable (YES) or +# disable (NO) the test list. This list is created by putting \test +# commands in the documentation. + +GENERATE_TESTLIST = YES + +# The GENERATE_BUGLIST tag can be used to enable (YES) or +# disable (NO) the bug list. This list is created by putting \bug +# commands in the documentation. + +GENERATE_BUGLIST = YES + +# The GENERATE_DEPRECATEDLIST tag can be used to enable (YES) or +# disable (NO) the deprecated list. This list is created by putting +# \deprecated commands in the documentation. + +GENERATE_DEPRECATEDLIST= YES + +# The ENABLED_SECTIONS tag can be used to enable conditional +# documentation sections, marked by \if sectionname ... \endif. + +ENABLED_SECTIONS = + +# The MAX_INITIALIZER_LINES tag determines the maximum number of lines +# the initial value of a variable or define consists of for it to appear in +# the documentation. If the initializer consists of more lines than specified +# here it will be hidden. Use a value of 0 to hide initializers completely. +# The appearance of the initializer of individual variables and defines in the +# documentation can be controlled using \showinitializer or \hideinitializer +# command in the documentation regardless of this setting. + +MAX_INITIALIZER_LINES = 30 + +# Set the SHOW_USED_FILES tag to NO to disable the list of files generated +# at the bottom of the documentation of classes and structs. If set to YES the +# list will mention the files that were used to generate the documentation. + +SHOW_USED_FILES = YES + +# If the sources in your project are distributed over multiple directories +# then setting the SHOW_DIRECTORIES tag to YES will show the directory hierarchy +# in the documentation. The default is NO. + +SHOW_DIRECTORIES = YES + +# Set the SHOW_FILES tag to NO to disable the generation of the Files page. +# This will remove the Files entry from the Quick Index and from the +# Folder Tree View (if specified). The default is YES. + +SHOW_FILES = YES + +# Set the SHOW_NAMESPACES tag to NO to disable the generation of the +# Namespaces page. +# This will remove the Namespaces entry from the Quick Index +# and from the Folder Tree View (if specified). The default is YES. + +SHOW_NAMESPACES = YES + +# The FILE_VERSION_FILTER tag can be used to specify a program or script that +# doxygen should invoke to get the current version for each file (typically from +# the version control system). Doxygen will invoke the program by executing (via +# popen()) the command <command> <input-file>, where <command> is the value of +# the FILE_VERSION_FILTER tag, and <input-file> is the name of an input file +# provided by doxygen. Whatever the program writes to standard output +# is used as the file version. See the manual for examples. + +FILE_VERSION_FILTER = + +# The LAYOUT_FILE tag can be used to specify a layout file which will be parsed +# by doxygen. The layout file controls the global structure of the generated +# output files in an output format independent way. The create the layout file +# that represents doxygen's defaults, run doxygen with the -l option. +# You can optionally specify a file name after the option, if omitted +# DoxygenLayout.xml will be used as the name of the layout file. + +LAYOUT_FILE = + +#--------------------------------------------------------------------------- +# configuration options related to warning and progress messages +#--------------------------------------------------------------------------- + +# The QUIET tag can be used to turn on/off the messages that are generated +# by doxygen. Possible values are YES and NO. If left blank NO is used. + +QUIET = YES + +# The WARNINGS tag can be used to turn on/off the warning messages that are +# generated by doxygen. Possible values are YES and NO. If left blank +# NO is used. + +WARNINGS = YES + +# If WARN_IF_UNDOCUMENTED is set to YES, then doxygen will generate warnings +# for undocumented members. If EXTRACT_ALL is set to YES then this flag will +# automatically be disabled. + +WARN_IF_UNDOCUMENTED = YES + +# If WARN_IF_DOC_ERROR is set to YES, doxygen will generate warnings for +# potential errors in the documentation, such as not documenting some +# parameters in a documented function, or documenting parameters that +# don't exist or using markup commands wrongly. + +WARN_IF_DOC_ERROR = YES + +# This WARN_NO_PARAMDOC option can be abled to get warnings for +# functions that are documented, but have no documentation for their parameters +# or return value. If set to NO (the default) doxygen will only warn about +# wrong or incomplete parameter documentation, but not about the absence of +# documentation. + +WARN_NO_PARAMDOC = YES + +# The WARN_FORMAT tag determines the format of the warning messages that +# doxygen can produce. The string should contain the $file, $line, and $text +# tags, which will be replaced by the file and line number from which the +# warning originated and the warning text. Optionally the format may contain +# $version, which will be replaced by the version of the file (if it could +# be obtained via FILE_VERSION_FILTER) + +WARN_FORMAT = "$file:$line: $text" + +# The WARN_LOGFILE tag can be used to specify a file to which warning +# and error messages should be written. If left blank the output is written +# to stderr. + +WARN_LOGFILE = + +#--------------------------------------------------------------------------- +# configuration options related to the input files +#--------------------------------------------------------------------------- + +# The INPUT tag can be used to specify the files and/or directories that contain +# documented source files. You may enter file names like "myfile.cpp" or +# directories like "/usr/src/myproject". Separate the files or directories +# with spaces. + +INPUT = . + +# This tag can be used to specify the character encoding of the source files +# that doxygen parses. Internally doxygen uses the UTF-8 encoding, which is +# also the default input encoding. Doxygen uses libiconv (or the iconv built +# into libc) for the transcoding. See http://www.gnu.org/software/libiconv for +# the list of possible encodings. + +INPUT_ENCODING = UTF-8 + +# If the value of the INPUT tag contains directories, you can use the +# FILE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp +# and *.h) to filter out the source-files in the directories. If left +# blank the following patterns are tested: +# *.c *.cc *.cxx *.cpp *.c++ *.java *.ii *.ixx *.ipp *.i++ *.inl *.h *.hh *.hxx +# *.hpp *.h++ *.idl *.odl *.cs *.php *.php3 *.inc *.m *.mm *.py *.f90 + +FILE_PATTERNS = + +# The RECURSIVE tag can be used to turn specify whether or not subdirectories +# should be searched for input files as well. Possible values are YES and NO. +# If left blank NO is used. + +RECURSIVE = YES + +# The EXCLUDE tag can be used to specify files and/or directories that should +# excluded from the INPUT source files. This way you can easily exclude a +# subdirectory from a directory tree whose root is specified with the INPUT tag. + +EXCLUDE = util/romcc/tests \ + util/vgabios \ + util/abuild \ + util/kconfig \ + payloads + +# The EXCLUDE_SYMLINKS tag can be used select whether or not files or +# directories that are symbolic links (a Unix filesystem feature) are excluded +# from the input. + +EXCLUDE_SYMLINKS = NO + +# If the value of the INPUT tag contains directories, you can use the +# EXCLUDE_PATTERNS tag to specify one or more wildcard patterns to exclude +# certain files from those directories. Note that the wildcards are matched +# against the file with absolute path, so to exclude all test directories +# for example use the pattern */test/* + +EXCLUDE_PATTERNS = + +# The EXCLUDE_SYMBOLS tag can be used to specify one or more symbol names +# (namespaces, classes, functions, etc.) that should be excluded from the +# output. The symbol name can be a fully qualified name, a word, or if the +# wildcard * is used, a substring. Examples: ANamespace, AClass, +# AClass::ANamespace, ANamespace::*Test + +EXCLUDE_SYMBOLS = + +# The EXAMPLE_PATH tag can be used to specify one or more files or +# directories that contain example code fragments that are included (see +# the \include command). + +EXAMPLE_PATH = + +# If the value of the EXAMPLE_PATH tag contains directories, you can use the +# EXAMPLE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp +# and *.h) to filter out the source-files in the directories. If left +# blank all files are included. + +EXAMPLE_PATTERNS = + +# If the EXAMPLE_RECURSIVE tag is set to YES then subdirectories will be +# searched for input files to be used with the \include or \dontinclude +# commands irrespective of the value of the RECURSIVE tag. +# Possible values are YES and NO. If left blank NO is used. + +EXAMPLE_RECURSIVE = NO + +# The IMAGE_PATH tag can be used to specify one or more files or +# directories that contain image that are included in the documentation (see +# the \image command). + +IMAGE_PATH = + +# The INPUT_FILTER tag can be used to specify a program that doxygen should +# invoke to filter for each input file. Doxygen will invoke the filter program +# by executing (via popen()) the command <filter> <input-file>, where <filter> +# is the value of the INPUT_FILTER tag, and <input-file> is the name of an +# input file. Doxygen will then use the output that the filter program writes +# to standard output. +# If FILTER_PATTERNS is specified, this tag will be +# ignored. + +INPUT_FILTER = + +# The FILTER_PATTERNS tag can be used to specify filters on a per file pattern +# basis. +# Doxygen will compare the file name with each pattern and apply the +# filter if there is a match. +# The filters are a list of the form: +# pattern=filter (like *.cpp=my_cpp_filter). See INPUT_FILTER for further +# info on how filters are used. If FILTER_PATTERNS is empty, INPUT_FILTER +# is applied to all files. + +FILTER_PATTERNS = + +# If the FILTER_SOURCE_FILES tag is set to YES, the input filter (if set using +# INPUT_FILTER) will be used to filter the input files when producing source +# files to browse (i.e. when SOURCE_BROWSER is set to YES). + +FILTER_SOURCE_FILES = NO + +#--------------------------------------------------------------------------- +# configuration options related to source browsing +#--------------------------------------------------------------------------- + +# If the SOURCE_BROWSER tag is set to YES then a list of source files will +# be generated. Documented entities will be cross-referenced with these sources. +# Note: To get rid of all source code in the generated output, make sure also +# VERBATIM_HEADERS is set to NO. + +SOURCE_BROWSER = YES + +# Setting the INLINE_SOURCES tag to YES will include the body +# of functions and classes directly in the documentation. + +INLINE_SOURCES = NO + +# Setting the STRIP_CODE_COMMENTS tag to YES (the default) will instruct +# doxygen to hide any special comment blocks from generated source code +# fragments. Normal C and C++ comments will always remain visible. + +STRIP_CODE_COMMENTS = NO + +# If the REFERENCED_BY_RELATION tag is set to YES +# then for each documented function all documented +# functions referencing it will be listed. + +REFERENCED_BY_RELATION = YES + +# If the REFERENCES_RELATION tag is set to YES +# then for each documented function all documented entities +# called/used by that function will be listed. + +REFERENCES_RELATION = YES + +# If the REFERENCES_LINK_SOURCE tag is set to YES (the default) +# and SOURCE_BROWSER tag is set to YES, then the hyperlinks from +# functions in REFERENCES_RELATION and REFERENCED_BY_RELATION lists will +# link to the source code. +# Otherwise they will link to the documentation. + +REFERENCES_LINK_SOURCE = YES + +# If the USE_HTAGS tag is set to YES then the references to source code +# will point to the HTML generated by the htags(1) tool instead of doxygen +# built-in source browser. The htags tool is part of GNU's global source +# tagging system (see http://www.gnu.org/software/global/global.html). You +# will need version 4.8.6 or higher. + +USE_HTAGS = NO + +# If the VERBATIM_HEADERS tag is set to YES (the default) then Doxygen +# will generate a verbatim copy of the header file for each class for +# which an include is specified. Set to NO to disable this. + +VERBATIM_HEADERS = YES + +#--------------------------------------------------------------------------- +# configuration options related to the alphabetical class index +#--------------------------------------------------------------------------- + +# If the ALPHABETICAL_INDEX tag is set to YES, an alphabetical index +# of all compounds will be generated. Enable this if the project +# contains a lot of classes, structs, unions or interfaces. + +ALPHABETICAL_INDEX = YES + +# If the alphabetical index is enabled (see ALPHABETICAL_INDEX) then +# the COLS_IN_ALPHA_INDEX tag can be used to specify the number of columns +# in which this list will be split (can be a number in the range [1..20]) + +COLS_IN_ALPHA_INDEX = 5 + +# In case all classes in a project start with a common prefix, all +# classes will be put under the same header in the alphabetical index. +# The IGNORE_PREFIX tag can be used to specify one or more prefixes that +# should be ignored while generating the index headers. + +IGNORE_PREFIX = + +#--------------------------------------------------------------------------- +# configuration options related to the HTML output +#--------------------------------------------------------------------------- + +# If the GENERATE_HTML tag is set to YES (the default) Doxygen will +# generate HTML output. + +GENERATE_HTML = YES + +# The HTML_OUTPUT tag is used to specify where the HTML docs will be put. +# If a relative path is entered the value of OUTPUT_DIRECTORY will be +# put in front of it. If left blank `html' will be used as the default path. + +HTML_OUTPUT = html + +# The HTML_FILE_EXTENSION tag can be used to specify the file extension for +# each generated HTML page (for example: .htm,.php,.asp). If it is left blank +# doxygen will generate files with .html extension. + +HTML_FILE_EXTENSION = .html + +# The HTML_HEADER tag can be used to specify a personal HTML header for +# each generated HTML page. If it is left blank doxygen will generate a +# standard header. + +HTML_HEADER = + +# The HTML_FOOTER tag can be used to specify a personal HTML footer for +# each generated HTML page. If it is left blank doxygen will generate a +# standard footer. + +HTML_FOOTER = + +# If the HTML_FOOTER_DESCRIPTION tag is set to YES, Doxygen will +# add generated date, project name and doxygen version to HTML footer. + +HTML_FOOTER_DESCRIPTION= YES + +# The HTML_STYLESHEET tag can be used to specify a user-defined cascading +# style sheet that is used by each HTML page. It can be used to +# fine-tune the look of the HTML output. If the tag is left blank doxygen +# will generate a default style sheet. Note that doxygen will try to copy +# the style sheet file to the HTML output directory, so don't put your own +# stylesheet in the HTML output directory as well, or it will be erased! + +HTML_STYLESHEET = + +# The HTML_COLORSTYLE_HUE tag controls the color of the HTML output. +# Doxygen will adjust the colors in the stylesheet and background images +# according to this color. Hue is specified as an angle on a colorwheel, +# see http://en.wikipedia.org/wiki/Hue for more information. +# For instance the value 0 represents red, 60 is yellow, 120 is green, +# 180 is cyan, 240 is blue, 300 purple, and 360 is red again. +# The allowed range is 0 to 359. + +HTML_COLORSTYLE_HUE = 220 + +# The HTML_COLORSTYLE_SAT tag controls the purity (or saturation) of +# the colors in the HTML output. For a value of 0 the output will use +# grayscales only. A value of 255 will produce the most vivid colors. + +HTML_COLORSTYLE_SAT = 100 + +# The HTML_COLORSTYLE_GAMMA tag controls the gamma correction applied to +# the luminance component of the colors in the HTML output. Values below +# 100 gradually make the output lighter, whereas values above 100 make +# the output darker. The value divided by 100 is the actual gamma applied, +# so 80 represents a gamma of 0.8, The value 220 represents a gamma of 2.2, +# and 100 does not change the gamma. + +HTML_COLORSTYLE_GAMMA = 80 + +# If the HTML_TIMESTAMP tag is set to YES then the footer of each generated HTML +# page will contain the date and time when the page was generated. Setting +# this to NO can help when comparing the output of multiple runs. + +HTML_TIMESTAMP = NO + +# If the HTML_ALIGN_MEMBERS tag is set to YES, the members of classes, +# files or namespaces will be aligned in HTML using tables. If set to +# NO a bullet list will be used. + +HTML_ALIGN_MEMBERS = YES + +# If the HTML_DYNAMIC_SECTIONS tag is set to YES then the generated HTML +# documentation will contain sections that can be hidden and shown after the +# page has loaded. For this to work a browser that supports +# JavaScript and DHTML is required (for instance Mozilla 1.0+, Firefox +# Netscape 6.0+, Internet explorer 5.0+, Konqueror, or Safari). + +HTML_DYNAMIC_SECTIONS = NO + +# If the GENERATE_DOCSET tag is set to YES, additional index files +# will be generated that can be used as input for Apple's Xcode 3 +# integrated development environment, introduced with OSX 10.5 (Leopard). +# To create a documentation set, doxygen will generate a Makefile in the +# HTML output directory. Running make will produce the docset in that +# directory and running "make install" will install the docset in +# ~/Library/Developer/Shared/Documentation/DocSets so that Xcode will find +# it at startup. +# See http://developer.apple.com/tools/creatingdocsetswithdoxygen.html +# for more information. + +GENERATE_DOCSET = NO + +# When GENERATE_DOCSET tag is set to YES, this tag determines the name of the +# feed. A documentation feed provides an umbrella under which multiple +# documentation sets from a single provider (such as a company or product suite) +# can be grouped. + +DOCSET_FEEDNAME = "Doxygen documentation" + +# When GENERATE_DOCSET tag is set to YES, this tag specifies a string that +# should uniquely identify the documentation set bundle. This should be a +# reverse domain-name style string, e.g. com.mycompany.MyDocSet. Doxygen +# will append .docset to the name. + +DOCSET_BUNDLE_ID = org.doxygen.Project + +# When GENERATE_PUBLISHER_ID tag specifies a string that should uniquely identify +# the documentation publisher. This should be a reverse domain-name style +# string, e.g. com.mycompany.MyDocSet.documentation. + +DOCSET_PUBLISHER_ID = org.doxygen.Publisher + +# The GENERATE_PUBLISHER_NAME tag identifies the documentation publisher. + +DOCSET_PUBLISHER_NAME = Publisher + +# If the GENERATE_HTMLHELP tag is set to YES, additional index files +# will be generated that can be used as input for tools like the +# Microsoft HTML help workshop to generate a compiled HTML help file (.chm) +# of the generated HTML documentation. + +GENERATE_HTMLHELP = NO + +# If the GENERATE_HTMLHELP tag is set to YES, the CHM_FILE tag can +# be used to specify the file name of the resulting .chm file. You +# can add a path in front of the file if the result should not be +# written to the html output directory. + +CHM_FILE = + +# If the GENERATE_HTMLHELP tag is set to YES, the HHC_LOCATION tag can +# be used to specify the location (absolute path including file name) of +# the HTML help compiler (hhc.exe). If non-empty doxygen will try to run +# the HTML help compiler on the generated index.hhp. + +HHC_LOCATION = + +# If the GENERATE_HTMLHELP tag is set to YES, the GENERATE_CHI flag +# controls if a separate .chi index file is generated (YES) or that +# it should be included in the master .chm file (NO). + +GENERATE_CHI = NO + +# If the GENERATE_HTMLHELP tag is set to YES, the CHM_INDEX_ENCODING +# is used to encode HtmlHelp index (hhk), content (hhc) and project file +# content. + +CHM_INDEX_ENCODING = + +# If the GENERATE_HTMLHELP tag is set to YES, the BINARY_TOC flag +# controls whether a binary table of contents is generated (YES) or a +# normal table of contents (NO) in the .chm file. + +BINARY_TOC = NO + +# The TOC_EXPAND flag can be set to YES to add extra items for group members +# to the contents of the HTML help documentation and to the tree view. + +TOC_EXPAND = NO + +# If the GENERATE_QHP tag is set to YES and both QHP_NAMESPACE and +# QHP_VIRTUAL_FOLDER are set, an additional index file will be generated +# that can be used as input for Qt's qhelpgenerator to generate a +# Qt Compressed Help (.qch) of the generated HTML documentation. + +GENERATE_QHP = NO + +# If the QHG_LOCATION tag is specified, the QCH_FILE tag can +# be used to specify the file name of the resulting .qch file. +# The path specified is relative to the HTML output folder. + +QCH_FILE = + +# The QHP_NAMESPACE tag specifies the namespace to use when generating +# Qt Help Project output. For more information please see +# http://doc.trolltech.com/qthelpproject.html#namespace + +QHP_NAMESPACE = org.doxygen.Project + +# The QHP_VIRTUAL_FOLDER tag specifies the namespace to use when generating +# Qt Help Project output. For more information please see +# http://doc.trolltech.com/qthelpproject.html#virtual-folders + +QHP_VIRTUAL_FOLDER = doc + +# If QHP_CUST_FILTER_NAME is set, it specifies the name of a custom filter to +# add. For more information please see +# http://doc.trolltech.com/qthelpproject.html#custom-filters + +QHP_CUST_FILTER_NAME = + +# The QHP_CUST_FILT_ATTRS tag specifies the list of the attributes of the +# custom filter to add. For more information please see +# <a href="http://doc.trolltech.com/qthelpproject.html#custom-filters"> +# Qt Help Project / Custom Filters</a>. + +QHP_CUST_FILTER_ATTRS = + +# The QHP_SECT_FILTER_ATTRS tag specifies the list of the attributes this +# project's +# filter section matches. +# <a href="http://doc.trolltech.com/qthelpproject.html#filter-attributes"> +# Qt Help Project / Filter Attributes</a>. + +QHP_SECT_FILTER_ATTRS = + +# If the GENERATE_QHP tag is set to YES, the QHG_LOCATION tag can +# be used to specify the location of Qt's qhelpgenerator. +# If non-empty doxygen will try to run qhelpgenerator on the generated +# .qhp file. + +QHG_LOCATION = + +# If the GENERATE_ECLIPSEHELP tag is set to YES, additional index files +# will be generated, which together with the HTML files, form an Eclipse help +# plugin. To install this plugin and make it available under the help contents +# menu in Eclipse, the contents of the directory containing the HTML and XML +# files needs to be copied into the plugins directory of eclipse. The name of +# the directory within the plugins directory should be the same as +# the ECLIPSE_DOC_ID value. After copying Eclipse needs to be restarted before +# the help appears. + +GENERATE_ECLIPSEHELP = NO + +# A unique identifier for the eclipse help plugin. When installing the plugin +# the directory name containing the HTML and XML files should also have +# this name. + +ECLIPSE_DOC_ID = org.doxygen.Project + +# The DISABLE_INDEX tag can be used to turn on/off the condensed index at +# top of each HTML page. The value NO (the default) enables the index and +# the value YES disables it. + +DISABLE_INDEX = NO + +# This tag can be used to set the number of enum values (range [1..20]) +# that doxygen will group on one line in the generated HTML documentation. + +ENUM_VALUES_PER_LINE = 4 + +# The GENERATE_TREEVIEW tag is used to specify whether a tree-like index +# structure should be generated to display hierarchical information. +# If the tag value is set to YES, a side panel will be generated +# containing a tree-like index structure (just like the one that +# is generated for HTML Help). For this to work a browser that supports +# JavaScript, DHTML, CSS and frames is required (i.e. any modern browser). +# Windows users are probably better off using the HTML help feature. + +GENERATE_TREEVIEW = YES + +# By enabling USE_INLINE_TREES, doxygen will generate the Groups, Directories, +# and Class Hierarchy pages using a tree view instead of an ordered list. + +USE_INLINE_TREES = YES + +# If the treeview is enabled (see GENERATE_TREEVIEW) then this tag can be +# used to set the initial width (in pixels) of the frame in which the tree +# is shown. + +TREEVIEW_WIDTH = 250 + +# When the EXT_LINKS_IN_WINDOW option is set to YES doxygen will open +# links to external symbols imported via tag files in a separate window. + +EXT_LINKS_IN_WINDOW = NO + +# Use this tag to change the font size of Latex formulas included +# as images in the HTML documentation. The default is 10. Note that +# when you change the font size after a successful doxygen run you need +# to manually remove any form_*.png images from the HTML output directory +# to force them to be regenerated. + +FORMULA_FONTSIZE = 10 + +# Use the FORMULA_TRANPARENT tag to determine whether or not the images +# generated for formulas are transparent PNGs. Transparent PNGs are +# not supported properly for IE 6.0, but are supported on all modern browsers. +# Note that when changing this option you need to delete any form_*.png files +# in the HTML output before the changes have effect. + +FORMULA_TRANSPARENT = YES + +# When the SEARCHENGINE tag is enabled doxygen will generate a search box +# for the HTML output. The underlying search engine uses javascript +# and DHTML and should work on any modern browser. Note that when using +# HTML help (GENERATE_HTMLHELP), Qt help (GENERATE_QHP), or docsets +# (GENERATE_DOCSET) there is already a search function so this one should +# typically be disabled. For large projects the javascript based search engine +# can be slow, then enabling SERVER_BASED_SEARCH may provide a better solution. + +SEARCHENGINE = YES + +# When the SERVER_BASED_SEARCH tag is enabled the search engine will be +# implemented using a PHP enabled web server instead of at the web client +# using Javascript. Doxygen will generate the search PHP script and index +# file to put on the web server. The advantage of the server +# based approach is that it scales better to large projects and allows +# full text search. The disadvances is that it is more difficult to setup +# and does not have live searching capabilities. + +SERVER_BASED_SEARCH = NO + +#--------------------------------------------------------------------------- +# configuration options related to the LaTeX output +#--------------------------------------------------------------------------- + +# If the GENERATE_LATEX tag is set to YES (the default) Doxygen will +# generate Latex output. + +GENERATE_LATEX = NO + +# The LATEX_OUTPUT tag is used to specify where the LaTeX docs will be put. +# If a relative path is entered the value of OUTPUT_DIRECTORY will be +# put in front of it. If left blank `latex' will be used as the default path. + +LATEX_OUTPUT = latex + +# The LATEX_CMD_NAME tag can be used to specify the LaTeX command name to be +# invoked. If left blank `latex' will be used as the default command name. +# Note that when enabling USE_PDFLATEX this option is only used for +# generating bitmaps for formulas in the HTML output, but not in the +# Makefile that is written to the output directory. + +LATEX_CMD_NAME = latex + +# The MAKEINDEX_CMD_NAME tag can be used to specify the command name to +# generate index for LaTeX. If left blank `makeindex' will be used as the +# default command name. + +MAKEINDEX_CMD_NAME = makeindex + +# If the COMPACT_LATEX tag is set to YES Doxygen generates more compact +# LaTeX documents. This may be useful for small projects and may help to +# save some trees in general. + +COMPACT_LATEX = NO + +# The PAPER_TYPE tag can be used to set the paper type that is used +# by the printer. Possible values are: a4, a4wide, letter, legal and +# executive. If left blank a4wide will be used. + +PAPER_TYPE = a4wide + +# The EXTRA_PACKAGES tag can be to specify one or more names of LaTeX +# packages that should be included in the LaTeX output. + +EXTRA_PACKAGES = + +# The LATEX_HEADER tag can be used to specify a personal LaTeX header for +# the generated latex document. The header should contain everything until +# the first chapter. If it is left blank doxygen will generate a +# standard header. Notice: only use this tag if you know what you are doing! + +LATEX_HEADER = + +# If the PDF_HYPERLINKS tag is set to YES, the LaTeX that is generated +# is prepared for conversion to pdf (using ps2pdf). The pdf file will +# contain links (just like the HTML output) instead of page references +# This makes the output suitable for online browsing using a pdf viewer. + +PDF_HYPERLINKS = NO + +# If the USE_PDFLATEX tag is set to YES, pdflatex will be used instead of +# plain latex in the generated Makefile. Set this option to YES to get a +# higher quality PDF documentation. + +USE_PDFLATEX = NO + +# If the LATEX_BATCHMODE tag is set to YES, doxygen will add the \batchmode. +# command to the generated LaTeX files. This will instruct LaTeX to keep +# running if errors occur, instead of asking the user for help. +# This option is also used when generating formulas in HTML. + +LATEX_BATCHMODE = NO + +# If LATEX_HIDE_INDICES is set to YES then doxygen will not +# include the index chapters (such as File Index, Compound Index, etc.) +# in the output. + +LATEX_HIDE_INDICES = NO + +# If LATEX_SOURCE_CODE is set to YES then doxygen will include +# source code with syntax highlighting in the LaTeX output. +# Note that which sources are shown also depends on other settings +# such as SOURCE_BROWSER. + +LATEX_SOURCE_CODE = NO + +#--------------------------------------------------------------------------- +# configuration options related to the RTF output +#--------------------------------------------------------------------------- + +# If the GENERATE_RTF tag is set to YES Doxygen will generate RTF output +# The RTF output is optimized for Word 97 and may not look very pretty with +# other RTF readers or editors. + +GENERATE_RTF = NO + +# The RTF_OUTPUT tag is used to specify where the RTF docs will be put. +# If a relative path is entered the value of OUTPUT_DIRECTORY will be +# put in front of it. If left blank `rtf' will be used as the default path. + +RTF_OUTPUT = rtf + +# If the COMPACT_RTF tag is set to YES Doxygen generates more compact +# RTF documents. This may be useful for small projects and may help to +# save some trees in general. + +COMPACT_RTF = NO + +# If the RTF_HYPERLINKS tag is set to YES, the RTF that is generated +# will contain hyperlink fields. The RTF file will +# contain links (just like the HTML output) instead of page references. +# This makes the output suitable for online browsing using WORD or other +# programs which support those fields. +# Note: wordpad (write) and others do not support links. + +RTF_HYPERLINKS = NO + +# Load stylesheet definitions from file. Syntax is similar to doxygen's +# config file, i.e. a series of assignments. You only have to provide +# replacements, missing definitions are set to their default value. + +RTF_STYLESHEET_FILE = + +# Set optional variables used in the generation of an rtf document. +# Syntax is similar to doxygen's config file. + +RTF_EXTENSIONS_FILE = + +#--------------------------------------------------------------------------- +# configuration options related to the man page output +#--------------------------------------------------------------------------- + +# If the GENERATE_MAN tag is set to YES (the default) Doxygen will +# generate man pages + +GENERATE_MAN = NO + +# The MAN_OUTPUT tag is used to specify where the man pages will be put. +# If a relative path is entered the value of OUTPUT_DIRECTORY will be +# put in front of it. If left blank `man' will be used as the default path. + +MAN_OUTPUT = man + +# The MAN_EXTENSION tag determines the extension that is added to +# the generated man pages (default is the subroutine's section .3) + +MAN_EXTENSION = .3 + +# If the MAN_LINKS tag is set to YES and Doxygen generates man output, +# then it will generate one additional man file for each entity +# documented in the real man page(s). These additional files +# only source the real man page, but without them the man command +# would be unable to find the correct page. The default is NO. + +MAN_LINKS = NO + +#--------------------------------------------------------------------------- +# configuration options related to the XML output +#--------------------------------------------------------------------------- + +# If the GENERATE_XML tag is set to YES Doxygen will +# generate an XML file that captures the structure of +# the code including all documentation. + +GENERATE_XML = NO + +# The XML_OUTPUT tag is used to specify where the XML pages will be put. +# If a relative path is entered the value of OUTPUT_DIRECTORY will be +# put in front of it. If left blank `xml' will be used as the default path. + +XML_OUTPUT = xml + +# The XML_SCHEMA tag can be used to specify an XML schema, +# which can be used by a validating XML parser to check the +# syntax of the XML files. + +XML_SCHEMA = + +# The XML_DTD tag can be used to specify an XML DTD, +# which can be used by a validating XML parser to check the +# syntax of the XML files. + +XML_DTD = + +# If the XML_PROGRAMLISTING tag is set to YES Doxygen will +# dump the program listings (including syntax highlighting +# and cross-referencing information) to the XML output. Note that +# enabling this will significantly increase the size of the XML output. + +XML_PROGRAMLISTING = YES + +#--------------------------------------------------------------------------- +# configuration options for the AutoGen Definitions output +#--------------------------------------------------------------------------- + +# If the GENERATE_AUTOGEN_DEF tag is set to YES Doxygen will +# generate an AutoGen Definitions (see autogen.sf.net) file +# that captures the structure of the code including all +# documentation. Note that this feature is still experimental +# and incomplete at the moment. + +GENERATE_AUTOGEN_DEF = NO + +#--------------------------------------------------------------------------- +# configuration options related to the Perl module output +#--------------------------------------------------------------------------- + +# If the GENERATE_PERLMOD tag is set to YES Doxygen will +# generate a Perl module file that captures the structure of +# the code including all documentation. Note that this +# feature is still experimental and incomplete at the +# moment. + +GENERATE_PERLMOD = NO + +# If the PERLMOD_LATEX tag is set to YES Doxygen will generate +# the necessary Makefile rules, Perl scripts and LaTeX code to be able +# to generate PDF and DVI output from the Perl module output. + +PERLMOD_LATEX = NO + +# If the PERLMOD_PRETTY tag is set to YES the Perl module output will be +# nicely formatted so it can be parsed by a human reader. +# This is useful +# if you want to understand what is going on. +# On the other hand, if this +# tag is set to NO the size of the Perl module output will be much smaller +# and Perl will parse it just the same. + +PERLMOD_PRETTY = YES + +# The names of the make variables in the generated doxyrules.make file +# are prefixed with the string contained in PERLMOD_MAKEVAR_PREFIX. +# This is useful so different doxyrules.make files included by the same +# Makefile don't overwrite each other's variables. + +PERLMOD_MAKEVAR_PREFIX = + +#--------------------------------------------------------------------------- +# Configuration options related to the preprocessor +#--------------------------------------------------------------------------- + +# If the ENABLE_PREPROCESSING tag is set to YES (the default) Doxygen will +# evaluate all C-preprocessor directives found in the sources and include +# files. + +ENABLE_PREPROCESSING = YES + +# If the MACRO_EXPANSION tag is set to YES Doxygen will expand all macro +# names in the source code. If set to NO (the default) only conditional +# compilation will be performed. Macro expansion can be done in a controlled +# way by setting EXPAND_ONLY_PREDEF to YES. + +MACRO_EXPANSION = NO + +# If the EXPAND_ONLY_PREDEF and MACRO_EXPANSION tags are both set to YES +# then the macro expansion is limited to the macros specified with the +# PREDEFINED and EXPAND_AS_DEFINED tags. + +EXPAND_ONLY_PREDEF = NO + +# If the SEARCH_INCLUDES tag is set to YES (the default) the includes files +# in the INCLUDE_PATH (see below) will be search if a #include is found. + +SEARCH_INCLUDES = YES + +# The INCLUDE_PATH tag can be used to specify one or more directories that +# contain include files that are not input files but should be processed by +# the preprocessor. + +INCLUDE_PATH = + +# You can use the INCLUDE_FILE_PATTERNS tag to specify one or more wildcard +# patterns (like *.h and *.hpp) to filter out the header-files in the +# directories. If left blank, the patterns specified with FILE_PATTERNS will +# be used. + +INCLUDE_FILE_PATTERNS = + +# The PREDEFINED tag can be used to specify one or more macro names that +# are defined before the preprocessor is started (similar to the -D option of +# gcc). The argument of the tag is a list of macros of the form: name +# or name=definition (no spaces). If the definition and the = are +# omitted =1 is assumed. To prevent a macro definition from being +# undefined via #undef or recursively expanded use the := operator +# instead of the = operator. + +PREDEFINED = + +# If the MACRO_EXPANSION and EXPAND_ONLY_PREDEF tags are set to YES then +# this tag can be used to specify a list of macro names that should be expanded. +# The macro definition that is found in the sources will be used. +# Use the PREDEFINED tag if you want to use a different macro definition. + +EXPAND_AS_DEFINED = + +# If the SKIP_FUNCTION_MACROS tag is set to YES (the default) then +# doxygen's preprocessor will remove all function-like macros that are alone +# on a line, have an all uppercase name, and do not end with a semicolon. Such +# function macros are typically used for boiler-plate code, and will confuse +# the parser if not removed. + +SKIP_FUNCTION_MACROS = YES + +#--------------------------------------------------------------------------- +# Configuration::additions related to external references +#--------------------------------------------------------------------------- + +# The TAGFILES option can be used to specify one or more tagfiles. +# Optionally an initial location of the external documentation +# can be added for each tagfile. The format of a tag file without +# this location is as follows: +# +# TAGFILES = file1 file2 ... +# Adding location for the tag files is done as follows: +# +# TAGFILES = file1=loc1 "file2 = loc2" ... +# where "loc1" and "loc2" can be relative or absolute paths or +# URLs. If a location is present for each tag, the installdox tool +# does not have to be run to correct the links. +# Note that each tag file must have a unique name +# (where the name does NOT include the path) +# If a tag file is not located in the directory in which doxygen +# is run, you must also specify the path to the tagfile here. + +TAGFILES = + +# When a file name is specified after GENERATE_TAGFILE, doxygen will create +# a tag file that is based on the input files it reads. + +GENERATE_TAGFILE = + +# If the ALLEXTERNALS tag is set to YES all external classes will be listed +# in the class index. If set to NO only the inherited external classes +# will be listed. + +ALLEXTERNALS = NO + +# If the EXTERNAL_GROUPS tag is set to YES all external groups will be listed +# in the modules index. If set to NO, only the current project's groups will +# be listed. + +EXTERNAL_GROUPS = YES + +# The PERL_PATH should be the absolute path and name of the perl script +# interpreter (i.e. the result of `which perl'). + +PERL_PATH = /usr/bin/perl + +#--------------------------------------------------------------------------- +# Configuration options related to the dot tool +#--------------------------------------------------------------------------- + +# If the CLASS_DIAGRAMS tag is set to YES (the default) Doxygen will +# generate a inheritance diagram (in HTML, RTF and LaTeX) for classes with base +# or super classes. Setting the tag to NO turns the diagrams off. Note that +# this option is superseded by the HAVE_DOT option below. This is only a +# fallback. It is recommended to install and use dot, since it yields more +# powerful graphs. + +CLASS_DIAGRAMS = YES + +# You can define message sequence charts within doxygen comments using the \msc +# command. Doxygen will then run the mscgen tool (see +# http://www.mcternan.me.uk/mscgen/) to produce the chart and insert it in the +# documentation. The MSCGEN_PATH tag allows you to specify the directory where +# the mscgen tool resides. If left empty the tool is assumed to be found in the +# default search path. + +MSCGEN_PATH = + +# If set to YES, the inheritance and collaboration graphs will hide +# inheritance and usage relations if the target is undocumented +# or is not a class. + +HIDE_UNDOC_RELATIONS = NO + +# If you set the HAVE_DOT tag to YES then doxygen will assume the dot tool is +# available from the path. This tool is part of Graphviz, a graph visualization +# toolkit from AT&T and Lucent Bell Labs. The other options in this section +# have no effect if this option is set to NO (the default) + +HAVE_DOT = YES + +# The DOT_NUM_THREADS specifies the number of dot invocations doxygen is +# allowed to run in parallel. When set to 0 (the default) doxygen will +# base this on the number of processors available in the system. You can set it +# explicitly to a value larger than 0 to get control over the balance +# between CPU load and processing speed. + +DOT_NUM_THREADS = 0 + +# By default doxygen will write a font called FreeSans.ttf to the output +# directory and reference it in all dot files that doxygen generates. This +# font does not include all possible unicode characters however, so when you need +# these (or just want a differently looking font) you can specify the font name +# using DOT_FONTNAME. You need need to make sure dot is able to find the font, +# which can be done by putting it in a standard location or by setting the +# DOTFONTPATH environment variable or by setting DOT_FONTPATH to the directory +# containing the font. + +DOT_FONTNAME = FreeSans + +# The DOT_FONTSIZE tag can be used to set the size of the font of dot graphs. +# The default size is 10pt. + +DOT_FONTSIZE = 10 + +# By default doxygen will tell dot to use the output directory to look for the +# FreeSans.ttf font (which doxygen will put there itself). If you specify a +# different font using DOT_FONTNAME you can set the path where dot +# can find it using this tag. + +DOT_FONTPATH = + +# If the CLASS_GRAPH and HAVE_DOT tags are set to YES then doxygen +# will generate a graph for each documented class showing the direct and +# indirect inheritance relations. Setting this tag to YES will force the +# the CLASS_DIAGRAMS tag to NO. + +CLASS_GRAPH = YES + +# If the COLLABORATION_GRAPH and HAVE_DOT tags are set to YES then doxygen +# will generate a graph for each documented class showing the direct and +# indirect implementation dependencies (inheritance, containment, and +# class references variables) of the class with other documented classes. + +COLLABORATION_GRAPH = YES + +# If the GROUP_GRAPHS and HAVE_DOT tags are set to YES then doxygen +# will generate a graph for groups, showing the direct groups dependencies + +GROUP_GRAPHS = YES + +# If the UML_LOOK tag is set to YES doxygen will generate inheritance and +# collaboration diagrams in a style similar to the OMG's Unified Modeling +# Language. + +UML_LOOK = YES + +# If set to YES, the inheritance and collaboration graphs will show the +# relations between templates and their instances. + +TEMPLATE_RELATIONS = NO + +# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDE_GRAPH, and HAVE_DOT +# tags are set to YES then doxygen will generate a graph for each documented +# file showing the direct and indirect include dependencies of the file with +# other documented files. + +INCLUDE_GRAPH = YES + +# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDED_BY_GRAPH, and +# HAVE_DOT tags are set to YES then doxygen will generate a graph for each +# documented header file showing the documented files that directly or +# indirectly include this file. + +INCLUDED_BY_GRAPH = YES + +# If the CALL_GRAPH and HAVE_DOT options are set to YES then +# doxygen will generate a call dependency graph for every global function +# or class method. Note that enabling this option will significantly increase +# the time of a run. So in most cases it will be better to enable call graphs +# for selected functions only using the \callgraph command. + +CALL_GRAPH = YES + +# If the CALLER_GRAPH and HAVE_DOT tags are set to YES then +# doxygen will generate a caller dependency graph for every global function +# or class method. Note that enabling this option will significantly increase +# the time of a run. So in most cases it will be better to enable caller +# graphs for selected functions only using the \callergraph command. + +CALLER_GRAPH = YES + +# If the GRAPHICAL_HIERARCHY and HAVE_DOT tags are set to YES then doxygen +# will graphical hierarchy of all classes instead of a textual one. + +GRAPHICAL_HIERARCHY = YES + +# If the DIRECTORY_GRAPH, SHOW_DIRECTORIES and HAVE_DOT tags are set to YES +# then doxygen will show the dependencies a directory has on other directories +# in a graphical way. The dependency relations are determined by the #include +# relations between the files in the directories. + +DIRECTORY_GRAPH = YES + +# The DOT_IMAGE_FORMAT tag can be used to set the image format of the images +# generated by dot. Possible values are png, jpg, or gif +# If left blank png will be used. + +DOT_IMAGE_FORMAT = png + +# The tag DOT_PATH can be used to specify the path where the dot tool can be +# found. If left blank, it is assumed the dot tool can be found in the path. + +DOT_PATH = + +# The DOTFILE_DIRS tag can be used to specify one or more directories that +# contain dot files that are included in the documentation (see the +# \dotfile command). + +DOTFILE_DIRS = + +# The DOT_GRAPH_MAX_NODES tag can be used to set the maximum number of +# nodes that will be shown in the graph. If the number of nodes in a graph +# becomes larger than this value, doxygen will truncate the graph, which is +# visualized by representing a node as a red box. Note that doxygen if the +# number of direct children of the root node in a graph is already larger than +# DOT_GRAPH_MAX_NODES then the graph will not be shown at all. Also note +# that the size of a graph can be further restricted by MAX_DOT_GRAPH_DEPTH. + +DOT_GRAPH_MAX_NODES = 50 + +# The MAX_DOT_GRAPH_DEPTH tag can be used to set the maximum depth of the +# graphs generated by dot. A depth value of 3 means that only nodes reachable +# from the root by following a path via at most 3 edges will be shown. Nodes +# that lay further from the root node will be omitted. Note that setting this +# option to 1 or 2 may greatly reduce the computation time needed for large +# code bases. Also note that the size of a graph can be further restricted by +# DOT_GRAPH_MAX_NODES. Using a depth of 0 means no depth restriction. + +MAX_DOT_GRAPH_DEPTH = 0 + +# Set the DOT_TRANSPARENT tag to YES to generate images with a transparent +# background. This is disabled by default, because dot on Windows does not +# seem to support this out of the box. Warning: Depending on the platform used, +# enabling this option may lead to badly anti-aliased labels on the edges of +# a graph (i.e. they become hard to read). + +DOT_TRANSPARENT = NO + +# Set the DOT_MULTI_TARGETS tag to YES allow dot to generate multiple output +# files in one run (i.e. multiple -o and -T options on the command line). This +# makes dot run faster, but since only newer versions of dot (>1.8.10) +# support this, this feature is disabled by default. + +DOT_MULTI_TARGETS = YES + +# If the GENERATE_LEGEND tag is set to YES (the default) Doxygen will +# generate a legend page explaining the meaning of the various boxes and +# arrows in the dot generated graphs. + +GENERATE_LEGEND = YES + +# If the DOT_CLEANUP tag is set to YES (the default) Doxygen will +# remove the intermediate dot files that are used to generate +# the various graphs. + +DOT_CLEANUP = YES diff --git a/Documentation/backup-docs/old/Doxyfile.coreboot_simple b/Documentation/backup-docs/old/Doxyfile.coreboot_simple new file mode 100644 index 0000000..2135d96 --- /dev/null +++ b/Documentation/backup-docs/old/Doxyfile.coreboot_simple @@ -0,0 +1,259 @@ +# Doxyfile 1.8.8 +DOXYFILE_ENCODING = UTF-8 +PROJECT_NAME = coreboot +PROJECT_NUMBER = +PROJECT_BRIEF = "coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers." +PROJECT_LOGO = documentation/coreboot_logo.png +OUTPUT_DIRECTORY = doxygen +CREATE_SUBDIRS = YES +ALLOW_UNICODE_NAMES = NO +OUTPUT_LANGUAGE = English +BRIEF_MEMBER_DESC = YES +REPEAT_BRIEF = YES +ABBREVIATE_BRIEF = +ALWAYS_DETAILED_SEC = YES +INLINE_INHERITED_MEMB = NO +FULL_PATH_NAMES = YES +STRIP_FROM_PATH = +STRIP_FROM_INC_PATH = +SHORT_NAMES = NO +JAVADOC_AUTOBRIEF = YES +QT_AUTOBRIEF = NO +MULTILINE_CPP_IS_BRIEF = NO +INHERIT_DOCS = YES +SEPARATE_MEMBER_PAGES = NO +TAB_SIZE = 8 +ALIASES = +TCL_SUBST = +OPTIMIZE_OUTPUT_FOR_C = YES +OPTIMIZE_OUTPUT_JAVA = NO +OPTIMIZE_FOR_FORTRAN = NO +OPTIMIZE_OUTPUT_VHDL = NO +EXTENSION_MAPPING = +MARKDOWN_SUPPORT = YES +AUTOLINK_SUPPORT = YES +BUILTIN_STL_SUPPORT = NO +CPP_CLI_SUPPORT = NO +SIP_SUPPORT = NO +IDL_PROPERTY_SUPPORT = YES +DISTRIBUTE_GROUP_DOC = NO +SUBGROUPING = YES +INLINE_GROUPED_CLASSES = NO +INLINE_SIMPLE_STRUCTS = NO +TYPEDEF_HIDES_STRUCT = NO +LOOKUP_CACHE_SIZE = 0 +EXTRACT_ALL = YES +EXTRACT_PRIVATE = NO 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+EXPAND_AS_DEFINED = +SKIP_FUNCTION_MACROS = YES +TAGFILES = +GENERATE_TAGFILE = +ALLEXTERNALS = NO +EXTERNAL_GROUPS = YES +EXTERNAL_PAGES = YES +PERL_PATH = /usr/bin/perl +CLASS_DIAGRAMS = YES +MSCGEN_PATH = +DIA_PATH = +HIDE_UNDOC_RELATIONS = NO +HAVE_DOT = NO +DOT_NUM_THREADS = 0 +DOT_FONTNAME = Helvetica +DOT_FONTSIZE = 10 +DOT_FONTPATH = +CLASS_GRAPH = YES +COLLABORATION_GRAPH = YES +GROUP_GRAPHS = YES +UML_LOOK = YES +UML_LIMIT_NUM_FIELDS = 10 +TEMPLATE_RELATIONS = NO +INCLUDE_GRAPH = YES +INCLUDED_BY_GRAPH = YES +CALL_GRAPH = YES +CALLER_GRAPH = YES +GRAPHICAL_HIERARCHY = YES +DIRECTORY_GRAPH = YES +DOT_IMAGE_FORMAT = png +INTERACTIVE_SVG = NO +DOT_PATH = +DOTFILE_DIRS = +MSCFILE_DIRS = +DIAFILE_DIRS = +PLANTUML_JAR_PATH = +DOT_GRAPH_MAX_NODES = 50 +MAX_DOT_GRAPH_DEPTH = 0 +DOT_TRANSPARENT = NO +DOT_MULTI_TARGETS = YES +GENERATE_LEGEND = YES +DOT_CLEANUP = YES diff --git a/Documentation/backup-docs/old/Intel/Board/Galileo_checklist.html b/Documentation/backup-docs/old/Intel/Board/Galileo_checklist.html new file mode 100644 index 0000000..ba1469b --- /dev/null +++ b/Documentation/backup-docs/old/Intel/Board/Galileo_checklist.html @@ -0,0 +1,162 @@ +<html> +<head> +<title>Galileo Implementation Status</title> +</title> +<body> +<h1>Galileo Implementation Status<br>2016/06/08 17:18:24 PDT</h1> +<table> + <tr><td colspan=2><b>Legend</b></td></tr> + <tr><td bgcolor="#ffc0c0">Red</td><td>Required - To-be-implemented</td></tr> + <tr><td bgcolor="#ffffc0">Yellow</td><td>Optional</td></tr> + <tr><td bgcolor="#c0ffc0">Green</td><td>Implemented</td></tr> +</table> +<table> + <tr valign="top"> + <td> +<table border=1> +<tr><th colspan=2>bootblock: 100% Done</th></tr> +<tr><th>Type</th><th>Routine</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>bootblock_c_entry</td></tr> +<tr bgcolor=#c0ffc0><td>Required</td><td>bootblock_main_with_timestamp</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>bootblock_mainboard_early_init</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>bootblock_mainboard_init</td></tr> +<tr bgcolor=#c0ffc0><td>Required</td><td>bootblock_pre_c_entry</td></tr> +<tr bgcolor=#c0ffc0><td>Required</td><td>bootblock_protected_mode_entry</td></tr> +<tr bgcolor=#c0ffc0><td>Required</td><td>bootblock_soc_early_init</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>bootblock_soc_init</td></tr> +<tr bgcolor=#c0ffc0><td>Required</td><td>tsc_freq_mhz</td></tr> +<tr bgcolor=#c0ffc0><td>Required</td><td>uart_init</td></tr> +</table> + </td> + <td width=5> </td> + <td> +<table border=1> +<tr><th colspan=2>romstage: 66% Done</th></tr> +<tr><th>Type</th><th>Routine</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>arch_segment_loaded</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>backup_top_of_ram</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>boot_device_init</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>car_mainboard_post_console_init</td></tr> +<tr bgcolor=#c0ffc0><td>Required</td><td>car_mainboard_pre_console_init</td></tr> +<tr bgcolor=#c0ffc0><td>Required</td><td>car_soc_post_console_init</td></tr> +<tr bgcolor=#c0ffc0><td>Required</td><td>car_soc_pre_console_init</td></tr> +<tr bgcolor=#c0ffc0><td>Required</td><td>car_stage_entry</td></tr> +<tr bgcolor=#c0ffc0><td>Required</td><td>cbfs_master_header_locator</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>cbmem_fail_resume</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>clear_recovery_mode_switch</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>cpu_smi_handler</td></tr> +<tr bgcolor=#c0ffc0><td>Required</td><td>fill_power_state</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>get_sw_write_protect_state</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>get_top_of_ram</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>gpio_acpi_path</td></tr> +<tr bgcolor=#c0ffc0><td>Required</td><td>init_timer</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>mainboard_add_dimm_info</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>mainboard_check_ec_image</td></tr> +<tr bgcolor=#ffc0c0><td>Required</td><td>mainboard_fill_spd_data</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>mainboard_io_trap_handler</td></tr> +<tr bgcolor=#ffc0c0><td>Required</td><td>mainboard_memory_init_params</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>mainboard_post</td></tr> +<tr bgcolor=#c0ffc0><td>Required</td><td>mainboard_romstage_entry</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>mainboard_save_dimm_info</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>mainboard_smi_apmc</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>mainboard_smi_gpi</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>mainboard_smi_sleep</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>map_oprom_vendev</td></tr> +<tr bgcolor=#ffc0c0><td>Required</td><td>migrate_power_state</td></tr> +<tr bgcolor=#ffc0c0><td>Required</td><td>mrc_cache_get_current_with_version</td></tr> +<tr bgcolor=#ffc0c0><td>Required</td><td>mrc_cache_stash_data_with_version</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>platform_prog_run</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>platform_segment_loaded</td></tr> +<tr bgcolor=#c0ffc0><td>Required</td><td>print_fsp_info</td></tr> +<tr bgcolor=#c0ffc0><td>Required</td><td>raminit</td></tr> +<tr bgcolor=#c0ffc0><td>Required</td><td>ramstage_cache_invalid</td></tr> +<tr bgcolor=#ffc0c0><td>Required</td><td>report_memory_config</td></tr> +<tr bgcolor=#c0ffc0><td>Required</td><td>romstage_common</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>save_chromeos_gpios</td></tr> +<tr bgcolor=#ffc0c0><td>Required</td><td>set_max_freq</td></tr> +<tr bgcolor=#c0ffc0><td>Required</td><td>setup_stack_and_mtrrs</td></tr> +<tr bgcolor=#ffc0c0><td>Required</td><td>smm_region</td></tr> +<tr bgcolor=#ffc0c0><td>Required</td><td>smm_region_size</td></tr> +<tr bgcolor=#c0ffc0><td>Required</td><td>soc_after_ram_init</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>soc_display_memory_init_params</td></tr> +<tr bgcolor=#c0ffc0><td>Required</td><td>soc_display_mtrrs</td></tr> +<tr bgcolor=#c0ffc0><td>Required</td><td>soc_get_variable_mtrr_count</td></tr> +<tr bgcolor=#c0ffc0><td>Required</td><td>soc_memory_init_params</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>soc_pre_ram_init</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>southbridge_smi_handler</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>stage_cache_add</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>stage_cache_load_stage</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>timestamp_get</td></tr> +<tr bgcolor=#c0ffc0><td>Required</td><td>tsc_freq_mhz</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>vb2ex_hwcrypto_digest_extend</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>vb2ex_hwcrypto_digest_finalize</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>vb2ex_hwcrypto_digest_init</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>vboot_platform_prepare_reboot</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>verstage_mainboard_init</td></tr> +</table> + </td> + <td width=5> </td> + <td> +<table border=1> +<tr><th colspan=2>ramstage: 55% Done</th></tr> +<tr><th>Type</th><th>Routine</td></tr> +<tr bgcolor=#ffc0c0><td>Required</td><td>acpi_create_serialio_ssdt</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>arch_segment_loaded</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>backup_top_of_ram</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>boot_device_init</td></tr> +<tr bgcolor=#c0ffc0><td>Required</td><td>cbfs_master_header_locator</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>cbmem_fail_resume</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>clear_recovery_mode_switch</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>cpu_smi_handler</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>fw_cfg_acpi_tables</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>get_sw_write_protect_state</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>get_top_of_ram</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>gpio_acpi_path</td></tr> +<tr bgcolor=#c0ffc0><td>Required</td><td>init_timer</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>lb_board</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>lb_framebuffer</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>mainboard_add_dimm_info</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>mainboard_io_trap_handler</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>mainboard_post</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>mainboard_silicon_init_params</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>mainboard_smi_apmc</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>mainboard_smi_gpi</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>mainboard_smi_sleep</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>mainboard_suspend_resume</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>map_oprom_vendev</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>mirror_payload</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>northbridge_smi_handler</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>nvm_mmio_to_flash_offset</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>platform_prog_run</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>platform_segment_loaded</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>save_chromeos_gpios</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>smbios_mainboard_bios_version</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>smbios_mainboard_manufacturer</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>smbios_mainboard_product_name</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>smbios_mainboard_serial_number</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>smbios_mainboard_set_uuid</td></tr> +<tr bgcolor=#c0ffc0><td>Required</td><td>smbios_mainboard_version</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>smm_disable_busmaster</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>soc_after_silicon_init</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>soc_display_silicon_init_params</td></tr> +<tr bgcolor=#ffc0c0><td>Required</td><td>soc_fill_acpi_wake</td></tr> +<tr bgcolor=#c0ffc0><td>Required</td><td>soc_silicon_init_params</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>soc_skip_ucode_update</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>southbridge_smi_handler</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>stage_cache_add</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>stage_cache_load_stage</td></tr> +<tr bgcolor=#ffc0c0><td>Required</td><td>timestamp_get</td></tr> +<tr bgcolor=#ffc0c0><td>Required</td><td>timestamp_tick_freq_mhz</td></tr> +<tr bgcolor=#c0ffc0><td>Required</td><td>tsc_freq_mhz</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>vb2ex_hwcrypto_digest_extend</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>vb2ex_hwcrypto_digest_finalize</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>vb2ex_hwcrypto_digest_init</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>wifi_regulatory_domain</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>write_smp_table</td></tr> +</table> + </td> + <td width=5> </td> + </tr> +</table> +</body> +</html> diff --git a/Documentation/backup-docs/old/Intel/Board/board.html b/Documentation/backup-docs/old/Intel/Board/board.html new file mode 100644 index 0000000..1b2d323 --- /dev/null +++ b/Documentation/backup-docs/old/Intel/Board/board.html @@ -0,0 +1,240 @@ +<!DOCTYPE html> +<html> + <head> + <title>Board</title> + </head> + <body> + +<h1>x86 Board Development</h1> +<p> + Board development requires System-on-a-Chip (SoC) support. + The combined steps are listed + <a target="_blank" href="../development.html">here</a>. + The development steps for the board are listed below: +</p> +<ol> + <li><a href="#RequiredFiles">Required Files</a></li> + <li>Enable <a href="#SerialOutput">Serial Output</a></li> + <li>Load the <a href="#SpdData">Memory Timing Data</a></li> + <li><a href="#DisablePciDevices">Disable</a> the PCI devices</li> + <li><a href="#AcpiTables">ACPI Tables</a></li> +</ol> + + +<hr> +<h1><a name="RequiredFiles">Required Files</a></h1> +<p> + Create the board directory as src/mainboard/<Vendor>/<Board>. +</p> + +<p> + The following files are required to build a new board: +</p> +<ol> + <li>Kconfig.name - Defines the Kconfig value for the board</li> + <li>Kconfig + <ol type="A"> + <li>Selects the SoC for the board and specifies the SPI flash size + <ol type="I"> + <li>BOARD_ROMSIZE_KB_<Size></li> + <li>SOC_<Vendor>_<Chip Family></li> + </ol> + </li> + <li>Declare the Kconfig values for: + <ol type="I"> + <li>MAINBOARD_DIR</li> + <li>MAINBOARD_PART_NUMBER</li> + <li>MAINBOARD_VENDOR</li> + </ol> + </li> + </ol> + </li> + <li>devicetree.cb - Enable root bridge and serial port + <ol type="A"> + <li>The first line must be "chip soc/Intel/<soc family>"; + this path is used by the generated static.c to include the chip.h + header file + </li> + </ol> + </li> + <li>romstage.c + <ol type="A"> + <li>Add routine mainboard_romstage_entry which calls romstage_common</li> + </ol> + </li> + <li>Configure coreboot build: + <ol type="A"> + <li>Set LOCALVERSION</li> + <li>Select vendor for the board</li> + <li>Select the board</li> + <li>CBFS_SIZE = 0x00100000</li> + <li>Set the CPU_MICROCODE_CBFS_LEN</li> + <li>Set the CPU_MICROCODE_CBFS_LOC</li> + <li>Set the FSP_IMAGE_ID_STRING</li> + <li>Set the FSP_LOC</li> + <li>Disable GOP_SUPPORT</li> + <li>No payload</li> + <li>Choose the default value for all other options</li> + </ol> + </li> +</ol> + + +<hr> +<h1><a name="SerialOutput">Enable Serial Output</a></h1> +<p> + Use the following steps to enable serial output: +</p> +<ol> + <li>Implement the car_mainboard_pre_console_init routine in the com_init.c + file: + <ol type="A"> + <li>Power on and enable the UART controller</li> + <li>Connect the UART receive and transmit data lines to the + appropriate SoC pins + </li> + </ol> + </li> + <li>Add Makefile.inc + <ol type="A"> + <li>Add com_init.c to romstage</li> + </ol> + </li> +</ol> + + +<hr> +<h1><a name="SpdData">Memory Timing Data</a></h1> +<p> + Memory timing data is located in the flash. This data is in the format of + <a target="_blank" href="https://en.wikipedia.org/wiki/Serial_presence_detect">serial presence detect</a> + (SPD) data. + Use the following steps to load the SPD data: +</p> +<ol> + <li>Edit Kconfig to add the DISPLAY_SPD_DATA" value which enables the + display of the SPD data being passed to MemoryInit + </li> + <li>Create an "spd" subdirectory</li> + <li>Create an spd/spd.c file for the SPD implementation + <ol type="A"> + <li>Implement the mainboard_fill_spd_data routine + <ol type="i"> + <li>Read the SPD data either from the spd.bin file or using I2C or SMBUS</li> + <li>Fill in the pei_data structure with SPD data for each of the DIMMs</li> + <li>Set the DIMM channel configuration</li> + </ol> + </li> + </ol> + </li> + <li>Add an .spd.hex file containing the memory timing data to the spd subdirectory</li> + <li>Create spd/Makefile.inc + <ol type="A"> + <li>Add spd.c to romstage</li> + <li>Add the .spd.hex file to SPD_SOURCES</li> + </ol> + </li> + <li>Edit Makefile.inc to add the spd subdirectory</li> + <li>Edit romstage.c + <ol type="A"> + <li>Call mainboard_fill_spd_data</li> + <li>Add mainboard_memory_init_params to copy the SPD and DRAM + configuration data from the pei_data structure into the UPDs + for MemoryInit + </li> + </ol> + </li> + <li>Edit devicetree.cb + <ol type="A"> + <li>Include the UPD parameters for MemoryInit except for: + <ul> + <li>Address of SPD data</li> + <li>DRAM configuration set above</li> + </ul> + </li> + </ol> + </li> + <li>A working FSP + <a target="_blank" href="../fsp1_1.html#MemoryInit">MemoryInit</a> + routine is required to complete debugging</li> + <li>Debug the result until port 0x80 outputs + <ol type="A"> + <li>0x34: + - Just after entering + <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/raminit.c;hb=HEAD#l67">raminit</a> + </li> + <li>0x36: + - Just before displaying the + <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/raminit.c;hb=HEAD#l106">UPD parameters</a> + for FSP MemoryInit + </li> + <li>0x92: <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l219">POST_FSP_MEMORY_INIT</a> + - Just before calling FSP + <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/raminit.c;hb=HEAD#l125">MemoryInit</a> + </li> + <li>0x37: + - Just after returning from FSP + <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/raminit.c;hb=HEAD#l127">MemoryInit</a> + </li> + </ol> + </li> + <li>Continue debugging with CONFIG_DISPLAY_HOBS enabled until TempRamExit is called</li> +</ol> + + + +<hr> +<h1><a name="DisablePciDevices">Disable PCI Devices</a></h1> +<p> + Ramstage's BS_DEV_ENUMERATE state displays the PCI vendor and device IDs for all + of the devices in the system. Edit the devicetree.cb file: +</p> +<ol> + <li>Edit the devicetree.cb file: + <ol type="A"> + <li>Add an entry for a PCI device.function and turn it off. The entry + should look similar to: +<pre><code>device pci 14.0 off end</code></pre> + </li> + <li>Turn on the devices for: + <ul> + <li>Memory Controller</li> + <li>Debug serial device</li> + </ul> + </li> + </ol> + </li> + <li>Debug until the BS_DEV_ENUMERATE state shows the proper state for all of the devices</li> +</ol> + + + +<hr> +<h1><a name="AcpiTables">ACPI Tables</a></h1> +<ol> + <li>Edit Kconfig + <ol type="A"> + <li>Add "select HAVE_ACPI_TABLES"</li> + </ol> + </li> + <li>Add the acpi_tables.c module: + <ol type="A"> + <li>Include soc/acpi.h</li> + <li>Add the acpi_create_fadt routine + <ol type="I"> + <li>fill in the ACPI header</li> + <li>Call the acpi_fill_in_fadt routine</li> + </ol> + </li> + </ol> + </li> + <li>Add the dsdt.asl module: + </li> +</ol> + + + +<hr> +<p>Modified: 20 February 2016</p> + </body> +</html> diff --git a/Documentation/backup-docs/old/Intel/Board/galileo.html b/Documentation/backup-docs/old/Intel/Board/galileo.html new file mode 100644 index 0000000..cdc8fda --- /dev/null +++ b/Documentation/backup-docs/old/Intel/Board/galileo.html @@ -0,0 +1,114 @@ +<!DOCTYPE html> +<html> + <head> + <title>Galileo</title> + </head> + <body> + +<h1>Intel® Galileo Development Board</h1> +<table> + <tr> + <td><a target="_blank" href="http://www.mouser.com/images/microsites/Intel_Galileo2_lrg.jpg"><img alt="Galileo Gen 2" src="http://www.mouser.com/images/microsites/Intel_Galileo2_lrg.jpg" width=500></a></td> + <td> + The Intel® Galileo Gen 2 mainboard code was developed along with the Intel® + <a target="_blank" href="../SoC/quark.html">Quark™</a> SoC: + <ul> + <li><a target="_blank" href="../development.html">Overall</a> development</li> + <li><a target="_blank" href="../SoC/soc.html">SoC</a> support</li> + <li><a target="_blank" href="../fsp1_1.html">FSP 1.1</a> integration</li> + <li><a target="_blank" href="board.html">Board</a> support</li> + <li><a target="_blank" href="Galileo_checklist.html">Implementation Checklist</a></li> + </ul> + </td> + </tr> +</table> + + + +<hr> +<h1>Galileo Board Documentation</h1> +<ul> + <li>Common Components + <ul> + <li>A/D: Texas Instruments <a target="_blank" href="http://www.ti.com/lit/ds/symlink/adc108s102.pdf">ADC108S102</a></li> + <li>Analog Switch: Texas Instruments <a target="_blank" href="http://www.ti.com/lit/ds/symlink/ts5a23159.pdf">TS5A23159</a></li> + <li>Ethernet (10/100 MB/S): Texas Instruments <a target="_blank" href="http://www.ti.com/lit/ds/symlink/dp83848-ep.pdf">DP83848</a></li> + <li>Load Switch: Texas Instruments <a target="_blank" href="http://www.ti.com/lit/ds/symlink/tps22920.pdf">TPS22920x</a></li> + <li>Memory (256 MiB): Micron <a target="_blank" href="https://www.micron.com/~/media/Documents/Products/Data%20Sheet/DRAM/DDR3/1Gb_1_35V_DDR3L.pdf">MT41K128M8</a></li> + <li>SoC: Intel® Quark™ <a target="_blank" href="../SoC/quark.html">X-1000</a></li> + <li>Serial EEPROM (1 KiB): ON Semiconductor® <a target="_blank" href="http://www.onsemi.com/pub_link/Collateral/CAT24C01-D.PDF">CAT24C08</a></li> + <li>SPI Flash (8 MiB): Winbond™ <a target="_blank" href="http://www.winbond-usa.com/resource-files/w25q64fv_revl1_100713.pdf">W25Q64FV</a></li> + <li>Step Down Converter: Texas Instruments <a target="_blank" href="http://www.ti.com/lit/ds/slvsag7c/slvsag7c.pdf">TPS62130</a></li> + <li>Step Down Converter: Texas Instruments <a target="_blank" href="http://www.ti.com/lit/ug/slvu570/slvu570.pdf">TPS652510</a></li> + <li>Termination Regulator: Texas Instruments <a target="_blank" href="http://www.ti.com/lit/ds/symlink/tps51200.pdf">TPS51200</a></li> + </ul> + </li> + <li>Make a bootable <a target="_blank" href="https://software.intel.com/en-us/get-started-galileo-linux-step1">micro SD card</a></li> +</ul> + +<h2>Galileo Gen 2 Board Documentation</h2> +<ul> + <li><a target="_blank" href="http://files.linuxgizmos.com/intel_galileo_gen2_blockdiagram.jpg">Block Diagram</a></li> + <li><a target="_blank" href="https://software.intel.com/en-us/iot/library/galileo-getting-started">Getting Started</a></li> + <li><a target="_blank" href="http://www.intel.com/content/www/us/en/embedded/products/galileo/galileo-overview.html">Overview</a></li> + <li><a target="_blank" href="http://files.linuxgizmos.com/intel_galileo_gen2_ports.jpg">Port Diagram</a></li> + <li><a target="_blank" href="http://download.intel.com/support/galileo/sb/intelgalileogen2prodbrief_330736_003.pdf">Product Brief</a></li> + <li><a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/documents/guides/galileo-g2-schematic.pdf">Schematic</a></li> + <li><a target="_blank" href="http://download.intel.com/support/galileo/sb/galileo_boarduserguide_330237_001.pdf">User Guide</a></li> + <li>Components + <ul> + <li>A/D: Texas Instruments <a target="_blank" href="http://www.ti.com/lit/ds/symlink/adc108s102.pdf">ADC108S102</a></li> + <li>I2C 16-channel, 12-bit PWM: NXP Semiconductors <a target="_blank" href="http://cache.nxp.com/documents/data_sheet/PCA9685.pdf">PCA9685</a></li> + <li>I2C I/O Ports: NXP Semiconductors <a target="_blank" href="http://www.nxp.com/documents/data_sheet/PCAL9535A.pdf">PCAL9535A</a></li> + <li>Octal Buffer/Driver: Texas Instruments <a target="_blank" href="http://www.ti.com/lit/ds/symlink/sn74lv541at.pdf">SN74LV541AT</a></li> + <li>Quadruple Bus Buffer: Texas Instruments <a target="_blank" href="http://www.ti.com/lit/ds/symlink/sn74lv125a.pdf">SN74LV125A</a></li> + <li>Quadruple Bus Buffer with 3-State Outputs: Texas Instruments <a target="_blank" href="http://www.ti.com/lit/ds/symlink/sn74lvc126a.pdf">SN74LVC126A</a></li> + <li>Serial EEPROM (1 KiB): ON Semiconductor® <a target="_blank" href="http://www.onsemi.com/pub_link/Collateral/CAT24C01-D.PDF">CAT24C08</a></li> + <li>Single 2-input multiplexer: NXP Semiconductors <a target="_blank" href="http://www.nxp.com/documents/data_sheet/74LVC1G157.pdf">74LVC1G157</a></li> + <li>Step Down Converter: Texas Instruments <a target="_blank" href="http://www.ti.com/lit/ds/slvsag7c/slvsag7c.pdf">TPS62130</a></li> + </ul> + </li> +</ul> + +<h2>Galileo Gen 1 Board Documentation</h2> +<ul> + <li><a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/documents/datasheets/galileo-g1-datasheet.pdf">Datasheet</a></li> + <li><a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/documents/guides/galileo-g1-schematic.pdf">Schematic</a></li> + <li>Components + <ul> + <li>A/D: Analog Devices <a target="_blank" href="http://www.analog.com/media/en/technical-documentation/data-sheets/AD7298-1.pdf">AD7298</a></li> + <li>Analog Switch, 2 channel: Texas Instruments <a target="_blank" href="http://www.ti.com.cn/cn/lit/ds/symlink/ts5a23159.pdf">TS5A23159</a></li> + <li>EEPROM & GPIO: Cypress <a target="_blank" href="http://www.cypress.com/file/37971/download">CY8C9540A</a></li> + <li>Power Distribution Switch: Texas Instruments <a target="_blank" href="http://www.ti.com/lit/ds/symlink/tps2044b.pdf">TPS2051BDBVR</a></li> + <li>RS232 Converter: Texas Instruments <a target="_blank" href="http://www.ti.com/lit/ds/symlink/max3232.pdf">MAX3232</a></li> + <li>Voltage-Level Translator: Texas Instruments<a target="_blank" href="http://www.ti.com/lit/ds/symlink/txs0108e.pdf">TXS0108E</a></li> + </ul> + </li> +</ul> + + + +<hr> +<h1>Debug Tools</h1> +<ul> + <li>Flash Programmer: + <ul> + <li>Dediprog <a target="_blank" href="http://www.dediprog.com/pd/spi-flash-solution/SF100">SF100</a> ISP IC Programmer</li> + </ul> + </li> + <li>JTAG Connector: <a target="_blank" href="https://www.google.com/webhp?sourceid=chrome-instant&ion=1&espv=2&ie=UTF-8#q=Olimex+ARM-JTAG-20-10">Olimex ARM-JTAG-20-10</a></li> + <li>JTAG Debugger: + <ul> + <li>Olimex LTD <a target="_blank" href="https://www.google.com/webhp?sourceid=chrome-instant&ion=1&espv=2&ie=UTF-8#q=Olimex+ARM-USB-OCD-H">ARM-USB-OCD-H</a></li> + <li>Tincan Tools <a target="_blank" href="https://www.tincantools.com/wiki/Flyswatter2">Flyswatter2</a></li> + </ul> + </li> + <li><a target="_blank" href="http://download.intel.com/support/processors/quark/sb/sourcedebugusingopenocd_quark_appnote_330015_003.pdf">Hardware Setup and Software Installation</a></li> + <li>USB Serial cable: FTDI <a target="_blank" href="https://www.google.com/webhp?sourceid=chrome-instant&ion=1&espv=2&ie=UTF-8#q=FTDI+TTL-232R-3V3">TTL-232R-3V3</a></li> +</ul> + + +<hr> +<p>Modified: 29 February 2016</p> + </body> +</html> diff --git a/Documentation/backup-docs/old/Intel/SoC/quark.html b/Documentation/backup-docs/old/Intel/SoC/quark.html new file mode 100644 index 0000000..61abebd --- /dev/null +++ b/Documentation/backup-docs/old/Intel/SoC/quark.html @@ -0,0 +1,179 @@ +<!DOCTYPE html> +<html> + <head> + <title>Quark™ SoC</title> + </head> + <body> + +<h1>Intel® Quark™ SoC</h1> +<table> + <tr> + <td><a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/images/embedded/16x9/edc-quark-block-diagram-16x9.png"><img alt="Quark Block Diagram" src="http://www.intel.com/content/dam/www/public/us/en/images/embedded/16x9/edc-quark-block-diagram-16x9.png" width=500></a></td> + <td> + The Quark™ SoC code was developed using the + <a target="_blank" href="../Board/galileo.html">Galileo Gen 2</a> + board: + <ul> + <li><a target="_blank" href="../development.html">Overall</a> development</li> + <li><a target="_blank" href="soc.html">SoC</a> support</li> + <li><a target="_blank" href="../fsp1_1.html">FSP 1.1</a> integration</li> + <li><a target="_blank" href="../Board/board.html">Board</a> support</li> + <li><a target="_blank" href="#QuarkFsp">Quark™ FSP</a></li> + <li><a target="_blank" href="#CorebootPayloadPkg">CorebootPayloadPkg</a></li> + </ul> + </td> + </tr> +</table> + + + +<hr> +<h1>Quark™ Documentation</h1> +<ul> + <li><a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/images/embedded/16x9/edc-quark-block-diagram-16x9.png">Block Diagram</a></li> + <li><a target="_blank" href="http://www.intel.com/content/www/us/en/embedded/products/quark/specifications.html">Specifications</a>: + <ul> + <li><a target="_blank" href="http://ark.intel.com/products/79084/Intel-Quark-SoC-X1000-16K-Cache-400-MHz">X1000</a> + - <a target="_blank" href="http://www.intel.com/content/www/us/en/search.html?keyword=X1000">Documentation</a>: + <ul> + <li><a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/documents/datasheets/quark-x1000-datasheet.pdf">Datasheet</a></li> + <li><a target="_blank" href="http://www.intel.com/content/dam/support/us/en/documents/processors/quark/sb/intelquarkcore_devman_001.pdf">Developer's Manual</a></li> + <li><a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/documents/product-briefs/intel-quark-product-brief-v3.pdf">Product Brief</a></li> + </ul> + </li> + </ul> + </li> + <li><a target="_blank" href="../index.html#Documentation">More documentation</a></li> +</ul> + + + +<hr> +<h1><a name="CorebootPayloadPkg">Quark™ EDK2 CorebootPayloadPkg</a></h1> +<p> +Build Instructions: +</p> +<ol> + <li>Set up <a href="#BuildEnvironment">build environment</a></li> + <li>Linux (assumes GCC48): +<pre><code>build -p CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc -a IA32 \ + -t GCC48 -b DEBUG -DDEBUG_PROPERTY_MASK=0x27 \ + -DDEBUG_PRINT_ERROR_LEVEL=0x80000042 -DSHELL_TYPE=BUILD_SHELL \ + -DMAX_LOGICAL_PROCESSORS=1 +ls Build/CorebootPayloadPkgIA32/DEBUG_GCC48/FV/UEFIPAYLOAD.fd +</code></pre> + </li> + <li>Windows (assumes Visual Studio 2015): +<pre><code>build -p CorebootPayloadPkg\CorebootPayloadPkgIa32.dsc -a IA32 -t VS2015x86 -b DEBUG -DDEBUG_PROPERTY_MASK=0x27 -DDEBUG_PRINT_ERROR_LEVEL=0x80000042 -DSHELL_TYPE=BUILD_SHELL -DMAX_LOGICAL_PROCESSORS=1 +dir Build\CorebootPayloadPkgIA32\DEBUG_VS2015x86\FV\UEFIPAYLOAD.fd +</code></pre> + </li> + <li>In the .config for coreboot, set the following Kconfig values: + <ul> + <li>CONFIG_PAYLOAD_ELF=y</li> + <li>CONFIG_PAYLOAD_FILE="path to UEFIPAYLOAD.fd"</li> + </ul> + </li> + <li>Build coreboot</li> + <li>Copy the image build/coreboot.rom into flash</li> +</ol> + + + +<hr> +<h1><a name="BuildEnvironment">Quark™ EDK2 Build Environment</a></h1> +<p> + Use the following steps to setup a build environment: +</p> +<ol> + <li>Get the EDK2 sources: + <ol type="A"> + <li>EDK2: git clone <a target="_blank" href="https://github.com/tianocore/edk2.git">https://github.com/tianocore/edk2.git</a></li> + <li>EDK2-non-osi: git clone <a target="_blank" href="https://github.com/tianocore/edk2-non-osi.git">https://github.com/tianocore/edk2-non-osi.git</a></li> + <li>Win32 BaseTools: git clone <a target="_blank" href="https://github.com/tianocore/edk2-BaseTools-win32.git">https://github.com/tianocore/edk2-BaseTools-win32.git</a></li> + </ol> + </li> + <li>Set up a build window: + <ul> + <li>Linux: +<pre><code>export WORKSPACE=$PWD +export PACKAGES_PATH="$PWD/edk2:$PWD/edk2-non-osi" +cd edk2 +export WORKSPACE=$PWD +. edksetup.sh +</code></pre> + </li> + <li>Windows: +<pre><code>set WORKSPACE=%CD% +set PACKAGES_PATH=%WORKSPACE%\edk2;%WORKSPACE%\edk2-non-osi +set EDK_TOOLS_BIN=%WORKSPACE%\edk2-BaseTools-win32 +cd edk2 +edksetup.bat +</code></pre> + </li> + </ul> + </li> +</ol> + + + +<hr> +<h1><a name="QuarkFsp">Quark™ FSP</a></h1> +<p> +Getting the Quark FSP source: +</p> +<ol> + <li>Set up an EDK-II <a href="#BuildEnvironment">Build Environment</a></li> + <li>cd edk2</li> + <li>mkdir QuarkFspPkg</li> + <li>cd QuarkFspPkg</li> + <li>Use git to clone <a target="_blank" href="https://review.gerrithub.io/#/admin/projects/LeeLeahy/quarkfsp">QuarkFspPkg</a> into the QuarkFpsPkg directory (.)</li> +</ol> + +<p> +Building QuarkFspPkg: +</p> +<ul> + <li>Linux: QuarkFspPkg/BuildFsp.sh -d32</li> + <li>Windows: QuarkFspPkg/BuildFsp.bat -d32</li> +</ul> + + + +<hr> +<h1>Quark™ EDK2 BIOS</h1> +<p> +Build Instructions: +</p> +<ol> + <li>Set up <a href="#BuildEnvironment">build environment</a></li> + <li>Build the image: + <ul> + <li>Linux: +<pre><code>build -p QuarkPlatformPkg/Quark.dsc -a IA32 -t GCC48 -b DEBUG -DDEBUG_PROPERTY_MASK=0x27 -DDEBUG_PRINT_ERROR_LEVEL=0x80000042 +ls Build/Quark/DEBUG_GCC48/FV/Quark.fd +</code></pre> + </li> + <li>Windows: +<pre><code>build -p QuarkPlatformPkg/Quark.dsc -a IA32 -t VS2012x86 -b DEBUG -DDEBUG_PROPERTY_MASK=0x27 -DDEBUG_PRINT_ERROR_LEVEL=0x80000042 +dir Build\Quark\DEBUG_VS2012x86\FV\Quark.fd +</code></pre> + </li> + </ul> + </li> +</ol> + +<p> +Documentation: +</p> +<ul> + <li><a target="_blank" href="https://github.com/tianocore/edk2/tree/master/QuarkPlatformPkg">EDK II firmware for Intel® Quark™ SoC X1000 based platforms</a></li> + <li>Intel® Quark™ SoC X1000 <a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/documents/guides/quark-x1000-uefi-firmware-writers-guide.pdf">UEFI Firmware Writer's Guide</a></li> +</ul> + + + +<hr> +<p>Modified: 17 May 2016</p> + </body> +</html> diff --git a/Documentation/backup-docs/old/Intel/SoC/soc.html b/Documentation/backup-docs/old/Intel/SoC/soc.html new file mode 100644 index 0000000..8f1d75c --- /dev/null +++ b/Documentation/backup-docs/old/Intel/SoC/soc.html @@ -0,0 +1,734 @@ +<!DOCTYPE html> +<html> + <head> + <title>SoC</title> + </head> + <body> + +<h1>x86 System on a Chip (SoC) Development</h1> +<p> + SoC development is best done in parallel with development for a specific + board. The combined steps are listed + <a target="_blank" href="../development.html">here</a>. + The development steps for the SoC are listed below: +</p> +<ol> + <li><a target="_blank" href="../fsp1_1.html#RequiredFiles">FSP 1.1</a> required files</li> + <li>SoC <a href="#RequiredFiles">Required Files</a></li> + <li><a href="#Descriptor">Start Booting</a></li> + <li><a href="#EarlyDebug">Early Debug</a></li> + <li><a href="#Bootblock">Bootblock</a></li> + <li><a href="#TempRamInit">TempRamInit</a></li> + <li><a href="#Romstage">Romstage</a> + <ol type="A"> + <li>Enable <a href="#SerialOutput">Serial Output"</a></li> + <li>Get the <a href="#PreviousSleepState">Previous Sleep State</a></li> + <li>Add the <a href="#MemoryInit">MemoryInit</a> Support</li> + <li>Disable the <a href="#DisableShadowRom">Shadow ROM</a></li> + </ol> + </li> + <li><a href="#Ramstage">Ramstage</a> + <ol type="A"> + <li><a href="#DeviceTree">Start Device Tree Processing</a></li> + <li>Set up the <a href="#MemoryMap">Memory Map"</a></li> + </ol> + </li> + <li><a href="#AcpiTables">ACPI Tables</a></li> + <li><a href="#LegacyHardware">Legacy Hardware</a></li> +</ol> + + +<hr> +<h1><a name="RequiredFiles">Required Files</a></h1> +<p> + Create the directory as src/soc/<Vendor>/<Chip Family>. +</p> + +<p> + The following files are required to build a new SoC: +</p> +<ul> + <li>Include files + <ul> + <li>include/soc/pei_data.h</li> + <li>include/soc/pm.h</li> + </ul> + </li> + <li>Kconfig - Defines the Kconfig value for the SoC and selects the tool + chains for the various stages: + <ul> + <li>select ARCH_BOOTBLOCK_<Tool Chain></li> + <li>select ARCH_RAMSTAGE_<Tool Chain></li> + <li>select ARCH_ROMSTAGE_<Tool Chain></li> + <li>select ARCH_VERSTAGE_<Tool Chain></li> + </ul> + </li> + <li>Makefile.inc - Specify the include paths</li> + <li>memmap.c - Top of usable RAM</li> +</ul> + + +<hr> +<h1><a name="Descriptor">Start Booting</a></h1> +<p> + Some SoC parts require additional firmware components in the flash. + This section describes how to add those pieces. +</p> + +<h2>Intel Firmware Descriptor</h2> +<p> + The Intel Firmware Descriptor (IFD) is located at the base of the flash part. + The following command overwrites the base of the flash image with the Intel + Firmware Descriptor: +</p> +<pre><code>dd if=descriptor.bin of=build/coreboot.rom conv=notrunc >/dev/null 2>&1</code></pre> + + +<h2><a name="MEB">Management Engine Binary</a></h2> +<p> + Some SoC parts contain and require that the Management Engine (ME) be running + before it is possible to bring the x86 processor out of reset. A binary file + containing the management engine code must be added to the firmware using the + ifdtool. The following commands add this binary blob: +</p> +<pre><code>util/ifdtool/ifdtool -i ME:me.bin build/coreboot.rom +mv build/coreboot.rom.new build/coreboot.rom +</code></pre> + + +<h2><a name="EarlyDebug">Early Debug</a></h2> +<p> + Early debugging between the reset vector and the time the serial port is enabled + is most easily done by writing values to port 0x80. +</p> + + +<h2>Success</h2> +<p> + When the reset vector is successfully invoked, port 0x80 will output the following value: +</p> +<ul> + <li>0x01: <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l45">POST_RESET_VECTOR_CORRECT</a> + - Bootblock successfully executed the + <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/16bit/reset16.inc;hb=HEAD#l4">reset vector</a> + and entered the 16-bit code at + <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/16bit/entry16.inc;hb=HEAD#l35">_start</a> + </li> +</ul> + + +<hr> +<h1><a name="Bootblock">Bootblock</a></h1> +<p> + Implement the bootblock using the following steps: +</p> +<ol> + <li>Create the directory as src/soc/<Vendor>/<Chip Family>/bootblock</li> + <li>Add the timestamp.inc file which initializes the floating point registers and saves + the initial timestamp. + </li> + <li>Add the bootblock.c file which: + <ol type="A"> + <li>Enables memory-mapped PCI config access</li> + <li>Updates the microcode by calling intel_update_microcode_from_cbfs</li> + <li>Enable ROM caching</li> + </ol> + </li> + <li>Edit the src/soc/<Vendor>/<Chip Family>/Kconfig file + <ol type="A"> + <li>Add the BOOTBLOCK_CPU_INIT value to point to the bootblock.c file</li> + <li>Add the CHIPSET_BOOTBLOCK_INCLUDE value to point to the timestamp.inc file</li> + </ol> + </li> + <li>Edit the src/soc/<Vendor>/<Chip Family>/Makefile.inc file + <ol type="A"> + <li>Add the bootblock subdirectory</li> + </ol> + </li> + <li>Edit the src/soc/<Vendor>/<Chip Family>/memmap.c file + <ol type="A"> + <li>Add the fsp/memmap.h include file</li> + <li>Add the mmap_region_granularity routine</li> + </ol> + </li> + <li>Add the necessary .h files to define the necessary values and structures</li> + <li>When successful port 0x80 will output the following values: + <ol type="A"> + <li>0x01: <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l45">POST_RESET_VECTOR_CORRECT</a> + - Bootblock successfully executed the + <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/16bit/reset16.inc;hb=HEAD#l4">reset vector</a> + and entered the 16-bit code at + <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/16bit/entry16.inc;hb=HEAD#l35">_start</a> + </li> + <li>0x10: <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l53">POST_ENTER_PROTECTED_MODE</a> + - Bootblock executing in + <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/32bit/entry32.inc;hb=HEAD#l55">32-bit mode</a> + </li> + <li>0x10 - Verstage/romstage reached 32-bit mode</li> + </ol> + </li> +</ol> + +<p> + <b>Build Note:</b> The following files are included into the default bootblock image: +</p> +<ul> + <li><a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/bootblock_romcc.S;hb=HEAD">src/arch/x86/bootblock_romcc.S</a> + added by <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/Makefile.inc;hb=HEAD#l133">src/arch/x86/Makefile.inc</a> + and includes the following files: + <ul> + <li><a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/prologue.inc">src/arch/x86/prologue.inc</a></li> + <li><a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/16bit/reset16.inc">src/cpu/x86/16bit/reset16.inc</a></li> + <li><a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/16bit/entry16.inc">src/cpu/x86/16bit/entry16.inc</a></li> + <li><a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/32bit/entry32.inc">src/cpu/x86/32bit/entry32.inc</a></li> + <li>The code in + <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/bootblock_romcc.S">src/arch/x86/bootblock_romcc.S</a> + includes src/soc/<Vendor>/<Chip Family>/bootblock/timestamp.inc using the + CONFIG_CHIPSET_BOOTBLOCK_INCLUDE value set above + </li> + <li><a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/sse_enable.inc">src/cpu/x86/sse_enable.inc</a></li> + <li>The code in + <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/Makefile.inc;hb=HEAD#l156">src/arch/x86/Makefile.inc</a> + invokes the ROMCC tool to convert the following "C" code into assembler as bootblock.inc: + <ul> + <li><a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/include/arch/bootblock_romcc.h">src/arch/x86/include/arch/bootblock_romcc.h</a></li> + <li><a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/lapic/boot_cpu.c">src/cpu/x86/lapic/boot_cpu.c</a></li> + <li>The CONFIG_BOOTBLOCK_CPU_INIT value set above typically points to the code in + src/soc/<Vendor>/<Chip Family>/bootblock/bootblock.c + </li> + </ul> + </li> + </ul> + </li> + <li><a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/id.S">src/arch/x86/id.S</a> + added by <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/Makefile.inc;hb=HEAD#l110">src/arch/x86/Makefile.inc</a> + </li> + <li><a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/intel/fit/fit.S">src/cpu/intel/fit/fit.S</a> + added by <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/intel/fit/Makefile.inc;hb=HEAD">src/cpu/intel/fit/Makefile.inc</a> + </li> + <li><a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/walkcbfs.S">src/arch/x86/walkcbfs.S</a> + added by <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/Makefile.inc;hb=HEAD#l137">src/arch/x86/Makefile.inc</a> + </li> +</ul> + + +<hr> +<h1><a name="TempRamInit">TempRamInit</a></h1> +<p> + Enable the call to TempRamInit in two stages: +</p> +<ol> + <li>Finding the FSP binary in the read-only CBFS region</li> + <li>Call TempRamInit</li> +</ol> + + +<h2>Find FSP Binary</h2> +<p> +Use the following steps to locate the FSP binary: +</p> +<ol> + <li>Edit the src/soc/<Vendor>/<Chip Family>/Kconfig file + <ol type="A"> + <li>Add "select USE_GENERIC_FSP_CAR_INC" to enable the use of + <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/cache_as_ram.inc">src/drivers/intel/fsp1_1/cache_as_ram.inc</a> + </li> + <li>Add "select SOC_INTEL_COMMON" to enable the use of the files from src/soc/intel/common + specifically building + <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/soc/intel/common/util.c">util.c</a> + </li> + </ol> + </li> + <li>Debug the result until port 0x80 outputs + <ol type="A"> + <li>0x90: <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l205">POST_FSP_TEMP_RAM_INIT</a> + - Just before calling + <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/cache_as_ram.inc;hb=HEAD#l73">TempRamInit</a> + </li> + <li>Alternating 0xba and 0x01 - The FSP image was not found</li> + </ol> + </li> + <li>Add the <a target="_blank" href="../fsp1_1.html#FspBinary">FSP binary file</a> to the flash image</li> + <li>Set the following Kconfig values: + <ul> + <li>CONFIG_FSP_LOC to the FSP base address specified in the previous step</li> + <li>CONFIG_FSP_IMAGE_ID_STRING</li> + </ul> + </li> + <li>Debug the result until port 0x80 outputs + <ol type="A"> + <li>0x90: <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l205">POST_FSP_TEMP_RAM_INIT</a> + - Just before calling + <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/cache_as_ram.inc;hb=HEAD#l73">TempRamInit</a> + </li> + <li>Alternating 0xbb and 0x02 - TempRamInit executed, no CPU microcode update found</li> + </ol> + </li> +</ol> + + +<h2>Calling TempRamInit</h2> +<p> +Use the following steps to debug the call to TempRamInit: +</p> +<ol> + <li>Add the CPU microcode update file + <ol type="A"> + <li>Add the microcode file with the following command +<pre><code>util/cbfstool/cbfstool build/coreboot.rom add -t microcode -n cpu_microcode_blob.bin -b <base address> -f cpu_microcode_blob.bin</code></pre> + </li> + <li>Set the Kconfig values + <ul> + <li>CONFIG_CPU_MICROCODE_CBFS_LOC set to the value from the previous step</li> + <li>CONFIG_CPU_MICROCODE_CBFS_LEN</li> + </ul> + </li> + </ol> + </li> + <li>Debug the result until port 0x80 outputs + <ol type="A"> + <li>0x90: <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l205">POST_FSP_TEMP_RAM_INIT</a> + - Just before calling + <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/cache_as_ram.inc;hb=HEAD#l73">TempRamInit</a> + </li> + <li>0x2A - Just before calling + <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/cache_as_ram.inc;hb=HEAD#l151">cache_as_ram_main</a> + which is the start of the verstage code which may be part of romstage + </li> + </ol> + </li> +</ol> + + +<hr> +<h1><a name="Romstage">Romstage</a></h1> + +<h2><a name="SerialOutput">Serial Output</a></h2> +<p> + The following steps add the serial output support for romstage: +</p> +<ol> + <li>Create the romstage subdirectory</li> + <li>Add romstage/romstage.c + <ol type="A"> + <li>Program the necessary base addresses</li> + <li>Disable the TCO</li> + </ol> + </li> + <li>Add romstage/Makefile.inc + <ol type="A"> + <li>Add romstage.c to romstage</li> + </ol> + </li> + <li>Add gpio configuration support if necessary</li> + <li>Add the necessary .h files to support the build</li> + <li>Update Makefile.inc + <ol type="A"> + <li>Add the romstage subdirectory</li> + <li>Add the gpio configuration support file to romstage</li> + </ol> + </li> + <li>Set the necessary Kconfig values to enable serial output: + <ul> + <li>CONFIG_DRIVERS_UART_<driver>=y</li> + <li>CONFIG_CONSOLE_SERIAL=y</li> + <li>CONFIG_UART_FOR_CONSOLE=<port></li> + <li>CONFIG_CONSOLE_SERIAL_115200=y</li> + </ul> + </li> +</ol> + + +<h2><a name="PreviousSleepState">Determine Previous Sleep State</a></h2> +<p> + The following steps implement the code to get the previous sleep state: +</p> +<ol> + <li>Implement the fill_power_state routine which determines the previous sleep state</li> + <li>Debug the result until port 0x80 outputs + <ol type="A"> + <li>0x32: + - Just after entering + <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/romstage.c;hb=HEAD#l99">romstage_common</a> + </li> + <li>0x33 - Just after calling + <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/romstage.c;hb=HEAD#l113">soc_pre_ram_init</a> + </li> + <li>0x34: + - Just after entering + <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/raminit.c;hb=HEAD#l67">raminit</a> + </li> + </ol> +</ol> + + +<h2><a name="MemoryInit">MemoryInit Support</a></h2> +<p> + The following steps implement the code to support the FSP MemoryInit call: +</p> +<ol> + <li>Add the chip.h header file to define the UPD values which get passed + to MemoryInit. Skip the values containing SPD addresses and DRAM + configuration data which is determined by the board. + <p> + <b>Build Note</b>: The src/mainboard/<Vendor>/<Board>/devicetree.cb + file specifies the default values for these parameters. The build + process creates the static.c module which contains the config data + structure containing these values. + </p> + </li> + <li>Edit romstage/romstage.c + <ol type="A"> + <li>Implement the romstage/romstage.c/soc_memory_init_params routine to + copy the values from the config structure into the UPD structure + </li> + <li>Implement the soc_display_memory_init_params routine to display + the updated UPD parameters by calling fsp_display_upd_value + </li> + </ol> + </li> +</ol> + + +<h2><a name="DisableShadowRom">Disable Shadow ROM</a></h2> +<p> + A shadow of the SPI flash part is mapped from 0x000e0000 to 0x000fffff. + This shadow needs to be disabled to allow RAM to properly respond to + this address range. +</p> +<ol> + <li>Edit romstage/romstage.c and add the soc_after_ram_init routine</li> +</ol> + + +<hr> +<h1><a name="Ramstage">Ramstage</a></h1> + +<h2><a name="DeviceTree">Start Device Tree Processing</a></h2> +<p> + The src/mainboard/<Vendor>/<Board>/devicetree.cb file drives the + execution during ramstage. This file is processed by the util/sconfig utility + to generate build/mainboard/<Vendor>/<Board>/static.c. The various + state routines in + src/lib/<a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/lib/hardwaremain.c;hb=HEAD#l128">hardwaremain.c</a> + call dev_* routines which use the tables in static.c to locate operation tables + associated with the various chips and devices. After location the operation + tables, the state routines call one or more functions depending upon the + state of the state machine. +</p> + +<h3><a name="ChipOperations">Chip Operations</a></h3> +<p> + Kick-starting the ramstage state machine requires creating the operation table + for the chip listed in devicetree.cb: +</p> +<ol> + <li>Edit src/soc/<SoC Vendor>/<SoC Family>/chip.c: + <ol type="A"> + <li> + This chip's operation table has the name + soc_<SoC Vendor>_<SoC Family>_ops which is derived from the + chip path specified in the devicetree.cb file. + </li> + <li>Use the CHIP_NAME macro to specify the name for the chip</li> + <li>For FSP 1.1, specify a .init routine which calls intel_silicon_init</li> + </ol> + </li> + <li>Edit src/soc/<SoC Vendor>/<SoC Family>/Makefile.inc and add chip.c to ramstage</li> +</ol> + +<h3>Domain Operations</h3> +<p> + coreboot uses the domain operation table to initiate operations on all of the + devices in the domain. By default coreboot enables all PCI devices which it + finds. Listing a device in devicetree.cb gives the board vendor control over + the device state. Non-PCI devices may also be listed under PCI device such as + the LPC bus or SMbus devices. +</p> +<ol> + <li>Edit src/soc/<SoC Vendor>/<SoC Family>/chip.c: + <ol type="A"> + <li> + The domain operation table is typically placed in + src/soc/<SoC Vendor>/<SoC Family>/chip.c. + The table typically looks like the following: +<pre><code>static struct device_operations pci_domain_ops = { + .read_resources = pci_domain_read_resources, + .set_resources = pci_domain_set_resources, + .scan_bus = pci_domain_scan_bus, + .ops_pci_bus = pci_bus_default_ops, +}; +</code></pre> + </li> + <li> + Create a .enable_dev entry in the chip operations table which points to a + routine which sets the domain table for the device with the DEVICE_PATH_DOMAIN. +<pre><code> if (dev->path.type == DEVICE_PATH_DOMAIN) { + dev->ops = &pci_domain_ops; + } +</code></pre> + </li> + <li> + During the BS_DEV_ENUMERATE state, ramstage now display the device IDs + for the PCI devices on the bus. + </li> + </ol> + </li> + <li>Set CONFIG_DEBUG_BOOT_STATE=y in the .config file</li> + <li> + Debug the result until the PCI vendor and device IDs are displayed + during the BS_DEV_ENUMERATE state. + </li> +</ol> + + +<h2><a name="DeviceDrivers">PCI Device Drivers</a></h2> +<p> + PCI device drivers consist of a ".c" file which contains a "pci_driver" data + structure at the end of the file with the attribute tag "__pci_driver". This + attribute tag places an entry into a link time table listing the various + coreboot device drivers. +</p> +<p> + Specify the following fields in the table: +</p> +<ol> + <li>.vendor - PCI vendor ID value of the device</li> + <li>.device - PCI device ID value of the device or<br> + .devices - Address of a zero terminated array of PCI device IDs + </li> + <li>.ops - Operations table for the device. This is the address + of a "static struct device_operations" data structure specifying + the routines to execute during the different states and sub-states + of ramstage's processing. + </li> + <li>Turn on the device in mainboard/<Vendor>/<Board>/devicetree.cb</li> + <li> + Debug until the device is on and properly configured in coreboot and + usable by the payload + </li> +</ol> + +<h3><a name="SubsystemIds">Subsystem IDs</a></h3> +<p> + PCI subsystem IDs are assigned during the BS_DEV_ENABLE state. The device + driver may use the common mechanism to assign subsystem IDs by adding + the ".ops_pci" to the pci_driver data structure. This field points to + a "struct pci_operations" that specifies a routine to set the subsystem + IDs for the device. The routine might look something like this: +</p> +<pre><code>static void pci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +{ + if (!vendor || !device) { + vendor = pci_read_config32(dev, PCI_VENDOR_ID); + device = vendor >> 16; + } + printk(BIOS_SPEW, + "PCI: %02x:%02x:%d subsystem vendor: 0x%04x, device: 0x%04x\n", + 0, PCI_SLOT(dev->path.pci.devfn), PCI_FUNC(dev->path.pci.devfn), + vendor & 0xffff, device); + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + ((device & 0xffff) << 16) | (vendor & 0xffff)); +} +</code></pre> + + + +<h2>Set up the <a name="MemoryMap">Memory Map</a></h2> +<p> + The memory map is built by the various PCI device drivers during the + BS_DEV_RESOURCES state of ramstage. The northcluster driver will typically + specify the DRAM resources while the other drivers will typically specify + the IO resources. These resources are hung off the device_t data structure by + src/device/device_util.c/<a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/device/device_util.c;hb=HEAD#l448">new_resource</a>. +</p> +<p> + During the BS_WRITE_TABLES state, coreboot collects these resources and + places them into a data structure identified by LB_MEM_TABLE. +</p> +<p> + Edit the device driver file: +</p> +<ol> + <li> + Implement a read_resources routine which calls macros defined in + src/include/device/<a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/device/device.h;hb=HEAD#l237">device.h</a> + like: + <ul> + <li>ram_resource</li> + <li>reserved_ram_resource</li> + <li>bad_ram_resource</li> + <li>uma_resource</li> + <li>mmio_resource</li> + </ul> + </li> +</ol> + +<p> + Testing: Verify that the resources are properly displayed by coreboot during the BS_WRITE_TABLES state. +</p> + + + +<hr> +<h1><a name="AcpiTables">ACPI Tables</a></h1> +<p> + One of the payloads that needs ACPI tables is the EDK2 <a target="_blank" href="quark.html#CorebootPayloadPkg">CorebootPayloadPkg</a>. +</p> + +<h2>FADT</h2> +<p> + The EDK2 module + CorebootModulePkg/Library/CbParseLib/<a target="_blank" href="https://github.com/tianocore/edk2/blob/master/CorebootModulePkg/Library/CbParseLib/CbParseLib.c#l450">CbParseLib.c</a> + requires that the FADT contains the values in the table below. + These values are placed into a HOB identified by + <a target="_blank" href="https://github.com/tianocore/edk2/blob/master/CorebootModulePkg/CorebootModulePkg.dec#l36">gUefiAcpiBoardInfoGuid</a> + by routine + CorebootModulePkg/CbSupportPei/CbSupportPei/<a target="_blank" href="https://github.com/tianocore/edk2/blob/master/CorebootModulePkg/CbSupportPei/CbSupportPei.c#l364">CbPeiEntryPoint</a>. +</p> +<table border="1"> + <tr bgcolor="#c0ffc0"> + <td>Coreboot Field</td> + <td>EDK2 Field</td> + <td>gUefiAcpiBoardInfoGuid</td> + <td>Use</li> + <td> + <a target="_blank" href="http://www.uefi.org/sites/default/files/resources/ACPI_6.0.pdf">ACPI Spec.</a> + Section + </td> + </tr> + <tr> + <td>gpe0_blk<br>gpe0_blk_len</td> + <td>Gpe0Blk<br>Gpe0BlkLen</td> + <td> + <a target="_blank" href="https://github.com/tianocore/edk2/blob/master/CorebootModulePkg/Library/CbParseLib/CbParseLib.c#l477">PmGpeEnBase</a> + </td> + <td><a target="_blank" href="https://github.com/tianocore/edk2/blob/master/CorebootPayloadPkg/Library/ResetSystemLib/ResetSystemLib.c#l129">Shutdown</a></td> + <td>4.8.4.1</td> + </tr> + <tr> + <td>pm1a_cnt_blk</td> + <td>Pm1aCntBlk</td> + <td>PmCtrlRegBase</td> + <td> + <a target="_blank" href="https://github.com/tianocore/edk2/blob/master/CorebootPayloadPkg/Library/ResetSystemLib/ResetSystemLib.c#l139">Shutdown</a><br> + <a target="_blank" href="https://github.com/tianocore/edk2/blob/master/CorebootPayloadPkg/Library/ResetSystemLib/ResetSystemLib.c#l40">Suspend</a> + </td> + <td>4.8.3.2.1</td> + </tr> + <tr> + <td>pm1a_evt_blk</td> + <td>Pm1aEvtBlk</td> + <td>PmEvtBase</td> + <td><a target="_blank" href="https://github.com/tianocore/edk2/blob/master/CorebootPayloadPkg/Library/ResetSystemLib/ResetSystemLib.c#l134">Shutdown</a></td> + <td>4.8.3.1.1</td> + </tr> + <tr> + <td>pm_tmr_blk</td> + <td>PmTmrBlk</td> + <td>PmTimerRegBase</td> + <td> + <a target="_blank" href="https://github.com/tianocore/edk2/blob/master/CorebootPayloadPkg/Library/AcpiTimerLib/AcpiTimerLib.c#l55">Timer</a> + </td> + <td>4.8.3.3</td> + </tr> + <tr> + <td>reset_reg.</td> + <td>ResetReg.Address</td> + <td>ResetRegAddress</td> + <td> + <a target="_blank" href="https://github.com/tianocore/edk2/blob/master/CorebootPayloadPkg/Library/ResetSystemLib/ResetSystemLib.c#l71">Cold</a> + and + <a target="_blank" href="https://github.com/tianocore/edk2/blob/master/CorebootPayloadPkg/Library/ResetSystemLib/ResetSystemLib.c#l98">Warm</a> + resets + </td> + <td>4.3.3.6</td> + </tr> + <tr> + <td>reset_value</td> + <td>ResetValue</td> + <td>ResetValue</td> + <td> + <a target="_blank" href="https://github.com/tianocore/edk2/blob/master/CorebootPayloadPkg/Library/ResetSystemLib/ResetSystemLib.c#l71">Cold</a> + and + <a target="_blank" href="https://github.com/tianocore/edk2/blob/master/CorebootPayloadPkg/Library/ResetSystemLib/ResetSystemLib.c#l98">Warm</a> + resets + </td> + <td>4.8.3.6</td> + </tr> +</table> +<p> + The EDK2 data structure is defined in + MdeModulePkg/Include/IndustryStandard/<a target="_blank" href="https://github.com/tianocore/edk2/blob/master/MdePkg/Include/IndustryStandard/Acpi61.h#l111">Acpi61.h</a> + The coreboot data structure is defined in + src/arch/x86/include/arch/<a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/include/arch/acpi.h;hb=HEAD#l237">acpi.h</a> +</p> + +<ol> + <li> + Select <a target="_blank" href="../Board/board.html#AcpiTables">HAVE_ACPI_TABLES</a> + in the board's Kconfig file + </li> + <li>Create a acpi.c module: + <ol type="A"> + <li>Add the acpi_fill_in_fadt routine and initialize the values above</li> + </ol> + </li> +</ol> + + + +<hr> +<h1><a name="LegacyHardware">Legacy Hardware</a></h1> +<p> + One of the payloads that needs legacy hardare is the EDK2 <a target="_blank" href="quark.html#CorebootPayloadPkg">CorebootPayloadPkg</a>. +</p> + +<table border="1"> + <tr bgcolor="c0ffc0"> + <th>Peripheral</th> + <th>Use</th> + <th>8259 Interrupt Vector</th> + <th>IDT Base Offset</th> + <th>Interrupt Handler</th> + </tr> + <tr> + <td> + <a target="_blank" href="http://www.scs.stanford.edu/10wi-cs140/pintos/specs/8254.pdf">8254</a> + Programmable Interval Timer + </td> + <td> + EDK2: PcAtChipsetPkg/8254TimerDxe/<a target="_blank" href="https://github.com/tianocore/edk2/blob/master/PcAtChipsetPkg/8254TimerDxe/Timer.c">Timer.c</a> + </td> + <td>0</td> + <td>0x340</td> + <td> + <a target="_blank" href="https://github.com/tianocore/edk2/blob/master/PcAtChipsetPkg/8254TimerDxe/Timer.c#l71">TimerInterruptHandler</a> + </td> + </tr> + <tr> + <td> + <a target="_blank" href="https://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=1&cad=rja&uact=8&ved=0ahUKEwibxYKU3ZDLAhVOzWMKHfuqB40QFggcMAA&url=http%3A%2F%2Fbochs.sourceforge.net%2Ftechspec%2Fintel-8259a-pic.pdf.gz&usg=AFQjCNF1NT0OQ6ys1Pn6Iv9sv6cKRzZbGg&sig2=HfBszp9xTVO_fajjPWCsJw">8259</a> + Programmable Interrupt Controller + </td> + <td> + EDK2: PcAtChipsetPkg/8259InterruptControllerDxe/<a target="_blank" href="https://github.com/tianocore/edk2/blob/master/PcAtChipsetPkg/8259InterruptControllerDxe/8259.c">8259.c</a> + </td> + <td> + Master interrupts: 0, 2 - 7<br> + Slave interrupts: 8 - 15<br> + Interrupt vector 1 is never generated, the cascaded input generates interrupts 8 - 15 + </td> + <td> + Master: 0x340, 0x350 - 0x378<br> + Slave: 0x380 - 0x3b8<br> + Interrupt descriptors are 8 bytes each + </td> + <td> </td> + </tr> +</table> + +<hr> +<p>Modified: 4 March 2016</p> + </body> +</html> \ No newline at end of file diff --git a/Documentation/backup-docs/old/Intel/development.html b/Documentation/backup-docs/old/Intel/development.html new file mode 100644 index 0000000..a2ba278 --- /dev/null +++ b/Documentation/backup-docs/old/Intel/development.html @@ -0,0 +1,377 @@ +<!DOCTYPE html> +<html> + <head> + <title>Development</title> + </head> + <body> + +<h1>Intel® x86 coreboot/FSP Development Process</h1> +<p> + The x86 development process for coreboot is broken into the following components: +</p> +<ul> + <li>coreboot <a target="_blank" href="SoC/soc.html">SoC</a> development</li> + <li>coreboot <a target="_blank" href="Board/board.html">mainboard</a> development</li> + <li><a target="_blank" href="fsp1_1.html">FSP 1.1</a> integration</li> +</ul> +<p> + The development process has two main phases: +</p> +<ol> + <li>Minimal coreboot; This phase is single threaded</li> + <li>Adding coreboot features</li> +</ol> + +<h2>Minimal coreboot</h2> +<p> + The combined steps below describe how to bring up a minimal coreboot for a + system-on-a-chip (SoC) and a development board: +</p> +<table> + <tr bgcolor="#ffffc0"> + <td>The initial coreboot steps are single threaded! + The initial minimal FSP development is also single threaded. + Progress can speed up by adding more developers after the minimal coreboot/FSP + implementation reaches the payload. + </td> + </tr> +</table> +<ol> + <li>Get the necessary tools: + <ul> + <li>Linux: Use your package manager to install m4 bison flex and the libcurses development + package. + <ul> + <li>Ubuntu or other Linux distribution that use apt, run: +<pre><code>sudo apt-get install m4 bison flex libncurses5-dev +</code></pre> + </li> + </ul> + </li> + </ul> + </li> + <li>Build the cross tools for i386: + <ul> + <li>Linux: +<pre><code>make crossgcc-i386</code></pre> + To use multiple processors for the toolchain build (which takes a long time), use: +<pre><code>make crossgcc-i386 CPUS=N</code></pre> + where N is the number of cores to use for the build. + </li> + </ul> + </li> + <li>Get something to build: + <ol type="A"> + <li><a target="_blank" href="fsp1_1.html#RequiredFiles">FSP 1.1</a> required files</li> + <li><a target="_blank" href="SoC/soc.html#RequiredFiles">SoC</a> required files</li> + <li><a target="_blank" href="Board/board.html#RequiredFiles">Board</a> required files</li> + </ol> + </li> + <li>Get result to start <a target="_blank" href="SoC/soc.html#Descriptor">booting</a></li> + <li><a target="_blank" href="SoC/soc.html#EarlyDebug">Early Debug</a></li> + <li>Implement and debug the <a target="_blank" href="SoC/soc.html#Bootblock">bootblock</a> code</li> + <li>Implement and debug the call to <a target="_blank" href="SoC/soc.html#TempRamInit">TempRamInit</a></li> + <li>Enable the serial port + <ol type="A"> + <li>Power on, enable and configure GPIOs for the + <a target="_blank" href="Board/board.html#SerialOutput">debug serial UART</a> + </li> + <li>Add the <a target="_blank" href="SoC/soc.html#SerialOutput">serial outupt</a> + support to romstage + </li> + </ol> + </li> + <li>Enable <a target="_blank" href="fsp1_1.html#corebootFspDebugging">coreboot/FSP</a> debugging</li> + <li>Determine the <a target="_blank" href="SoC/soc.html#PreviousSleepState">Previous Sleep State</a></li> + <li>Enable DRAM: + <ol type="A"> + <li>Implement the SoC + <a target="_blank" href="SoC/soc.html#MemoryInit">MemoryInit</a> + Support + </li> + <li>Implement the board support to read the + <a target="_blank" href="Board/board.html#SpdData">Memory Timing Data</a> + </li> + </ol> + </li> + <li>Disable the + <a target="_blank" href="SoC/soc.html#DisableShadowRom">Shadow ROM</a> + </li> + <li>Enable CONFIG_DISPLAY_MTRRS to verify the MTRR configuration</li> + <li> + Implement the .init routine for the + <a target="_blank" href="SoC/soc.html#ChipOperations">chip operations</a> + structure which calls FSP SiliconInit + </li> + <li> + Start ramstage's + <a target="_blank" href="SoC/soc.html#DeviceTree">device tree processing</a> + to display the PCI vendor and device IDs + </li> + <li> + Disable the + <a target="_blank" href="Board/board.html#DisablePciDevices">PCI devices</a> + </li> + <li> + Implement the + <a target="_blank" href="SoC/soc.html#MemoryMap">memory map</a> + </li> + <li>coreboot should now attempt to load the payload</li> +</ol> + + + +<h2>Add coreboot Features</h2> +<p> + Most of the coreboot development gets done in this phase. Implementation tasks in this + phase are easily done in parallel. +</p> +<ul> + <li>Payload and OS Features: + <ul> + <li><a target="_blank" href="SoC/soc.html#AcpiTables">ACPI Tables</a></li> + <li><a target="_blank" href="SoC/soc.html#LegacyHardware">Legacy hardware</a> support</li> + </ul> + </li> +</ul> + + + +<hr> +<table border="1"> + <tr bgcolor="#c0ffc0"> + <th colspan=3><h1>Features</h1></th> + </tr> + <tr bgcolor="#c0ffc0"> + <th>SoC</th> + <th>Where</th> + <th>Testing</th> + </tr> + <tr> + <td>8254 Programmable Interval Timer</td> + <td><a target="_blank" href="SoC/soc.html#LegacyHardware">Legacy hardware</a> support</td> + <td><a target="_blank" href="SoC/quark.html#CorebootPayloadPkg">CorebootPayloadPkg</a> gets to shell prompt</td> + </tr> + <tr> + <td>8259 Programmable Interrupt Controller</td> + <td><a target="_blank" href="SoC/soc.html#LegacyHardware">Legacy hardware</a> support</td> + <td><a target="_blank" href="SoC/quark.html#CorebootPayloadPkg">CorebootPayloadPkg</a> gets to shell prompt</td> + </tr> + <tr> + <td>Cache-as-RAM</td> + <td> + <a target="_blank" href="SoC/soc.html#TempRamInit">Find</a> + FSP binary: + <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/cache_as_ram.inc;hb=HEAD#l38">cache_as_ram.inc</a><br> + Enable: FSP 1.1 <a target="_blank" href="SoC/soc.html#TempRamInit">TempRamInit</a> + called from + <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/cache_as_ram.inc;hb=HEAD#l73">cache_as_ram.inc</a><br> + Disable: FSP 1.1 TempRamExit called from + <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/after_raminit.S;hb=HEAD#l41">after_raminit.S</a><br> + </td> + <td>FindFSP: POST code 0x90 + (<a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l205">POST_FSP_TEMP_RAM_INIT</a>) + is displayed<br> + Enable: POST code + <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/cache_as_ram.inc;hb=HEAD#l151">0x2A</a> + is displayed<br> + Disable: CONFIG_DISPLAY_MTRRS=y, MTRRs displayed after call to TempRamExit + </td> + </tr> + <tr> + <td>Memory Map</td> + <td> + Implement a device driver for the + <a target="_blank" href="SoC/soc.html#MemoryMap">north cluster</a> + </td> + <td>coreboot displays the memory map correctly during the BS_WRITE_TABLES state</td> + </tr> + <tr> + <td>MTRRs</td> + <td> + Set values: src/drivers/intel/fsp1_1/stack.c/<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/stack.c;hb=HEAD#l42">setup_stack_and_mtrrs</a><br> + Load values: src/drivers/intel/fsp1_1/<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/after_raminit.S;hb=HEAD#l71">after_raminit.S</a> + </td> + <td>Set: Post code 0x91 + (<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l213">POST_FSP_TEMP_RAM_EXIT</a>) + is displayed by + <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/after_raminit.S;hb=HEAD#l41">after_raminit.S</a><br> + Load: Post code 0x3C is displayed by + <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/after_raminit.S;hb=HEAD#l152">after_raminit.S</a><br> + and CONFIG_DISPLAY_MTRRS=y displays the correct memory regions</td> + </tr> + <tr> + <td>PCI Device Support</td> + <td>Implement a PCI <a target="_blank" href="SoC/soc.html#DeviceDrivers">device driver</a></td> + <td>The device is detected by coreboot and usable by the payload</td> + </tr> + <tr> + <td>Ramstage state machine</td> + <td> + Implement the chip and domain operations to start the + <a target="_blank" href="SoC/soc.html#DeviceTree">device tree</a> + processing + </td> + <td> + During the BS_DEV_ENUMERATE state, ramstage now display the device IDs + for the PCI devices on the bus. + </td> + </tr> + <tr> + <td>ROM Shadow<br>0x000E0000 - 0x000FFFFF</td> + <td> + Disable: src/soc/<Vendor>/<Chip Family>/romstage/romstage.c/<a target="_blank" href="SoC/soc.html#DisableShadowRom">soc_after_ram_init routine</a> + </td> + <td>Operates as RAM: Writes followed by a read to the 0x000E0000 - 0x000FFFFF region returns the value written</td> + </tr> + + + <tr bgcolor="#c0ffc0"> + <th>Board</th> + <th>Where</th> + <th>Testing</th> + </tr> + <tr> + <td>Device Tree</td> + <td> + <a target="_blank" href="SoC/soc.html#DeviceTree">List</a> PCI vendor and device IDs by starting + the device tree processing<br> + <a target="_blank" href="Board/board.html#DisablePciDevices">Disable</a> PCI devices<br> + Enable: Implement a PCI <a target="_blank" href="SoC/soc.html#DeviceDrivers">device driver</a> + <td> + List: BS_DEV_ENUMERATE state displays PCI vendor and device IDs<br> + Disable: BS_DEV_ENUMERATE state shows the devices as disabled<br> + Enable: BS_DEV_ENUMERATE state shows the device as on and the device works for the payload + </td> + </tr> + <tr> + <td>DRAM</td> + <td> + Load SPD data: src/soc/mainboard/<Vendor>/<Board>/spd/<a target="_blank" href="Board/board.html#SpdData">spd.c</a><br> + UPD Setup: + <ul> + <li>src/soc<Vendor>//<Chip Family>/romstage/<a target="_blank" href="SoC/soc.html#MemoryInit">romstage.c</a></li> + <li>src/mainboard/<Vendor>/<Board>/<a target="_blank" href="Board/board.html#SpdData">romstage.c</a></li> + </ul> + FSP 1.1 MemoryInit called from src/drivers/intel/fsp1_1/<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/raminit.c;hb=HEAD#l126">raminit.c</a> + </td> + <td>Select the following Kconfig values + <ul> + <li>DISPLAY_HOBS</li> + <li>DISPLAY_UPD_DATA</li> + </ul> + Testing successful if: + <ul> + <li>MemoryInit UPD values are correct</li> + <li>MemoryInit returns 0 (success) and</li> + <li>The the message "ERROR - coreboot's requirements not met by FSP binary!" + is not displayed + </li> + </ul> + </td> + </tr> + <tr> + <td>Serial Port</td> + <td> + SoC <a target="_blank" href="SoC/soc.html#SerialOutput">Support</a><br> + Enable: src/soc/mainboard/<Board>/com_init.c/<a target="_blank" href="Board/board.html#SerialOutput">car_mainboard_pre_console_init</a> + </td> + <td>Debug serial output works</td> + </tr> + + + <tr bgcolor="#c0ffc0"> + <th>Payload</th> + <th>Where</th> + <th>Testing</th> + </tr> + <tr> + <td>ACPI Tables</td> + <td> + SoC <a target="_blank" href="SoC/soc.html#AcpiTables">Support</a><br> + </td> + <td>Verified by payload or OS</td> + </tr> + + + <tr bgcolor="#c0ffc0"> + <th>FSP</th> + <th>Where</th> + <th>Testing</th> + </tr> + <tr> + <td>TempRamInit</td> + <td>FSP <a target="_blank" href="SoC/soc.html#TempRamInit">TempRamInit</a></td> + <td>FSP binary found: POST code 0x90 + (<a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l205">POST_FSP_TEMP_RAM_INIT</a>) + is displayed<br> + TempRamInit successful: POST code + <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/cache_as_ram.inc;hb=HEAD#l151">0x2A</a> + is displayed<br> + </td> + </tr> + <tr> + <td>MemoryInit</td> + <td><a target="_blank" href="SoC/soc.html#MemoryInit">SoC</a> support<br> + <a target="_blank" href="Board/board.html#SpdData">Board</a> support<br> + </td> + <td>Select the following Kconfig values + <ul> + <li>DISPLAY_HOBS</li> + <li>DISPLAY_UPD_DATA</li> + </ul> + Testing successful if: + <ul> + <li>MemoryInit UPD values are correct</li> + <li>MemoryInit returns 0 (success) and</li> + <li>The the message "ERROR - coreboot's requirements not met by FSP binary!" + is not displayed + </li> + </ul> + </td> + </tr> + <tr> + <td>TempRamExit</td> + <td>src/drivers/intel/fsp1_1/<a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/after_raminit.S;hb=HEAD#l51">after_raminit.S</a></td> + <td>Post code 0x91 + (<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l212">POST_FSP_TEMP_RAM_EXIT</a>) + is displayed before calling TempRamExit by + <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/after_raminit.S;hb=HEAD#l141">after_raminit.S</a>, + CONFIG_DISPLAY_MTRRS=y displays the correct memory regions and + Post code 0x39 is displayed by + <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/after_raminit.S;hb=HEAD#l141">after_raminit.S</a><br> + </td> + </tr> + <tr> + <td>SiliconInit</td> + <td> + Implement the .init routine for the + <a target="_blank" href="SoC/soc.html#ChipOperations">chip operations</a> structure + </td> + <td>During BS_DEV_INIT_CHIPS state, SiliconInit gets called and returns 0x00000000</td> + </tr> + <tr> + <td>FspNotify</td> + <td> + The code which calls FspNotify is located in + src/drivers/intel/fsp1_1/<a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/fsp_util.c;hb=HEAD#l182">fsp_util.c</a>. + The fsp_notify_boot_state_callback routine is called three times as specified + by the BOOT_STATE_INIT_ENTRY macros below the routine. + </td> + <td> + The FspNotify routines are called during: + <ul> + <li>BS_DEV_RESOURCES - on exit</li> + <li>BS_PAYLOAD_LOAD - on exit</li> + <li>BS_OS_RESUME - on entry (S3 resume)</li> + </ul> + </td> + </tr> +</table> + + + +<hr> +<p>Modified: 4 March 2016</p> + </body> +</html> \ No newline at end of file diff --git a/Documentation/backup-docs/old/Intel/fsp1_1.html b/Documentation/backup-docs/old/Intel/fsp1_1.html new file mode 100644 index 0000000..1e1e88f --- /dev/null +++ b/Documentation/backup-docs/old/Intel/fsp1_1.html @@ -0,0 +1,77 @@ +<!DOCTYPE html> +<html> + <head> + <title>FSP 1.1</title> + </head> + <body> + +<h1>x86 FSP 1.1 Integration</h1> +<p> + Firmware Support Package (FSP) integration requires System-on-a-Chip (SoC) + and board support. The combined steps are listed + <a target="_blank" href="development.html">here</a>. + The development steps for FSP are listed below: +</p> +<ol> + <li><a href="#RequiredFiles">Required Files</a></li> + <li>Add the <a href="#FspBinary">FSP Binary File</a> to the coreboot File System</li> + <li>Enable <a href="#corebootFspDebugging">coreboot/FSP Debugging</a></li> +</ol> + +<p> + FSP Documentation: +</p> +<ul> + <li>Intel® Firmware Support Package External Architecture Specification <a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/fsp-architecture-spec-v1-1.pdf">V1.1</a></li> +</ul> + +<hr> +<h1><a name="RequiredFiles">Required Files</a></h1> +<h2><a name="corebootRequiredFiles">coreboot Required Files</a></h2> +<ol> + <li>Create the following directories if they do not already exist: + <ul> + <li>src/vendorcode/intel/fsp/fsp1_1/<Chip Family></li> + <li>3rdparty/blobs/mainboard/<Board Vendor>/<Board Name></li> + </ul> + </li> + <li> + The following files may need to be copied from the FSP build or release into the + directories above if they are not present or are out of date: + <ul> + <li>FspUpdVpd.h: src/vendorcode/intel/fsp/fsp1_1/<Chip Family>/FspUpdVpd.h</li> + <li>FSP.bin: 3rdparty/blobs/mainboard/<Board Vendor>/<Board Name>/fsp.bin</li> + </ul> + </li> +</ol> + + +<hr> +<h1><a name="FspBinary">Add the FSP Binary File to coreboot File System</a></h1> +<p> + Add the FSP binary to the coreboot flash image using the following command: +</p> +<pre><code>util/cbfstool/cbfstool build/coreboot.rom add -t fsp -n fsp.bin -b <base address> -f fsp.bin</code></pre> +<p> + This command relocates the FSP binary to the 4K byte aligned location in CBFS so that the + FSP code for TempRamInit may be executed in place. +</p> + + +<hr> +<h1><a name="corebootFspDebugging">Enable coreboot/FSP Debugging</a></h1> +<p> + Set the following Kconfig values: +</p> +<ul> + <li>CONFIG_DISPLAY_FSP_ENTRY_POINTS - Display the FSP entry points in romstage</li> + <li>CONFIG_DISPLAY_HOBS - Display and verify the hand-off-blocks (HOBs) returned by MemoryInit</li> + <li>CONFIG_DISPLAY_VBT - Display Video BIOS Table (VBT) used for GOP</li> + <li>CONFIG_DISPLAY_UPD_DATA - Display the user specified product data passed to MemoryInit and SiliconInit</li> +</ul> + + +<hr> +<p>Modified: 17 May 2016</p> + </body> +</html> diff --git a/Documentation/backup-docs/old/Intel/index.html b/Documentation/backup-docs/old/Intel/index.html new file mode 100644 index 0000000..cabcbff --- /dev/null +++ b/Documentation/backup-docs/old/Intel/index.html @@ -0,0 +1,86 @@ +<!DOCTYPE html> +<html> + <head> + <title>Intel® x86</title> + </head> + <body> + +<h1>Intel® x86 Boards</h1> +<ul> + <li><a target="_blank" href="Board/galileo.html">Galileo</a></li> + <li><a target="_blank" href="http://wiki.minnowboard.org/Coreboot">MinnowBoard MAX</a></li> +</ul> + + + +<h1>Intel® x86 SoCs</h1> +<ul> + <li><a target="_blank" href="SoC/quark.html">Quark™</a></li> +</ul> + + + +<hr> +<h1>x86 coreboot Development</h1> +<ul> + <li>Get the <a target="_blank" href="https://www.coreboot.org/Git">coreboot source</li> + <li><a target="_blank" href="development.html">Overall</a> development</li> + <li><a target="_blank" href="fsp1_1.html">FSP 1.1</a> integration + </li> + <li><a target="_blank" href="SoC/soc.html">SoC</a> support</li> + <li><a target="_blank" href="Board/board.html">Board</a> support</li> +</ul> + + + +<hr> +<h1>Payload Development</h1> +<ul> + <li><a target="_blank" href="SoC/quark.html#CorebootPayloadPkg">CorebootPayloadPkg</a> + <ul> + <li><a target="_blank" href="https://github.com/tianocore/tianocore.github.io/wiki/EDK-II-Development-Process">EDK II Development Process</a></li> + <li>EDK II <a target="_blank" href="https://github.com/tianocore/tianocore.github.io/wiki/EDK%20II%20White%20papers">White Papers</a></li> + <li><a target="_blank" href="https://github.com/tianocore/tianocore.github.io/wiki/SourceForge-to-Github-Quick-Start">SourceForge to Github Quick Start</a></li> + <li>UEFI <a target="_blank" href="http://www.uefi.org/sites/default/files/resources/UEFI%20Spec%202_5_Errata_A.PDF">2.5 Errata A</a></li> + </ul> + </li> +</ul> + + + +<hr> +<h1><a name="Documentation">Documentation</a></h1> +<ul> + <li><a target="_blank" href="http://www.uefi.org/specifications">ACPI Specifications</a></li> + <li>Intel® 64 and IA-32 Architectures <a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-manual-325462.pdf">Software Developer Manual</a></li> + <li><a target="_blank" href="http://www.uefi.org/specifications">UEFI Specifications</a></li> +</ul> + +<h2><a name="Edk2Documentation">EDK-II Documentation</a></h2> +<ul> + <li>Build <a target="_blank" href="https://github.com/tianocore-docs/Docs/raw/master/Specifications/Build_Spec_1_26.pdf">V1.26</a></li> + <li>Coding Standards <a target="_blank" href="https://github.com/tianocore-docs/Docs/raw/master/Specifications/CCS_2_1_Draft.pdf">V2.1</a></li> + <li>DEC <a target="_blank" href="https://github.com/tianocore-docs/Docs/raw/master/Specifications/DEC_Spec_1_25.pdf">V1.25</a></li> + <li>DSC <a target="_blank" href="https://github.com/tianocore-docs/Docs/raw/master/Specifications/DSC_Spec_1_26.pdf">V1.26</a></li> + <li><a target="_blank" href="https://github.com/tianocore/tianocore.github.io/wiki/UEFI-Driver-Writer's-Guide">Driver Writer's Guide</a></li> + <li>Expression Syntax <a target="_blank" href="https://github.com/tianocore-docs/Docs/raw/master/Specifications/ExpressionSyntax_1.1.pdf">V1.1</a></li> + <li>FDF <a target="_blank" href="https://github.com/tianocore-docs/Docs/raw/master/Specifications/FDF_Spec_1_26.pdf">V1.26</a></li> + <li>INF <a target="_blank" href="https://github.com/tianocore-docs/Docs/raw/master/Specifications/INF_Spec_1_25.pdf">V1.25</a></li> + <li>PCD <a target="_blank" href="https://github.com/tianocore-docs/Docs/raw/master/Specifications/PCD_Infrastructure.pdf">PCD</a>V0.55</li> + <li>UNI <a target="_blank" href="https://github.com/tianocore-docs/Docs/raw/master/Specifications/UNI_File_Spec_v1_2_Errata_A.pdf">V1.2 Errata A</a></li> + <li>VRF <a target="_blank" href="https://github.com/tianocore-docs/Docs/raw/master/Specifications/VFR_1_9.pdf">V1.9</a></li> +</ul> + +<h2><a name="FspDocumentation">FSP Documentation</a></h2> +<ul> + <li>Intel® Firmware Support Package External Architecture Specification <a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/fsp-architecture-spec-v2.pdf">V2.0</a></li> + <li>Intel® Firmware Support Package External Architecture Specification <a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/fsp-architecture-spec-v1-1.pdf">V1.1</a></li> + <li>Intel® Firmware Support Package External Architecture Specification <a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/fsp-architecture-spec.pdf">V1.0</a></li> +</ul> + + + +<hr> +<p>Modified: 17 May 2016</p> + </body> +</html> diff --git a/Documentation/backup-docs/old/Kconfig.tex b/Documentation/backup-docs/old/Kconfig.tex new file mode 100644 index 0000000..2b2bf7f --- /dev/null +++ b/Documentation/backup-docs/old/Kconfig.tex @@ -0,0 +1,480 @@ +\documentclass[10pt,letterpaper]{article} +\usepackage[latin1]{inputenc} +\usepackage{amsmath} +\usepackage{amsfonts} +\usepackage{amssymb} +\author{Ron Minnich} +\title{Kconfig usage in coreboot v2} +\begin{document} +\section{Introduction} +This document describes how to use Kconfig in v2. We describe our usage of Kconfig files, Makefile.inc files, when and where to use them, how to use them, and, interestingly, when and where not to use them. +\section{Kconfig variations} +Most Kconfig files set variables, which can be set as part of the Kconfig dialog. Not all Kconfig variables are set by the user, however; some are too dangerous. These are merely enabled by the mainboard. + +For variables set by the user, see src/console/Kconfig. + +For variables not set by the user, see src/mainboard/amd/serengeti_cheetah/Kconfig. Users should never set such variables as the cache as ram base. These are highly mainboard dependent. + +Kconfig files use the source command to include subdirectories. In most cases, save for limited cases described below, subdirectories have Kconfig files. They are always sourced unconditionally. + +\section{Makefile and Makefile.inc} +There is only one Makefile, at the top level. All other makefiles are included as Makefile.inc. All the next-level Makefile.inc files are selected in the top level Makefile. Directories that are platform-independent are in BUILD-y; platform-dependent (e.g. Makefile.inc's that depend on architecture) are included in PLATFORM-y. + +Make is not recursive. There is only one make process. +\subsection{subdirs usage} +Further includes of Makefile.inc, if needed, are done via subdirs-y commands. As in Linux, the subdirs can be conditional or unconditional. Conditional includes are done via subdirs-$(CONFIG_VARIABLE) usage; unconditional are done via subdirs-y. + +We define the common rules for which variation to use below. +\subsection{object file specification} +There are several different types of objects specified in the tree. They are: +\begin{description} +\item[obj]objects for the ram part of the code +\item[driver]drivers for the ram part. Drivers are not represented in the device tree but do have a driver struct attached in the driver section. +\item[initobj]seperately-compiled code for the ROM section of coreboot +\end{description} +These items are specified via the -y syntax as well. Conditional object inclusion is done via the -$(CONFIG_VARIABLE) syntax. + +\section{Example: AMD serengeti cheetah} +\subsection{mainboard/Kconfig} +Defines Vendor variables. Currently defined variables are: +Sources all Kconfig files in the vendor directories. +\input{ mainboardkconfig.tex} +\subsection{mainboard/Makefile.inc} +There is none at this time. +\subsection{mainboard/$<$vendor$>$/Kconfig} +We use the amd as a model. The only action currently taken is to source all Kconfig's in the +subdirectories. +\subsection{mainboard/$<$vendor$>$/Makefile.inc} +We use amd as a model. There is currently no Makefile.inc at this level. +\subsection{mainboard/$<$vendor$>$/$<$board$>$/Kconfig} +The mainboard Kconfig and Makefile.inc are designed to be the heart of the build. The defines +and rules in here determine everything about how a mainboard target is built. +We will use serengeti_cheetah as a model. It defines these variables. +\input{ mainboardkconfig.tex} +\subsection{mainboard/$<$vendor$>$/$<$board$>$/Makefile.inc} +This is a fairly complex Makefile.inc. Because this is such a critical component, we are going to excerpt and take it piece by piece. +Note that this is the mainboard as of August, 2009, and it may change over time. +\subsubsection{objects} +We define objects in the first part. The mainbard itself is a driver and included unconditionally. Other objects are conditional: +\begin{verbatim} +driver-y += mainboard.o + +#needed by irq_tables and mptable and acpi_tables +obj-y += get_bus_conf.o +obj-$(CONFIG_HAVE_MP_TABLE) += mptable.o +obj-$(CONFIG_HAVE_PIRQ_TABLE) += irq_tables.o +obj-$(CONFIG_HAVE_ACPI_TABLES) += dsdt.o +obj-$(CONFIG_HAVE_ACPI_TABLES) += acpi_tables.o +obj-$(CONFIG_HAVE_ACPI_TABLES) += fadt.o + +#./ssdt.o is in northbridge/amd/amdk8/Config.lb +obj-$(CONFIG_ACPI_SSDTX_NUM) += ssdt2.o +obj-$(CONFIG_ACPI_SSDTX_NUM) += ssdt3.o +obj-$(CONFIG_HAVE_ACPI_TABLES) += ssdt4.o +driver-y += ../../../drivers/i2c/i2cmux/i2cmux.o + +# This is part of the conversion to init-obj and away from included code. + +initobj-y += crt0.o +\end{verbatim} +\subsubsection{romcc legacy support} +We hope to move away from romcc soon, but for now, if one is using romcc, the Makefile.inc must define +crt0 include files (assembly code for startup, usually); and several ldscripts. These are taken directly from the +old Config.lb. Note that these use the -y syntax and can use the ability to be included conditionally. +\begin{verbatim} +crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc +crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc +crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc +crt0-y += ../../../../src/arch/i386/lib/id.inc +crt0-y += ../../../../src/cpu/amd/car/cache_as_ram.inc +crt0-y += auto.inc + +ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb +ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds +ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds +ldscript-y += ../../../../src/arch/i386/lib/id.lds +ldscript-y += ../../../../src/arch/i386/lib/failover.lds + +\end{verbatim} +\subsubsection{POST_EVALUATION} +POST_EVALUATION rules should be placed after this section: +\begin{verbatim} +ifdef POST_EVALUATION +\end{verbatim} +to ensure that the values of variables are correct. +Here are the post-evaluation rules for this mainboard: +\begin{verbatim} +$(obj)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl + iasl -p dsdt -tc $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl + mv dsdt.hex $@ + +$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/dsdt.c + $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $< -o $@ + +$(obj)/ssdt2.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci2.asl + iasl -p $(CURDIR)/pci2 -tc $(CONFIG_MAINBOARD)/dx/pci2.asl + perl -pi -e 's/AmlCode/AmlCode_ssdt2/g' pci2.hex + mv pci2.hex ssdt2.c + +$(obj)/ssdt3.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci3.asl" + iasl -p $(CURDIR)/pci3 -tc $(CONFIG_MAINBOARD)/ + perl -pi -e 's/AmlCode/AmlCode_ssdt3/g' pci3.hex + mv pci3.hex ssdt3.c + +$(obj)/ssdt4.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci4.asl" + iasl -p $(CURDIR)/pci4 -tc $(CONFIG_MAINBOARD)/dx/pci4.asl + perl -pi -e 's/AmlCode/AmlCode_ssdt4/g' pci4.hex + mv pci4.hex ssdt4.c + +$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/rom.c $(obj)/option_table.h + $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/rom.c -o $@ + perl -e 's/.rodata/.rom.data/g' -pi $@ + perl -e 's/.text/.section .rom.text/g' -pi $@ + +\end{verbatim} +The last rule is for romcc, and, again, we hope to eliminate romcc usage and this rule soon. The first set of rules concern ACPI tables. +\subsubsection{devicetree.cb} +Most of the old Config.lb is gone, but one piece remains: the device tree specification. This tree is still required to build a mainboard +properly, as it defines topology and chips that can be defined no other way. +Let's go through the tree. +\begin{verbatim} +chip northbridge/amd/amdk8/root_complex + device cpu_cluster 0 on + chip cpu/amd/socket_F + device lapic 0 on end + end + end +\end{verbatim} +This topology is always somewhat confusing to newcomers, and even to coreboot veterans. + +We root the tree at the pci-e {\it root complex}. There is always the question of how and where to root the tree. Over the years we +have found that the one part that never goes away is the root complex. CPU sockets may be empty or full; but there is always a northbridge +somewhere, since it runs memory. + + +What is the APIC? Northbridges always have an Advanced Programmable Interrupt Controller, and that {\it APIC cluster} is a topological connection to the +CPU socket. So the tree is rooted at the northbridge, which has a link to a CPU cluster, and then the CPU. The CPU contains +its own APIC, and will define any parameters needed. In this case, we have a northbridge of type +{\it northbridge/amd/amdk8/root_complex}, with its own cpu_cluster device which we turn on, +which connects to a {\it cpu/amd/socket_F}, +which has a local apic, which is on. + +Note that we do not enumerate all CPUs, even on this SMP mainboard. The reason is they may not all be there. The CPU we define here +is the so-called Boot Strap Processor, or BSP; the other CPUs will come along later, as the are discovered. We do not require (unlike many +BIOSes) that the BSP be CPU 0; any CPU will do. +\begin{verbatim} + device domain 0 on + chip northbridge/amd/amdk8 + device pci 18.0 on # northbridge + # devices on link 0, link 0 == LDT 0 +\end{verbatim} +Here begins the pci domain, which usually starts with 0. Then there is the northbridge, which bridges to the PCI bus. On +Opterons, certain CPU control registers are managed in PCI config space in device 18.0 (BSP), 19.0 (AP), and up. +\begin{verbatim} + chip southbridge/amd/amd8132 + # the on/off keyword is mandatory + device pci 0.0 on end + device pci 0.1 on end + device pci 1.0 on end + device pci 1.1 on end + end +\end{verbatim} +This is the 8132, a bridge to a secondary PCI bus. +\begin{verbatim} + chip southbridge/amd/amd8111 + # this "device pci 0.0" is the parent the next one + # PCI bridge + device pci 0.0 on + device pci 0.0 on end + device pci 0.1 on end + device pci 0.2 off end + device pci 1.0 off end + end +\end{verbatim} +The 8111 is a bridge to other busses and to the legacy ISA devices such as superio. +\begin{verbatim} + device pci 1.0 on + chip superio/winbond/w83627hf + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off # CIR + io 0x60 = 0x100 + end + device pnp 2e.7 off # GAME_MIDI_GIPO1 + io 0x60 = 0x220 + io 0x62 = 0x300 + irq 0x70 = 9 + end + device pnp 2e.8 off end # GPIO2 + device pnp 2e.9 off end # GPIO3 + device pnp 2e.a off end # ACPI + device pnp 2e.b on # HW Monitor + io 0x60 = 0x290 + irq 0x70 = 5 + end + end + end +\end{verbatim} +The pnp refers to the many Plug N Play devices on a superio. 2e refers to the base I/O address of the superio, and the number following the +2e (i.e. 2e.1) is the Logical Device Number, or LDN. Each LDN has a common configuration (base, irq, etc.) and these are set by the statements under the LDN. +\begin{verbatim} + device pci 1.1 on end + device pci 1.2 on end +\end{verbatim} +More devices. These statements set up placeholders in the device tree. +\begin{verbatim} + device pci 1.3 on + chip drivers/i2c/i2cmux # pca9556 smbus mux + device i2c 18 on #0 pca9516 1 + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic #dimm 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic #dimm 0-1-1 + device i2c 53 on end + end + end + device i2c 18 on #1 pca9516 2 + chip drivers/generic/generic #dimm 1-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 1-0-1 + device i2c 51 on end + end + chip drivers/generic/generic #dimm 1-1-0 + device i2c 52 on end + end + chip drivers/generic/generic #dimm 1-1-1 + device i2c 53 on end + end + chip drivers/generic/generic #dimm 1-2-0 + device i2c 54 on end + end + chip drivers/generic/generic #dimm 1-2-1 + device i2c 55 on end + end + chip drivers/generic/generic #dimm 1-3-0 + device i2c 56 on end + end + chip drivers/generic/generic #dimm 1-3-1 + device i2c 57 on end + end + end + end + end # acpi +\end{verbatim} +These are the i2c devices. +\begin{verbatim} + device pci 1.5 off end + device pci 1.6 off end +\end{verbatim} +More placeholders. +\begin{verbatim} + register "ide0_enable" = "1" + register "ide1_enable" = "1" + end + end # device pci 18.0 + +\end{verbatim} +These "register" commands set controls in the southbridge. +\begin{verbatim} + device pci 18.0 on end + device pci 18.0 on end +\end{verbatim} +These are the other two hypertransport links. +\begin{verbatim} + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end +\end{verbatim} +The 18.1 devices are, again, northbridge control for various k8 functions. +\begin{verbatim} + end + \end{verbatim} +That's it for the BSP I/O and HT busses. Now we begin the AP busses. Not much here. +\begin{verbatim} + chip northbridge/amd/amdk8 + device pci 19.0 on # northbridge + chip southbridge/amd/amd8151 + # the on/off keyword is mandatory + device pci 0.0 on end + device pci 1.0 on end + end + end # device pci 19.0 + + device pci 19.0 on end + device pci 19.0 on end + device pci 19.1 on end + device pci 19.2 on end + device pci 19.3 on end + end + + +\end{verbatim} + +\subsection{cpu socket} +The CPU socket is the key link from mainboard to its CPUs. Since many models of CPU can go in a socket, the mainboard mentions only +the socket, and the socket, in turn, references the various model CPUs which can be plugged into it. The socket is thus the focus +of all defines and Makefile controls for building the CPU components of a board. + +\subsubsection{ cpu/Kconfig} +Defines variables. Current variables are: +\input{cpukconfig.tex} +Sources all Kconfig files in the vendor directories. +\subsubsection{ cpu/Makefile.inc} +Unconditionally sources all Makefile.inc in the vendor directories. + +\subsection{cpu/$<$vendor$>$/Kconfig} +The only action currently taken is to source all Kconfig's in the +subdirectories. +\subsection{cpu/$<$vendor$>$/Makefile.inc} +{\em Conditionally} source the socket directories. +Example: +\begin{verbatim} +subdirs-$(CONFIG_CPU_AMD_SOCKET_F) += socket_F +\end{verbatim} +. +CONFIG_CPU_AMD_SOCKET_F is set in a mainboard file. + +\subsection{cpu/$<$vendor$>$/$<$socket$>$/Kconfig} +Set variables that relate to this {\em socket}, and {\em any models that plug into this socket}. Note that +the socket, as much as possible, should control the models, because the models may plug into many sockets. +Socket_F currently sets: +\input{socketfkconfig.tex} + +It sources only those Kconfigs that relate to this particular socket, i.e. not all possible models are sourced. + +\subsection{cpu/$<$vendor$>$/$<$model$>$/Kconfig} +CPU Model Kconfigs only set variables, We do not expect that they will source any other Kconfig. The socket Kconfig should do that +if needed. +\subsection{cpu/$<$vendor$>$/$<$model$>$/Makefile.inc} +The Makefile.inc {\em unconditionally} specifies drivers and objects to be included in the build. There is no conditional +compilation at this point. IF a socket is included, it includes the models. If a model is included, it should include {em all} +objects, because it is not possible to determine at build time what options may be needed for a given model CPU. +This Makefile.inc includes no other Makefile.inc files; any inclusion should be done in the socket Makefile.inc. + +\subsection{northbridge} +\subsubsection{northbridge/Kconfig} +No variables. Source all vendor directory Kconfigs. +\subsubsection{northbridge/Makefile.inc} +No variables. unconditionally include all vendor Makefile.inc +\subsubsection{northbridge/$<$vendor$>$/Kconfig} +No variables. Source all chip directory Kconfigs. +\subsubsection{northbridge/$<$vendor$>$/Makefile.inc} +No variables. {\em Conditionally} include all chipset Makefile.inc. The variable +is the name of the part, e.g. +\begin{verbatim} +subdirs-$(CONFIG_NORTHBRIDGE_AMD_AMDK8) += amdk8 +\end{verbatim} +. +\subsubsection{northbridge/$<$vendor$>$/$<$chip$>$/Kconfig} +Typically a small number of variables. One defines the part name. Here is an example +of the variables defined for the K8. +\begin{verbatim} +config NORTHBRIDGE_AMD_AMDK8 + bool + default n + +config AGP_APERTURE_SIZE + hex + default 0x4000000 +\end{verbatim} +\subsubsection{northbridge/$<$vendor$>$/$<$chip$>$/Makefile.inc} +Typically very small set of rules, and very simple. +Since this file is already conditionally included, +we don't need to test for the chipset CONFIG variable. We +can therefore test other variables (which is part of the reason +we set up conditional inclusion of this file, instead +of unconditionally including it). Here is an example from AMD K8. +Note that we can make a variable conditional on the ACPI tables. +\begin{verbatim} +driver-y += northbridge.o +driver-y += misc_control.o +obj-y += get_sblk_pci1234.o +obj-$(CONFIG_HAVE_ACPI_TABLES) += amdk8_acpi.o +\end{verbatim} + +\subsection{southbridge} +\subsubsection{southbridge/Kconfig} +No variables. Source all vendor directory Kconfigs. +\subsubsection{southbridge/Makefile.inc} +No variables. {\em Unconditionally} include all vendor Makefile.inc +\subsubsection{southbridge/$<$vendor$>$/Kconfig} +No variables. Source all chip directory Kconfigs. +\subsubsection{southbridge/$<$vendor$>$/Makefile.inc} +No variables. {\em Conditionally} include all chipset Makefile.inc. The variable +is the name of the part, e.g. +\begin{verbatim} +subdirs-$(CONFIG_SOUTHBRIDGE_AMD_AMD8111) += amd8111 +\end{verbatim} +. +\subsubsection{southbridge/$<$vendor$>$/$<$chip$>$/Kconfig} +Typically a small number of variables. One defines the part name. Here is an example +of the variables defined for the K8. +\begin{verbatim} +config SOUTHBRIDGE_AMD_AMD8111 + bool + default n + +\end{verbatim} +\subsubsection{southbridge/$<$vendor$>$/$<$chip$>$/Makefile.inc} +Typically very small set of rules, and very simple. +Since this file is already conditionally included, +we don't need to test for the chipset CONFIG variable. We +can therefore test other variables (which is part of the reason +we set up conditional inclusion of this file, instead +of unconditionally including it). Here is an example from AMD 8111. +No conditionals in this one yet. +\begin{verbatim} +driver-y += amd8111.o +driver-y += amd8111_usb.o +driver-y += amd8111_lpc.o +driver-y += amd8111_ide.o +driver-y += amd8111_acpi.o +driver-y += amd8111_usb2.o +driver-y += amd8111_ac97.o +driver-y += amd8111_nic.o +driver-y += amd8111_pci.o +driver-y += amd8111_smbus.o +obj-y += amd8111_reset.o +\end{verbatim} + +\subsubsection{vendor and part} +\subsection{southbridge} +\subsubsection{vendor and part} +\subsection{superio} +\subsection{drivers/i2c} +This is a rather special case. There are no Kconfig files or Makefile.inc files here. They are not needed. +To compile in one of these files, name the .o directory. E.g. in serengeti_cheetah we have: +\begin{verbatim} +\end{verbatim} + +\subsubsection{vendor and part} + +\end{document} diff --git a/Documentation/backup-docs/old/Makefile b/Documentation/backup-docs/old/Makefile new file mode 100644 index 0000000..96b66a9 --- /dev/null +++ b/Documentation/backup-docs/old/Makefile @@ -0,0 +1,70 @@ +# +# Makefile for coreboot paper. +# hacked together by Stefan Reinauer stepan@openbios.org +# + +PDFLATEX=pdflatex -t a4 + +FIGS=codeflow.pdf hypertransport.pdf + +all: CorebootPortingGuide.pdf Kconfig.pdf + +SVG2PDF=$(shell which svg2pdf) +INKSCAPE=$(shell which inkscape) +CONVERT=$(shell which convert) + +codeflow.pdf: codeflow.svg +ifneq ($(strip $(SVG2PDF)),) + svg2pdf $< $@ +else ifneq ($(strip $(INKSCAPE)),) + inkscape $< --export-pdf=$@ +else ifneq ($(strip $(CONVERT)),) + convert $< $@ +endif + +hypertransport.pdf: hypertransport.svg +ifneq ($(strip $(SVG2PDF)),) + svg2pdf $< $@ +else ifneq ($(strip $(INKSCAPE)),) + inkscape $< --export-pdf=$@ +else ifneq ($(strip $(CONVERT)),) + convert $< $@ +endif + +CorebootPortingGuide.toc: $(FIGS) CorebootBuildingGuide.tex + # 2 times to make sure we have a current toc. + $(PDFLATEX) CorebootBuildingGuide.tex + $(PDFLATEX) CorebootBuildingGuide.tex + +CorebootPortingGuide.pdf: $(FIGS) CorebootBuildingGuide.tex CorebootPortingGuide.toc + $(PDFLATEX) CorebootBuildingGuide.tex + +Kconfig.pdf: Kconfig.tex mainboardkconfig.tex cpukconfig.tex socketfkconfig.tex + $(PDFLATEX) $< + +# quick, somebody! make me a macro! +mainboardkconfig.tex: ../src/mainboard/Kconfig + cat beginverbatim.tex > $@ + grep '^config' $< | awk '{print $2}' >>$@ + cat endverbatim.tex >> $@ + +skconfig.tex: ../src/mainboard/amd/serengeti_cheetah/Kconfig + cat beginverbatim.tex > $@ + grep '^config' $< | awk '{print $2}' >>$@ + cat endverbatim.tex >> $@ + +cpukconfig.tex: ../src/cpu/Kconfig + cat beginverbatim.tex > $@ + grep '^config' $< | awk '{print $2}' >>$@ + cat endverbatim.tex >> $@ + +socketfkconfig.tex: ../src/cpu/amd/socket_F/Kconfig + cat beginverbatim.tex > $@ + grep '^config' $< | awk '{print $2}' >>$@ + cat endverbatim.tex >> $@ + +clean: + rm -f *.aux *.idx *.log *.toc *.out $(FIGS) mainboardkconfig.tex skconfig.tex cpukconfig.tex socketfkconfig.tex + +distclean: clean + rm -f CorebootPortingGuide.pdf Kconfig.pdf diff --git a/Documentation/backup-docs/old/POSTCODES b/Documentation/backup-docs/old/POSTCODES new file mode 100644 index 0000000..5d337b6 --- /dev/null +++ b/Documentation/backup-docs/old/POSTCODES @@ -0,0 +1,25 @@ +------------------------------------------------------------------------------- +coreboot POST Codes +------------------------------------------------------------------------------- + +This is an (incomplete) list of POST codes emitted by coreboot v4. + +0x10 Entry into protected mode +0x01 Entry into 'crt0.s' reset code jumps to here +0x11 Start copying coreboot to RAM with decompression if compressed +0x12 Copy/decompression finished jumping to RAM +0x80 Entry into coreboot in RAM +0x13 Entry into c_start +0xfe Pre call to hardwaremain() +0x39 Console is initialized +0x40 Console boot message succeeded +0x66 Devices have been enumerated +0x88 Devices have been configured +0x89 Devices have been enabled +0xf8 Entry into elf boot +0xf3 Jumping to payload + +Errors (used in several places): + +0xee Not supposed to get here +0xff Elfload fail or die() called diff --git a/Documentation/backup-docs/old/RFC/chip.tex b/Documentation/backup-docs/old/RFC/chip.tex new file mode 100644 index 0000000..5e366b8 --- /dev/null +++ b/Documentation/backup-docs/old/RFC/chip.tex @@ -0,0 +1,266 @@ + RFC for the chip specification architecture + +\begin{abstract} +At the end of this document is the original message that motivated the +change. +\end{abstract} + +\section{Scope} +This document defines how LinuxBIOS programmers can specify chips that +are used, specified, and initalized. The current scope is for superio +chips, but the architecture should allow for specification of other chips such +as southbridges. Multiple chips of same or different type are supported. + +\section{Goals} +The goals of the new chip architecture are these: +\begin{itemize} +\item seperate implementation details from specification in the Config file +(translation: no more C code in Config files) +\item make the specification easier for people to use and understand +\item remove private details of a given chip to the chip file as much +as possible +\item allow unique register-set-specifiers for each chip +\end{itemize} + +\section{Specification in the Config file} +The specification looks like this: +\begin{verbatim} +chip <name> [path=<path>] ["<configuration>"] +\end{verbatim} +The name is in the standard LinuxBIOS form of type/vendor/name, e.g. +"southbridge/intel/piix4e" or "superio/ite/it8671f". The class of the +chip is derived from the first pathname component of the name, and the chip +configuration is derived from the following components. + +The path defines the access mechanism to the chip. +It is optional. If present, it overrides the default path to the chip. + +The configuration defines chip-specific configuration details, and is also +optional. Note that an empty configuration will leave the chip with +no enabled resources. This may be desirable in some cases. + +\section{Results of specifying a chip} + +When one or more chips are specified, the data about the chips +is saved until the entire file is parsed. At this point, the config tool +creates a file in the build directory called chip.c This file contains +a common struct containing information about +each individual chip and an array of pointers to these structures. + +For each chip, there are two structures. The structures contain control +information for the chip, and register initialization information. The +names of the structures are derived by ``flattening'' the chip name, +as in the current linuxbios. For example, superio/ite/xyz uses +two structs, one called superio_ite_xyz_control and one called +superio_ite_xyz_init. The control struct is initialized from the +chip name and path information, and has a pointer to the +config struct. The config struct is initialized from the quote string + +\begin{verbatim} +From rminnich@lanl.gov Fri May 16 10:34:13 2003 +Date: Tue, 13 May 2003 08:11:46 -0600 (MDT) +From: ron minnich rminnich@lanl.gov +To: linuxbios@clustermatic.org +Subject: RFC:new superio proposal + +Abstract: + The superio architecture for linuxbios has worked for the last 2 +years but is being stretched to the limit by the changes in superio chips. +The architecture depended on superio resources being relatively constant +between chips, but this assumption no longer holds. In this document we +propose several alternatives and solicit comments. + +Overview: +The superio architecture in linuxbios was developed over time, and +modified as circumstances required. In the beginning it was relatively +simple and assumed only one superio per mainboard. The latest version +allows an arbitrary number of superios per mainboard, and allows complete +specification of the superio base I/O address along with the specification +of reasonable default valures for both the base I/O address and the +superio parameters such as serial enable, baud rate, and so on. + +Specification of superio control parameters is done by a configuration +line such as: + +nsuperio sis/950 com1={1} floppy=1 lpt=1 + +This fragment sets the superio type to sis/950; sets com1, floppy, and lpt +to enabled; and leaves the defaults to com1 (baud rate, etc.) to the +default values. + +While it is not obvious, these configuration parameters are fragments of a +C initializer. The initializers are used to build a statically initialized +structure of this type: + +struct superio { + struct superio_control *super; // the ops for the device. + unsigned int port; // if non-zero, overrides the default port + // com ports. This is not done as an array (yet). + // We think it's easier to set up from python if it is not an + // array. + struct com_ports com1, com2, com3, com4; + // DMA, if it exists. + struct lpt_ports lpt1, lpt2; + /* flags for each device type. Unsigned int. */ + // low order bit ALWAYS means enable. Next bit means to enable + // LPT is in transition, so we leave this here for the moment. + // The winbond chips really stretched the way this works. + // so many functions! + unsigned int ide, floppy, lpt; + unsigned int keyboard, cir, game; + unsigned int gpio1, gpio2, gpio3; + unsigned int acpi,hwmonitor; +}; + +These structures are, in turn, created and statically initialized by a +config-tool-generated structure that defines all the superios. This file +is called nsuperio.c, is created for each mainboard you build, only +appears in the build directory, and looks like this: + +=== +extern struct superio_control superio_winbond_w83627hf_control; + +struct superio superio_winbond_w83627hf= { + &superio_winbond_w83627hf_control, + .com1={1}, .com2={1}, .floppy=1, .lpt=1, .keyboard=1, .hwmonitor=1}; + +struct superio *all_superio[] = {&superio_winbond_w83627hf, +}; + +unsigned long nsuperio = 1; +=== + +This example shows a board with one superio (nsuperio). The superio +consists of a winbond w83627hf, with com1, com2, floppy, lpt, keyboard, +and hwmonitor enabled. Note that this structure also allows for +over-riding the default superio base, although that capability is rarely +used. + +The control structure is used to define how to access the superio for +purposes of control. It looks like this: +=== +struct superio_control { + void (*pre_pci_init)(struct superio *s); + void (*init)(struct superio *s); + void (*finishup)(struct superio *s); + unsigned int defaultport; /* the defaultport. Can be overridden + * by commands in config + */ + // This is the print name for debugging + char *name; +}; +=== + +There are three methods for stages of hardwaremain. First is pre_pci_init +(for chips like the acer southbridge that require you to enable some +resources BEFORE pci scan); init, called during the 'middle' phase of +hardwaremain; and finishup, called before the payload is loaded. + +This approach was inspired by and borrows heavily on the Plan 9 kernel +configuration tools. + +The problem: + +When the first version of the superio structure came out it was much +smaller. It has grown and in the limit this structure is the union of all +possibly superio chips. Obviously, in the long term, this is not +practical: we can not anticipate all possible superio chips for all time. + +The common PC BIOS solution to this type of problem is to continue with +binary structures but add version numbers to them, so that all code that +uses a given structure has to check the version number. Personally, I find +this grotesque and would rather not work this way. + +Using textual strings for configuration is something I find far more +attractive. Plan 9 has shown that this approach has no real limits and +suffices for configuration tasks. The Linux kernel does more limited use +of strings for configuration, but still depends on them. Strings are +easier to read and work with than binary structures, and more important, a +lot easier to deal with when things start going wrong. + +The proposed solution: + +What follows are three possible ideas for specifying superio resources and +their settings. + +A common part of the new idea is to eliminate the common superio +structure, due to the many variations in chips, and make it invisible +outside a given superio source file -- the superio structure is now +private to a given superio. Thus, sis/950/superio.c would contain its own +superio structure definitions, and also might contain more than once +instance of these structures (consider a board with 2 sis 950 chips). + +The control structure would change as follows: +struct superio_control { + int (*create)(struct superio *s); + void (*pre_pci_init)(struct superio *s); + void (*init)(struct superio *s); + void (*finishup)(struct superio *s); + unsigned int defaultport; /* the defaultport. Can be overridden + * by commands in config + */ + // This is the print name for debugging + char *name; +}; + +I.e. we add a new function for creating the superio. + +Communication of superio settings from linuxbios to the superio would be +via textual strings. The superio structure becomes this: + +struct superio { + struct superio_control *super; // the ops for the device. + unsigned int port; // if non-zero, overrides the default port + struct configuration *config; +}; + + +So now the question becomes, what is the configuration structure? +There are several choices. The simplest, from my point of view, are +keyword-value pairs: +struct configuration { + const char *keyword; + const char *value; +}; + +These get filled in by the config tool as before. The linuxbios libary can +then provide a generic parsing function for the superios to use. + +The remaining question is how should the superio command look in +freebios2? + +superio sis/950 "com1=115200,8n1 lpt=1 com2=9600" + +or + +superio sis/950 "com1baud=115200 lpt=1 com1chars=8n1" + +or + +superio sis/950 ((com1 115200 8n1) (lpt 1)) + +So, my questions: + +1. Does this new scheme look workable. If not, what needs to change? +2. What should the 'struct configuration' be? does keyword/value work? +3. what should the superio command look like? + +Comments welcome. + +I'd like to adopt this "RFC" approach for freebios2 as much as we can. +There was a lot of give-and-take in the early days of linuxbios about +structure and it proved useful. There's a lot that will start happening in +freebios2 now, and we need to try to make sure it will work for everyone. + +Those of you who are doing mainboards, please look at freebios2 and see +how it looks for you. There's a lot of good work that has been done (not +by me so far, thanks Eric and Stefan), and more that needs to be done. +Consider trying out romcc as an "assembly code killer". See how it fits +together and if you can work with it or need changes. Bring comments back +to this list. + +thanks + +ron + +\end{verbatim} diff --git a/Documentation/backup-docs/old/RFC/config.tex b/Documentation/backup-docs/old/RFC/config.tex new file mode 100644 index 0000000..696ab7a --- /dev/null +++ b/Documentation/backup-docs/old/RFC/config.tex @@ -0,0 +1,290 @@ + New config language for LinuxBIOS + +\begin{abstract} +We describe the new configuration language for LinuxBIOS. +\end{abstract} + +\section{Scope} +This document defines the new configuration language for LinuxBIOS. + +\section{Goals} +The goals of the new language are these: +\begin{itemize} +\item Simplified Makefiles so people can see what is set +\item Move from the regular-expression-based language to something +a bit more comprehensible and flexible +\item make the specification easier for people to use and understand +\item allow unique register-set-specifiers for each chip +\item allow generic register-set-specifiers for each chip +\item generate static initialization code, as needed, for the +specifiers. +\end{itemize} + +\section{Language} +Here is the new language. It is very similar to the old one, differing +in only a few respects. It borrows heavily from Greg Watson's suggestions. + +I am presenting it in a pseudo-BNF in the hopes it will be easier. Things +in '' are keywords; things in ``'' are strings in the actual text. +\begin{verbatim} +#exprs are composed of factor or factor + factor etc. +expr ::= factor ( ``+'' factor | ``-'' factor | )* +#factors are term or term * term or term / term or ... +factor ::= term ( ``*'' term | ``/'' term | ... )* +# +unary-op ::= ``!'' ID +# term is a number, hexnumber, ID, unary-op, or a full-blown expression +term ::= NUM | XNUM | ID | unary-op | ``(`` expr ``)'' + +# Option command. Can be an expression or quote-string. +# Options are used in the config tool itself (in expressions and 'if') +# and are also passed to the C compiler when building linuxbios. +# It is an error to have two option commands in a file. +# It is an error to have an option command after the ID has been used +# in an expression (i.e. 'set after used' is an error) +option ::= 'option' ID '=' (``value'' | term) + +# Default command. The ID is set to this value if no option command +# is scanned. +# Multiple defaults for an ID will produce warning, but not errors. +# It is OK to scan a default command after use of an ID. +# Options always over-ride defaults. +default ::= 'default' ID '=' (``value'' | term) + +# the mainboard, southbridge, northbridge commands +# cause sourcing of Config.lb files as in the old config tool +# as parts are sourced, a device tree is built. The structure +# of the tree is determined by the structure of the components +# as they are specified. To attach a superio to a southbridge, for +# example, one would do this: +# southbridge acer/5432 +# superio nsc/123 +# end +# end +# the tool generates static initializers for this hierarchy. + +# add C code to the current component (motherboard, etc. ) +# to initialise the component-INDEPENDENT structure members +init ::= 'init' ``CODE'' + +# add C code to the current component (motherboard, etc. ) +# to initialise the component-DEPENDENT structure members +register ::= 'register' ``CODE'' + + +# mainboard command +# statements in this block will set variables controlling the mainboard, +# and will also place components (northbridge etc.) in the device tree +# under this mainboard +mainboard ::= 'mainboard' PATH (statements)* 'end' + +# standard linuxbios commands +southbridge ::= 'southbridge' PATH (statemnts)* 'end' +northbridge ::= 'northbridge' PATH (statemnts)* 'end' +superio ::= 'superio PATH (statemnts)* 'end' +cpu ::= 'cpu' PATH (statemnts)* 'end' +arch ::= 'arch' PATH (statemnts)* 'end' + +# files for building linuxbios +# include a file in crt0.S +mainboardinit ::= 'mainboardinit' PATH + +# object file +object ::= 'object' PATH +# driver objects are just built into the image in a different way +driver ::= 'driver' PATH + +# Use the Config.lb file in the PATH +dir ::= 'dir' PATH + +# add a file to the set of ldscript files +ldscript ::= 'ldscript' PATH + +# dependencies or actions for the makerule command +dep ::= 'dep' ``dependency-string'' +act ::= 'act' ``actions'' +depsacts ::= (dep | act)* +# set up a makerule +# +makerule ::= 'makerule' PATH depsacts + +#defines for use in makefiles only +# note usable in the config tool, not passed to cc +makedefine ::= 'makedefine' ``RAWTEXT'' + +# add an action to an existing make rule +addaction ::= 'addaction' PATH ``ACTION'' + +# statements +statement ::= + option + | default + | cpu + | arch + | northbridge + | southbridge + | superio + | object + | driver + | mainboardinit + | makerule + | makedefine + | addaction + | init + | register + | iif + | dir + | ldscript + +statements ::= (statement)* + +# target directory specification +target ::= 'target' PATH + +# and the whole thing +board ::= target (option)* mainboard + +\end{verbatim} + +\subsubsection{Command definitions} +\subsubsubsection{option} +\subsubsubsection{default} +\subsubsubsection{cpu} +\subsubsubsection{arch} +\subsubsubsection{northbridge} +\subsubsubsection{southbridge} +\subsubsubsection{superio} +\subsubsubsection{object} +\subsubsubsection{driver} +\subsubsubsection{mainboardinit} +\subsubsubsection{makerule} +\subsubsubsection{makedefine} +\subsubsubsection{addaction} +\subsubsubsection{init} +\subsubsubsection{register} +\subsubsubsection{iif} +\subsubsubsection{dir} +\subsubsubsection{ldscript} + + +A sample file: + +\begin{verbatim} +target x + +# over-ride the default rom size in the mainboard file +option CONFIG_ROM_SIZE=1024*1024 +mainboard amd/solo +end + +\end{verbatim} + +Sample mainboard file +\begin{verbatim} +# +### +### Set all of the defaults for an x86 architecture +### +arch i386 end +cpu k8 end +# +option CONFIG_DEBUG=1 +default CONFIG_USE_FALLBACK_IMAGE=1 +option A=(1+2) +option B=0xa +# +### +### Build our 16 bit and 32 bit linuxBIOS entry code +### +mainboardinit cpu/i386/entry16.inc +mainboardinit cpu/i386/entry32.inc +ldscript cpu/i386/entry16.lds +ldscript cpu/i386/entry32.lds +# +### +### Build our reset vector (This is where linuxBIOS is entered) +### +if CONFIG_USE_FALLBACK_IMAGE + mainboardinit cpu/i386/reset16.inc + ldscript cpu/i386/reset16.lds +else + mainboardinit cpu/i386/reset32.inc + ldscript cpu/i386/reset32.lds +end +. +. +. +if CONFIG_USE_FALLBACK_IMAGE mainboardinit arch/i386/lib/noop_failover.inc end +# +### +### Romcc output +### +#makerule ./failover.E dep "$(CONFIG_MAINBOARD)/failover.c" act "$(CPP) -I$(TOP)/src $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c > ./failever.E" +#makerule ./failover.inc dep "./romcc ./failover.E" act "./romcc -O ./failover.E > failover.inc" +#mainboardinit ./failover.inc +makerule ./auto.E dep "$(CONFIG_MAINBOARD)/auto.c" act "$(CPP) -I$(TOP)/src -$(ROMCCPPFLAGS) $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c > ./auto.E" +makerule ./auto.inc dep "./romcc ./auto.E" act "./romcc -O ./auto.E > auto.inc" +mainboardinit ./auto.inc +# +### +### Include the secondary Configuration files +### +northbridge amd/amdk8 +end +southbridge amd/amd8111 +end +#mainboardinit arch/i386/smp/secondary.inc +superio nsc/pc87360 + register "com1={1} com2={0} floppy=1 lpt=1 keyboard=1" +end +dir /pc80 +##dir /src/superio/winbond/w83627hf +cpu p5 end +cpu p6 end +cpu k7 end +cpu k8 end +# +### +### Build the objects we have code for in this directory. +### +##object mainboard.o +driver mainboard.o +object static_devices.o +if CONFIG_HAVE_MP_TABLE object mptable.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end +### Location of the DIMM EEPROMS on the SMBUS +### This is fixed into a narrow range by the DIMM package standard. +### +option SMBUS_MEM_DEVICE_START=(0xa << 3) +option SMBUS_MEM_DEVICE_END=(SMBUS_MEM_DEVICE_START +1) +option SMBUS_MEM_DEVICE_INC=1 +# +### The linuxBIOS bootloader. +### +option CONFIG_PAYLOAD_SIZE = (CONFIG_ROM_SECTION_SIZE - CONFIG_ROM_IMAGE_SIZE) +option CONFIG_ROM_PAYLOAD_START = (0xffffffff - CONFIG_ROM_SIZE + CONFIG_ROM_SECTION_OFFSET + 1) +# + +\end{verbatim} + +I've found the output of the new tool to be easier to +handle. Makefile.settings looks like this, for example: +\begin{verbatim} +TOP:=/home/rminnich/src/yapps2/freebios2 +TARGET_DIR:=x +export CONFIG_MAINBOARD:=/home/rminnich/src/yapps2/freebios2/src/mainboard/amd/solo +export CONFIG_ARCH:=i386 +export CONFIG_RAMBASE:=0x4000 +export CONFIG_ROM_IMAGE_SIZE:=65535 +export CONFIG_PAYLOAD_SIZE:=131073 +export CONFIG_MAX_CPUS:=1 +export CONFIG_HEAP_SIZE:=8192 +export CONFIG_STACK_SIZE:=8192 +export CONFIG_MEMORY_HOLE:=0 +export COREBOOT_VERSION:=1.1.0 +export CC:=$(CONFIG_CROSS_COMPILE)gcc + +\end{verbatim} + +In other words, instead of expressions, we see the values. It's easier to +deal with. diff --git a/Documentation/backup-docs/old/abi-data-consumption.txt b/Documentation/backup-docs/old/abi-data-consumption.txt new file mode 100644 index 0000000..81442e7 --- /dev/null +++ b/Documentation/backup-docs/old/abi-data-consumption.txt @@ -0,0 +1,22 @@ +This text describes the ABI coreboot presents to downstream users. Such +users are payloads and/or operating systems. Therefore, this text serves +at what can be relied on for downstream consumption. Anything not explicitly +listed as consumable is subject to change without notice. + +Background and Usage + +coreboot passes information to downstream users using coreboot tables. These +table definitions can be found in src/include/boot/coreboot_tables.h and +payloads/libpayload/include/coreboot_tables.h respectively within coreboot +and libpayload. One of the most vital and important pieces of information +found within these tables is the memory map of the system indicating +available and reserved memory. + +In 2009 cbmem was added to coreboot. The "CBMEM high table memory manager" +serves a way for coreboot to bookkeep its own internal data. While some +of this data may be exposed through the coreboot tables the data structures +used to manage the data within the cbmem area is subject to change. + +Provided the above, if one needs a piece of data exposed to the OS +or payload it should reside within the coreboot tables. If it isn't there +then a code change will be required to add it to the coreboot tables. diff --git a/Documentation/backup-docs/old/beginverbatim.tex b/Documentation/backup-docs/old/beginverbatim.tex new file mode 100644 index 0000000..453714c --- /dev/null +++ b/Documentation/backup-docs/old/beginverbatim.tex @@ -0,0 +1 @@ +\begin{verbatim} diff --git a/Documentation/backup-docs/old/cbfs.txt b/Documentation/backup-docs/old/cbfs.txt new file mode 100644 index 0000000..7ecc901 --- /dev/null +++ b/Documentation/backup-docs/old/cbfs.txt @@ -0,0 +1,421 @@ + +Received: from www.crouse-house.com ([199.45.160.146] + for coreboot@coreboot.org; Fri, 19 Dec 2008 23:11:59 +0100 +From: Jordan Crouse jordan@cosmicpenguin.net + + +Greetings. I apologize for the incompleteness of what I am about to +discuss. I was planning on working on it leisurely, but my employment +circumstances changed and I've been trying to get it completed in a +hurry before I had to leave it behind. + +I've been thinking a lot about LAR lately, and ways to make it more +extensible and robust. Marc and I have been trading ideas back and +forth for a number of months, and over time a clear idea of what I +wanted to do started to take shape. + +My goal was to add small things to LAR while retaining the overall +scheme. Over time, the scheme evolved slightly, but I think you'll find +that it remains true to the original idea. Below is the beginnings of +an architecture document - I did it in text form, but if met with +aclaim, it should be wikified. This presents what I call CBFS - the +next generation LAR for next generation Coreboot. Its easier to +describe what it is by describing what changed: + +A header has been added somewhere in the bootblock similar to Carl +Daniel's scheme. In addition to the coreboot information, the header +reports the size of the ROM, the alignment of the blocks, and the offset +of the first component in the CBFS. The master header provides all +the information LAR needs plus the magic number information flashrom needs. + +Each "file" (or component, as I style them) now has a type associated +with it. The type is used by coreboot to identify the type of file that +it is loading, and it can also be used by payloads to group items in the +CBFS by type (i.e - bayou can ask for all components that are payloads). + +The header on each "file" (or component, as I like to style them) has +been simplified - We now only store the length, the type, the checksum, +and the offset to the data. The name scheme remains the same. The +addtional information, which is component specific, has been moved to +the component itself (see below). + +The components are arranged in the ROM aligned along the specified +alignment from the master header - this is to facilitate partial re-write. + +Other then that, the LAR ideas remain pretty much the same. + +The plan for moving the metadata to the components is to allow many +different kinds of components, not all of which are groked by coreboot. + However, there are three essential component types that are groked by +coreboot, and they are defined: + +stage - the stage is being parsed from the original ELF, and stored in +the ROM as a single blob of binary data. The load address, start +address, compression type and length are stored in the component sub-header. + +payload - this is essentially SELF in different clothing - same idea as +SELF, with the sub-header as above. + +optionrom - This is in flux - right now, the optionrom is stored +unadulterated and uncompressed, but that is likely to be changed. + +Following this email are two replies containing the v3 code and a new +ROM tool to implement this respectively. I told you that I was trying +to get this out before I disappear, and I'm not kidding - the code is +compile tested and not run-tested. I hope that somebody will embrace +this code and take it the rest of the way, otherwise it will die a +pretty short death. + +I realize that this will start an awesome flamewar, and I'm looking +forward to it. Thanks for listening to me over the years - and good +luck with coreboot. When you all make a million dollars, send me a few +bucks, will you? + +Jordan + +Coreboot CBFS Specification +Jordan Crouse jordan@cosmicpenguin.net + += Introduction = + +This document describes the coreboot CBFS specification (from here +referred to as CBFS). CBFS is a scheme for managing independent chunks +of data in a system ROM. Though not a true filesystem, the style and +concepts are similar. + + += Architecture = + +The CBFS architecture looks like the following: + +/---------------\ <-- Start of ROM +| /-----------\ | --| +| | Header | | | +| |-----------| | | +| | Name | | |-- Component +| |-----------| | | +| |Data | | | +| |.. | | | +| -----------/ | --| +| | +| /-----------\ | +| | Header | | +| |-----------| | +| | Name | | +| |-----------| | +| |Data | | +| |.. | | +| -----------/ | +| | +| ... | +| /-----------\ | +| | | | +| | Bootblock | | +| | --------- | | +| | Reset | | <- 0xFFFFFFF0 +| -----------/ | +---------------/ + + +The CBFS architecture consists of a binary associated with a physical +ROM disk referred hereafter as the ROM. A number of independent of +components, each with a header prepended on to data are located within +the ROM. The components are nominally arranged sequentially, though they +are aligned along a pre-defined boundary. + +The bootblock occupies the last 20k of the ROM. Within +the bootblock is a master header containing information about the ROM +including the size, alignment of the components, and the offset of the +start of the first CBFS component within the ROM. + += Master Header = + +The master header contains essential information about the ROM that is +used by both the CBFS implementation within coreboot at runtime as well +as host based utilities to create and manage the ROM. The master header +will be located somewhere within the bootblock (last 20k of the ROM). A +pointer to the location of the header will be located at offset +-4 from the end of the ROM. This translates to address 0xFFFFFFFC on a +normal x86 system. The pointer will be to physical memory somewhere +between - 0xFFFFB000 and 0xFFFFFFF0. This makes it easier for coreboot +to locate the header at run time. Build time utilities will +need to read the pointer and do the appropriate math to locate the header. + +The following is the structure of the master header: + +struct cbfs_header { + u32 magic; + u32 version; + u32 romsize; + u32 bootblocksize; + u32 align; + u32 offset; + u32 architecture; + u32 pad[1]; +} __attribute__((packed)); + +The meaning of each member is as follows: + +'magic' is a 32 bit number that identifies the ROM as a CBFS type. The +magic +number is 0x4F524243, which is 'ORBC' in ASCII. + +'version' is a version number for CBFS header. cbfs_header structure may be +different if version is not matched. + +'romsize' is the size of the ROM in bytes. Coreboot will subtract 'size' from +0xFFFFFFFF to locate the beginning of the ROM in memory. + +'bootblocksize' is the size of bootblock reserved in firmware image. + +'align' is the number of bytes that each component is aligned to within the +ROM. This is used to make sure that each component is aligned correctly +with +regards to the erase block sizes on the ROM - allowing one to replace a +component at runtime without disturbing the others. + +'offset' is the offset of the the first CBFS component (from the start of +the ROM). This is to allow for arbitrary space to be left at the beginning +of the ROM for things like embedded controller firmware. + +'architecture' describes which architecture (x86, arm, ...) this CBFS is created +for. + += Bootblock = +The bootblock is a mandatory component in the ROM. It is located in the +last +20k of the ROM space, and contains, among other things, the location of the +master header and the entry point for the loader firmware. The bootblock +does not have a component header attached to it. + += Components = + +CBFS components are placed in the ROM starting at 'offset' specified in +the master header and ending at the bootblock. Thus the total size +available +for components in the ROM is (ROM size - 20k - 'offset'). Each CBFS +component is to be aligned according to the 'align' value in the header. +Thus, if a component of size 1052 is located at offset 0 with an 'align' +value +of 1024, the next component will be located at offset 2048. + +Each CBFS component will be indexed with a unique ASCII string name of +unlimited size. + +Each CBFS component starts with a header: + +struct cbfs_file { + char magic[8]; + unsigned int len; + unsigned int type; + unsigned int checksum; + unsigned int offset; +}; + +'magic' is a magic value used to identify the header. During runtime, +coreboot will scan the ROM looking for this value. The default magic is +the string 'LARCHIVE'. + +'len' is the length of the data, not including the size of the header and +the size of the name. + +'type' is a 32 bit number indicating the type of data that is attached. +The data type is used in a number of ways, as detailed in the section +below. + +'checksum' is a 32bit checksum of the entire component, including the +header and name. + +'offset' is the start of the component data, based off the start of the +header. +The difference between the size of the header and offset is the size of the +component name. + +Immediately following the header will be the name of the component, +which will +null terminated and 16 byte aligned. The following picture shows the +structure of the header: + +/--------\ <- start +| Header | +|--------| <- sizeof(struct cbfs_file) +| Name | +|--------| <- 'offset' +| Data | +| ... | +--------/ <- start + 'offset' + 'len' + +== Searching Alogrithm == + +To locate a specific component in the ROM, one starts at the 'offset' +specified in the CBFS master header. For this example, the offset will +be 0. + + From that offset, the code should search for the magic string on the +component, jumping 'align' bytes each time. So, assuming that 'align' is +16, the code will search for the string 'LARCHIVE' at offset 0, 16, 32, etc. +If the offset ever exceeds the allowable range for CBFS components, then no +component was found. + +Upon recognizing a component, the software then has to search for the +specific name of the component. This is accomplished by comparing the +desired name with the string on the component located at +offset + sizeof(struct cbfs_file). If the string matches, then the +component +has been located, otherwise the software should add 'offset' + 'len' to +the offset and resume the search for the magic value. + +== Data Types == + +The 'type' member of struct cbfs_file is used to identify the content +of the component data, and is used by coreboot and other +run-time entities to make decisions about how to handle the data. + +There are three component types that are essential to coreboot, and so +are defined here. + +=== Stages === + +Stages are code loaded by coreboot during the boot process. They are +essential to a successful boot. Stages are comprised of a single blob +of binary data that is to be loaded into a particular location in memory +and executed. The uncompressed header contains information about how +large the data is, and where it should be placed, and what additional memory +needs to be cleared. + +Stages are assigned a component value of 0x10. When coreboot sees this +component type, it knows that it should pass the data to a sub-function +that will process the stage. + +The following is the format of a stage component: + +/--------\ +| Header | +|--------| +| Binary | +| .. | +--------/ + +The header is defined as: + +struct cbfs_stage { + unsigned int compression; + unsigned long long entry; + unsigned long long load; + unsigned int len; + unsigned int memlen; +}; + +'compression' is an integer defining how the data is compressed. There +are three compression types defined by this version of the standard: +none (0x0), lzma (0x1), and nrv2b (0x02, deprecated), though additional +types may be added assuming that coreboot understands how to handle the scheme. + +'entry' is a 64 bit value indicating the location where the program +counter should jump following the loading of the stage. This should be +an absolute physical memory address. + +'load' is a 64 bit value indicating where the subsequent data should be +loaded. This should be an absolute physical memory address. + +'len' is the length of the compressed data in the component. + +'memlen' is the amount of memory that will be used by the component when +it is loaded. + +The component data will start immediately following the header. + +When coreboot loads a stage, it will first zero the memory from 'load' to +'memlen'. It will then decompress the component data according to the +specified scheme and place it in memory starting at 'load'. Following that, +it will jump execution to the address specified by 'entry'. +Some components are designed to execute directly from the ROM - coreboot +knows which components must do that and will act accordingly. + +=== Payloads === + +Payloads are loaded by coreboot following the boot process. + +Stages are assigned a component value of 0x20. When coreboot sees this +component type, it knows that it should pass the data to a sub-function +that will process the payload. Furthermore, other run time +applications such as 'bayou' may easily index all available payloads +on the system by searching for the payload type. + + +The following is the format of a stage component: + +/-----------\ +| Header | +| Segment 1 | +| Segment 2 | +| ... | +|-----------| +| Binary | +| .. | +-----------/ + +The header is as follows: + +struct cbfs_payload { + struct cbfs_payload_segment segments; +} + +The header contains a number of segments corresponding to the segments +that need to be loaded for the payload. + +The following is the structure of each segment header: + +struct cbfs_payload_segment { + unsigned int type; + unsigned int compression; + unsigned int offset; + unsigned long long load_addr; + unsigned int len; + unsigned int mem_len; +}; + +'type' is the type of segment, one of the following: + +PAYLOAD_SEGMENT_CODE 0x45444F43 The segment contains executable code +PAYLOAD_SEGMENT_DATA 0x41544144 The segment contains data +PAYLOAD_SEGMENT_BSS 0x20535342 The memory speicfied by the segment + should be zeroed +PAYLOAD_SEGMENT_PARAMS 0x41524150 The segment contains information for + the payload +PAYLOAD_SEGMENT_ENTRY 0x52544E45 The segment contains the entry point + for the payload + +'compression' is the compression scheme for the segment. Each segment can +be independently compressed. There are three compression types defined by +this version of the standard: none (0x0), lzma (0x1), and nrv2b +(0x02, deprecated), though additional types may be added assuming that +coreboot understands how to handle the scheme. + +'offset' is the address of the data within the component, starting from +the component header. + +'load_addr' is a 64 bit value indicating where the segment should be placed +in memory. + +'len' is a 32 bit value indicating the size of the segment within the +component. + +'mem_len' is the size of the data when it is placed into memory. + +The data will located immediately following the last segment. + +=== Option ROMS === + +The third specified component type will be Option ROMs. Option ROMS will +have component type '0x30'. They will have no additional header, the +uncompressed binary data will be located in the data portion of the +component. + +=== NULL === + +There is a 4th component type ,defined as NULL (0xFFFFFFFF). This is +the "don't care" component type. This can be used when the component +type is not necessary (such as when the name of the component is unique. +i.e. option_table). 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SeaBIOS, ...</text> +</svg> diff --git a/Documentation/backup-docs/old/coreboot_logo.png b/Documentation/backup-docs/old/coreboot_logo.png new file mode 100644 index 0000000..dde1aa6 Binary files /dev/null and b/Documentation/backup-docs/old/coreboot_logo.png differ diff --git a/Documentation/backup-docs/old/endverbatim.tex b/Documentation/backup-docs/old/endverbatim.tex new file mode 100644 index 0000000..f832f3f --- /dev/null +++ b/Documentation/backup-docs/old/endverbatim.tex @@ -0,0 +1 @@ +\end{verbatim} diff --git a/Documentation/backup-docs/old/gcov.txt b/Documentation/backup-docs/old/gcov.txt new file mode 100644 index 0000000..896ec93 --- /dev/null +++ b/Documentation/backup-docs/old/gcov.txt @@ -0,0 +1,227 @@ +This patch contains our local modifications for gcov-io.h and libgcov.c. +The file gcov-iov.h is taken from a gcc build (produced at compile +time). The file gcov-io.c is unchanged. + +--- gcc-4.7.2/gcc/gcov-io.h 2011-12-04 10:27:19.000000000 -0800 ++++ coreboot/src/lib/gcov-io.h 2013-01-12 16:45:57.000000000 -0800 +@@ -163,6 +163,24 @@ + #ifndef GCC_GCOV_IO_H + #define GCC_GCOV_IO_H + ++#ifdef __COREBOOT__ ++#define GCOV_LINKAGE /* nothing */ ++/* We need the definitions for ++ BITS_PER_UNIT and ++ LONG_LONG_TYPE_SIZE ++ They are defined in gcc/defaults.h and gcc/config/<arch_depend_files> ++ (like, gcc/config/i386/i386.h). And it can be overridden by setting ++ in build scripts. Here I hardcoded the value for x86. */ ++#define BITS_PER_UNIT 8 ++#define LONG_LONG_TYPE_SIZE 64 ++ ++/* There are many gcc_assertions. Set the vaule to 1 if we want a warning ++ message if the assertion fails. */ ++#ifndef ENABLE_ASSERT_CHECKING ++#define ENABLE_ASSERT_CHECKING 1 ++#endif ++#endif /* __COREBOOT__ */ ++ + #if IN_LIBGCOV + /* About the target */ + +@@ -232,7 +250,9 @@ + is not also used in a DSO. */ + #if IN_LIBGCOV + ++#ifndef __COREBOOT__ + #include "tconfig.h" ++#endif /* __COREBOOT__ */ + + #define gcov_var __gcov_var + #define gcov_open __gcov_open +@@ -455,8 +475,10 @@ + /* Register a new object file module. */ + extern void __gcov_init (struct gcov_info *) ATTRIBUTE_HIDDEN; + ++#ifndef __COREBOOT__ + /* Called before fork, to avoid double counting. */ + extern void __gcov_flush (void) ATTRIBUTE_HIDDEN; ++#endif + + /* The merge function that just sums the counters. */ + extern void __gcov_merge_add (gcov_type *, unsigned) ATTRIBUTE_HIDDEN; +--- gcc-4.7.2/libgcc/libgcov.c 2012-01-11 10:50:21.000000000 -0800 ++++ coreboot/src/lib/libgcov.c 2013-01-16 09:45:11.000000000 -0800 +@@ -25,12 +25,41 @@ + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + http://www.gnu.org/licenses/. */ + ++#define __COREBOOT__ ++#ifdef __COREBOOT__ ++#include <stdlib.h> ++#include <string.h> ++#include <console/console.h> ++#include <assert.h> ++typedef s32 pid_t; ++#define gcc_assert(x) ASSERT(x) ++#define fprintf(file, x...) printk(BIOS_ERR, x) ++#define alloca(size) __builtin_alloca (size) ++#include "gcov-glue.c" ++ ++/* Define MACROs to be used by coreboot compilation. */ ++# define L_gcov ++# define L_gcov_interval_profiler ++# define L_gcov_pow2_profiler ++# define L_gcov_one_value_profiler ++# define L_gcov_indirect_call_profiler ++# define L_gcov_average_profiler ++# define L_gcov_ior_profiler ++ ++# define HAVE_CC_TLS 0 ++# define __GCOV_KERNEL__ ++ ++# define IN_LIBGCOV 1 ++# define IN_GCOV 0 ++#else /* __COREBOOT__ */ + #include "tconfig.h" + #include "tsystem.h" + #include "coretypes.h" + #include "tm.h" + #include "libgcc_tm.h" ++#endif /* __COREBOOT__ */ + ++#ifndef __COREBOOT__ + #if defined(inhibit_libc) + #define IN_LIBGCOV (-1) + #else +@@ -41,6 +70,7 @@ + #define GCOV_LINKAGE /* nothing */ + #endif + #endif ++#endif /* __COREBOOT__ */ + #include "gcov-io.h" + + #if defined(inhibit_libc) +@@ -68,12 +98,17 @@ + + #else + ++#ifndef __COREBOOT__ + #include <string.h> + #if GCOV_LOCKED + #include <fcntl.h> + #include <errno.h> + #include <sys/stat.h> + #endif ++#else ++void __gcov_merge_add(gcov_type *counters __attribute__ ((unused)), ++ unsigned n_counters __attribute__ ((unused))) {} ++#endif /* __COREBOOT__ */ + + #ifdef L_gcov + #include "gcov-io.c" +@@ -99,6 +134,10 @@ + static int + create_file_directory (char *filename) + { ++#ifdef __COREBOOT__ ++ (void) filename; ++ return 0; ++#else + #if !defined(TARGET_POSIX_IO) && !defined(_WIN32) + (void) filename; + return -1; +@@ -137,6 +176,7 @@ + }; + return 0; + #endif ++#endif + } + + static struct gcov_fn_buffer * +@@ -279,7 +319,7 @@ + struct gcov_ctr_summary *cs_ptr; + const struct gcov_ctr_info *ci_ptr; + unsigned t_ix; +- int f_ix; ++ int f_ix = 0; + gcov_unsigned_t c_num; + const char *gcov_prefix; + int gcov_prefix_strip = 0; +@@ -329,6 +369,7 @@ + } + } + ++#ifndef __COREBOOT__ + { + /* Check if the level of dirs to strip off specified. */ + char *tmp = getenv("GCOV_PREFIX_STRIP"); +@@ -352,6 +393,7 @@ + prefix_length--; + } + else ++#endif + prefix_length = 0; + + /* If no prefix was specified and a prefix stip, then we assume +@@ -696,8 +738,10 @@ + if (filename_length > gcov_max_filename) + gcov_max_filename = filename_length; + ++#ifndef __COREBOOT__ + if (!gcov_list) + atexit (gcov_exit); ++#endif + + info->next = gcov_list; + gcov_list = info; +@@ -767,14 +811,15 @@ + + #ifdef L_gcov_merge_single + /* The profile merging function for choosing the most common value. +- It is given an array COUNTERS of N_COUNTERS old counters and it +- reads the same number of counters from the gcov file. The counters +- are split into 3-tuples where the members of the tuple have +- meanings: +- +- -- the stored candidate on the most common value of the measured entity +- -- counter +- -- total number of evaluations of the value */ ++ * It is given an array COUNTERS of N_COUNTERS old counters and it ++ * reads the same number of counters from the gcov file. The counters ++ * are split into 3-tuples where the members of the tuple have ++ * meanings: ++ * ++ * -- the stored candidate on the most common value of the measured entity ++ * -- counter ++ * -- total number of evaluations of the value ++ */ + void + __gcov_merge_single (gcov_type *counters, unsigned n_counters) + { +@@ -805,15 +850,16 @@ + + #ifdef L_gcov_merge_delta + /* The profile merging function for choosing the most common +- difference between two consecutive evaluations of the value. It is +- given an array COUNTERS of N_COUNTERS old counters and it reads the +- same number of counters from the gcov file. The counters are split +- into 4-tuples where the members of the tuple have meanings: +- +- -- the last value of the measured entity +- -- the stored candidate on the most common difference +- -- counter +- -- total number of evaluations of the value */ ++ * difference between two consecutive evaluations of the value. It is ++ * given an array COUNTERS of N_COUNTERS old counters and it reads the ++ * same number of counters from the gcov file. The counters are split ++ * into 4-tuples where the members of the tuple have meanings: ++ * ++ * -- the last value of the measured entity ++ * -- the stored candidate on the most common difference ++ * -- counter ++ * -- total number of evaluations of the value ++ */ + void + __gcov_merge_delta (gcov_type *counters, unsigned n_counters) + { diff --git a/Documentation/backup-docs/old/gerrit_guidelines.md b/Documentation/backup-docs/old/gerrit_guidelines.md new file mode 100644 index 0000000..1833b0a --- /dev/null +++ b/Documentation/backup-docs/old/gerrit_guidelines.md @@ -0,0 +1,277 @@ +coreboot Gerrit Etiquette and Guidelines +======================================== + +The following rules are the requirements for behavior in the coreboot +codebase in gerrit. These have mainly been unwritten rules up to this +point, and should be familiar to most users who have been active in +coreboot for a period of time. Following these rules will help reduce +friction in the community. + +Note that as with many rules, there are exceptions. Some have been noted +in the 'More Detail' section. If you feel there is an exception not listed +here, please discuss it in the mailing list to get this document updated. +Don't just assume that it's okay, even if someone on IRC says it is. + + +Summary: +-------- +These are the expectations for committing, reviewing, and submitting code +into coreboot git and gerrit. While breaking individual rules may not have +immediate consequences, the coreboot leadership may act on repeated or +flagrant violations with or without notice. + +* Don't violate the licenses. +* Let non-trivial patches sit in a review state for at least 24 hours +before submission. +* Try to coordinate with platform maintainers when making changes to +platforms. +* If you give a patch a -2, you are responsible for giving concrete +recommendations for what could be changed to resolve the issue the patch +addresses. +* Don't modify other people's patches without their consent. +* Be respectful to others when commenting. +* Don’t submit patches that you know will break other platforms. + + +More detail: +------------ +* Don't violate the licenses. If you're submitting code that you didn't +write yourself, make sure the license is compatible with the license of the +project you're submitting the changes to. If you’re submitting code that +you wrote that might be owned by your employer, make sure that your +employer is aware and you are authorized to submit the code. For +clarification, see the Developer's Certificate of Origin in the coreboot +[Signed-off-by policy](http://www.coreboot.org/Development_Guidelines#Sign-off_Procedure). + +* Let non-trivial patches sit in a review state for at least 24 hours +before submission. Remember that there are coreboot developers in timezones +all over the world, and everyone should have a chance to contribute. +Trivial patches would be things like whitespace changes or spelling fixes. +In general, small changes that don’t impact the final binary output. The +24-hour period would start at submission, and would be restarted at any +update which significantly changes any part of the patch. Patches can be +'Fast-tracked' and submitted in under this 24 hour with the agreement of at +least 3 +2 votes. + +* Do not +2 patches that you authored or own, even for something as trivial +as whitespace fixes. When working on your own patches, it’s easy to +overlook something like accidentally updating file permissions or git +submodule commit IDs. Let someone else review the patch. An exception to +this would be if two people worked in the patch together. If both +2 the +patch, that is acceptable, as each is giving a +2 to the other's work. + +* Try to coordinate with platform maintainers and other significant +contributors to the code when making changes to platforms. The platform +maintainers are the users who initially pushed the code for that platform, +as well as users who have made significant changes to a platform. To find +out who maintains a piece of code, please use util/scripts/maintainers.go +or refer to the original author of the code in git log. + +* If you give a patch a -2, you are responsible for giving concrete +recommendations for what could be changed to resolve the issue the patch +addresses. If you feel strongly that a patch should NEVER be merged, you +are responsible for defending your position and listening to other points +of view. Giving a -2 and walking away is not acceptable, and may cause your + -2 to be removed by the coreboot leadership after no less than a week. A + notification that the -2 will be removed unless there is a response will + be sent out at least 2 days before it is removed. + +* Don't modify other people's patches unless you have coordinated this with +the owner of that patch. Not only is this considered rude, but your changes +could be unintentionally lost. An exception to this would be for patches +that have not been updated for more than 90 days. In that case, the patch +can be taken over if the original author does not respond to requests for +updates. Alternatively, a new patch can be pushed with the original +content, and both patches should be updated to reference the other. + +* Be respectful to others when commenting on patches. Comments should +be kept to the code, and should be kept in a polite tone. We are a +worldwide community and English is a difficult language. Assume your +colleagues are intelligent and do not intend disrespect. Resist the urge to +retaliate against perceived verbal misconduct, such behavior is not +conducive to getting patches merged. + +* Don’t submit code that you know will break other platforms. If your patch +affects code that is used by other platforms, it should be compatible with +those platforms. While it would be nice to update any other platforms, you +must at least provide a path that will allow other platforms to continue +working. + + +Recommendations for gerrit activity: +------------------------------------ +These guidelines are less strict than the ones listed above. These are more +of the “good idea” variety. You are requested to follow the below +guidelines, but there will probably be no actual consequences if they’re +not followed. That said, following the recommendations below will speed up +review of your patches, and make the members of the community do less work. + +* Each patch should be kept to one logical change, which should be +described in the title of the patch. Unrelated changes should be split out +into separate patches. Fixing whitespace on a line you’re editing is +reasonable. Fixing whitespace around the code you’re working on should be a +separate ‘cleanup’ patch. Larger patches that touch several areas are fine, +so long as they are one logical change. Adding new chips and doing code +cleanup over wide areas are two examples of this. + +* Test your patches before submitting them to gerrit. It's also appreciated +if you add a line to the commit message describing how the patch was +tested. This prevents people from having to ask whether and how the patch +was tested. Examples of this sort of comment would be ‘TEST=Built +platform’ or ‘Tested by building and booting platform’. Stating that the +patch was not tested is also fine, although you might be asked to do some +testing in cases where that would be reasonable. + +* Take advantage of the lint tools to make sure your patches don’t contain +trivial mistakes. By running ‘make gitconfig’, the lint-stable tools are +automatically put in place and will test your patches before they are +committed. As a violation of these tools will cause the jenkins build test +to fail, it’s to your advantage to test this before pushing to gerrit. + +* Don't submit patch trains longer than around 20 patches unless you +understand how to manage long patch trains. Long patch trains can become +difficult to handle and tie up the build servers for long periods of time +if not managed well. Rebasing a patch train over and over as you fix +earlier patches in the train can hide comments, and make people review the +code multiple times to see if anything has changed between revisions. When +pushing long patch trains, it is recommended to only push the full patch +train once - the initial time, and only to rebase three or four patches at +a time. + +* Run 'make what-jenkins-does' locally on patch trains before submitting. +This helps verify that the patch train won’t tie up the jenkins builders +for no reason if there are failing patches in the train. For running +parallel builds, you can specify the number of cores to use by setting the +the CPUS environment variable. Example: + make what-jenkins-does CPUS=8 + +* Use a topic when pushing a train of patches. This groups the commits +together so people can easily see the connection at the top level of +gerrit. Topics can be set for individual patches in gerrit by going into +the patch and clicking on the icon next to the topic line. Topics can also +be set when you push the patches into gerrit. For example, to push a set of +commits with the the i915-kernel-x60 set, use the command: + git push origin HEAD:refs/for/master/i915-kernel-x60 + +* If one of your patches isn't ready to be merged, make sure it's obvious +that you don't feel it's ready for merge yet. The preferred way to show +this is by marking in the commit message that it’s not ready until X. The +commit message can be updated easily when it’s ready to be pushed. +Examples of this are "WIP: title" or "[NEEDS_TEST]: title". Another way to +mark the patch as not ready would be to give it a -1 or -2 review, but +isn't as obvious as the commit message. These patches can also be pushed as +drafts as shown in the next guideline. + +* When pushing patches that are not for submission, these should be marked +as such. This can be done in the title ‘[DONOTSUBMIT]’, or can be pushed as +draft commits, so that only explicitly added reviewers will see them. These +sorts of patches are frequently posted as ideas or RFCs for the community +to look at. To push a draft, use the command: + git push origin HEAD:refs/drafts/master + +* Respond to anyone who has taken the time to review your patches, even if +it's just to say that you disagree. While it may seem annoying to address a +request to fix spelling or 'trivial' issues, it’s generally easy to handle +in gerrit’s built-in editor. If you do use the built-in editor, remember to +get that change to your local copy before re-pushing. It's also acceptable +to add fixes for these sorts of comments to another patch, but it's +recommended that that patch be pushed to gerrit before the initial patch +gets submitted. + +* Consider breaking up large individual patches into smaller patches +grouped by areas. This makes the patches easier to review, but increases +the number of patches. The way you want to handle this is a personal +decision, as long as each patch is still one logical change. + +* If you have an interest in a particular area or mainboard, set yourself +up as a ‘maintainer’ of that area by adding yourself to the MAINTAINERS +file in the coreboot root directory. Eventually, this should automatically +add you as a reviewer when an area that you’re listed as a maintainer is +changed. + +* Submit mainboards that you’re working on to the board-status repo. This +helps others and shows that these mainboards are currently being +maintained. At some point, boards that are not up to date in the +board-status repo will probably end up getting removed from the coreboot +master branch. + +* Abandon patches that are no longer useful, or that you don’t intend to +keep working on to get submitted. + +* Bring attention to patches that you would like reviewed. Add reviewers, +ask for reviewers on IRC or even just rebase it against the current +codebase to bring it to the top of the gerrit list. If you’re not sure who +would be a good reviewer, look in the MAINTAINERS file or git history of +the files that you’ve changed, and add those people. + +* Familiarize yourself with the coreboot [commit message +guidelines](http://www.coreboot.org/Git#Commit_messages), before pushing +patches. This will help to keep annoying requests to fix your commit +message to a minimum. + +* If there have been comments or discussion on a patch, verify that the +comments have been addressed before giving a +2. If you feel that a comment +is invalid, please respond to that comment instead of just ignoring it. + +* Be conscientious when reviewing patches. As a reviewer who approves (+2) +a patch, you are responsible for the patch and the effect it has on the +codebase. In the event that the patch breaks things, you are expected to +be actively involved in the cleanup effort. This means you shouldn’t +2 a +patch just because you trust the author of a patch - Make sure you +understand what the implications of a patch might be, or leave the review +to others. Partial reviews, reviewing code style, for example, can be given +a +1 instead of a +2. This also applies if you think the patch looks good, +but may not have the experience to know if there may be unintended +consequences. + +* If there is still ongoing discussion to a patch, try to wait for a +conclusion to the discussion before submitting it to the tree. If you feel +that someone is just bikeshedding, maybe just state that and give a time +that the patch will be submitted if no new objections are raised. + +* When working with patch trains, for minor requests it’s acceptable to +create a fix addressing a comment in another patch at the end of the patch +train. This minimizes rebases of the patch train while still addressing the +request. For major problems where the change doesn’t work as intended or +breaks other platforms, the change really needs to go into the original +patch. + +* When bringing in a patch from another git repo, update the original +git/gerrit tags by prepending the lines with 'Original-'. Marking +the original text this way makes it much easier to tell what changes +happened in which repository. This applies to these lines, not the actual +commit message itself: + Commit-Id: + Change-Id: + Signed-off-by: + Reviewed-on: + Tested-by: + Reviewed-by: +The script 'util/gitconfig/rebase.sh' can be used to help automate this. +Other tags such as 'Commit-Queue' can simply be removed. + + +Expectations contributors should have: +-------------------------------------- +* Don't expect that people will review your patch unless you ask them to. +Adding other people as reviewers is the easiest way. Asking for reviews for +individual patches in the IRC channel, or by sending a direct request to an +individual through your favorite messenger is usually the best way to get a +patch reviewed quickly. + +* Don't expect that your patch will be submitted immediately after getting +a +2. As stated previously, non-trivial patches should wait at least 24 +hours before being submitted. That said, if you feel that your patch or +series of patches has been sitting longer than needed, you can ask for it +to be submitted on IRC, or comment that it's ready for submission in the +patch. This will move it to the top of the list where it's more likely to +be noticed and acted upon. + +* Reviews are about the code. It's easy to take it personally when someone +is criticising your code, but the whole idea is to get better code into our +codebase. Again, this also applies in the other direction: review code, +criticize code, but don’t make it personal. + + +Requests for clarification and suggestions for updates to these guidelines +should be sent to the coreboot mailing list at coreboot@coreboot.org. diff --git a/Documentation/backup-docs/old/hypertransport.svg b/Documentation/backup-docs/old/hypertransport.svg new file mode 100644 index 0000000..757e7f4 --- /dev/null +++ b/Documentation/backup-docs/old/hypertransport.svg @@ -0,0 +1,59 @@ +<?xml version="1.0" encoding="utf-8"?> +<!DOCTYPE svg PUBLIC "-//W3C//DTD SVG 1.1//EN" "http://www.w3.org/Graphics/SVG/1.1/DTD/svg11.dtd"> +<svg version="1.1" id="Layer_1" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink" x="0px" y="0px" + width="256px" height="512px" viewBox="0 0 256 512" enable-background="new 0 0 256 512" xml:space="preserve"> +<font horiz-adv-x="2048"> +<font-face font-family="ArialMT" units-per-em="2048" underline-position="-217" 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mode 100644 index 0000000..f440f8d --- /dev/null +++ b/Documentation/backup-docs/old/mainboard_io_trap_handler_sample.c @@ -0,0 +1,51 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <console/console.h> +#include <cpu/x86/smm.h> +#include <soc/pm.h> +#include <soc/smm.h> +#include <elog.h> +#include <ec/google/chromeec/ec.h> +#include <soc/gpio.h> +#include <soc/iomap.h> +#include <soc/nvs.h> +#include <soc/pm.h> +#include <soc/smm.h> +#include "ec.h" +#include "gpio.h" + +int mainboard_io_trap_handler(int smif) +{ + switch (smif) { + case 0x99: + printk(BIOS_DEBUG, "Sample\n"); + smm_get_gnvs()->smif = 0; + break; + default: + return 0; + } + + /* On success, the IO Trap Handler returns 0 + * On failure, the IO Trap Handler returns a value != 0 + * + * For now, we force the return value to 0 and log all traps to + * see what's going on. + */ + //smm_get_gnvs()->smif = 0; + return 1; +} diff --git a/Documentation/backup-docs/old/submodules.txt b/Documentation/backup-docs/old/submodules.txt new file mode 100644 index 0000000..631e3513 --- /dev/null +++ b/Documentation/backup-docs/old/submodules.txt @@ -0,0 +1,46 @@ +Use of git submodules in coreboot +================================= +coreboot uses git submodules to keep certain parts of the tree separate, +with two major use cases: + +First, we use a vendor tool by NVIDIA for systems based on their SoC +and since they publish it through git, we can just import it into our +tree using submodules. + +Second, lots of boards these days require binaries and we want to keep +them separate from coreboot proper to clearly delineate shiny Open Source +from ugly blobs. +Since we don't want to impose blobs on users who really don't need them, +that repository is only downloaded and checked out on explicit request. + +Handling submodules +------------------- +For the most part, submodules should be automatically checked out on the +first execution of the coreboot Makefile. + +To manually fetch all repositories (eg. when you want to prepare the tree +for archiving, or to use it without network access), run + + $ git submodule update --init --checkout + +This also checks out the binaries below `3rdparty/` + +Mirroring coreboot +------------------ +When running a coreboot mirror to checkout from, for full operation, you +should also mirror the blobs and nvidia-cbootimage repository, and place +them in the same directory as the coreboot repository mirror. + +That is, when residing in coreboot's repository, `cd ../blobs.git` +should move you to the blobs repository. + +With that, no matter what the URL of your coreboot repository is, the +git client (of a sufficiently new version) is able to pick up the other +repositories transparently. + +Minimum requirements +-------------------- +git needs to be able to handle relative paths to submodule repositories, +and it needs to know about non-automatic submodules. + +For these features, we require git version 1.7.6.1 or newer. diff --git a/Documentation/backup-docs/old/timestamp.md b/Documentation/backup-docs/old/timestamp.md new file mode 100644 index 0000000..3a4c73b --- /dev/null +++ b/Documentation/backup-docs/old/timestamp.md @@ -0,0 +1,200 @@ +Table of Contents +================= +Introduction + Transition from cache to cbmem + +Data structures used + cache_state + table + entries + +Function APIs + timestamp_init + timestamp_add + timestamp_add_now + timestamp_sync + +Use / Test Cases + Case 1: Timestamp Region Exists + Case 2: No timestamp region, fresh boot, cbmem_initialize called after + timestamp_init + Case 3: No timestamp region, fresh boot, cbmem_initialize called before + timestamp_init + Case 4: No timestamp region, resume, cbmem_initialize called after + timestamp_init + Case 5: No timestamp region, resume, cbmem_initialize called before + timestamp_init + + +Introduction +============ +The aim of the timestamp library is to make it easier for different boards +to save timestamps in cbmem / stash (until cbmem is brought up) by +providing a simple API to initialize, add and sync timestamps. In order +to make the timestamps persistent and accessible from the kernel, we +need to ensure that all the saved timestamps end up in cbmem under +the CBMEM_ID_TIMESTAMP tag. However, until the cbmem area is available, +the timestamps can be saved to a SoC-defined _timestamp region or in a +local stage-specific stash. The work of identifying the right location for +storing timestamps is done by the library and is not exposed to the user. + +Working of timestamp library from a user perspective can be outlined in +the following steps: +1. Initialize the base time and reset cbmem timestamp area +2. Start adding timestamps + +Behind the scenes, the timestamp library takes care of: +1. Identifying the correct location for storing timestamps (cbmem or timestamp + region or local stash). +2. Once cbmem is up, ensure that all timestamps are synced from timestamp + region or local stash into the cbmem area. +3. Add a new cbmem timestamp area based on whether a reset of the cbmem + timestamp region is required or not. + +Transition from cache to cbmem +------------------------------ +To move timestamps from the cache to cbmem (and initialize the cbmem area in +the first place), we use the CBMEM_INIT_HOOK infrastructure of coreboot. + +When cbmem is initialized, the hook is called, which creates the area, +copies all timestamps to cbmem and disables the cache. + +After such a transition, timestamp_init() must not be run again. + + +Data structures used +==================== +The main structure that maintains information about the timestamp cache is: +struct __attribute__((__packed__)) timestamp_cache { + uint16_t cache_state; + struct timestamp_table table; + struct timestamp_entry entries[MAX_TIMESTAMP_CACHE]; +}; + +cache_state +----------- +The state of the cache is maintained by cache_state attribute which can +be any one of the following: + +enum { + TIMESTAMP_CACHE_UNINITIALIZED = 0, + TIMESTAMP_CACHE_INITIALIZED, + TIMESTAMP_CACHE_NOT_NEEDED, +}; + +By default, if the cache is stored in local stash (bss area), then +it will be reset to uninitialized state. However, if the cache is +stored in timestamp region, then it might have garbage in any of the +attributes. Thus, if the timestamp region is being used by any board, it is +initialized to default values by the library. + +Once the cache is initialized, its state is set to +CACHE_INITIALIZED. Henceforth, the calls to cache i.e. timestamp_add +know that the state reflected is valid and timestamps can be directly +saved in the cache. + +Once the cbmem area is up (i.e. call to timestamp_sync_cache_to_cbmem), +we do not need to store the timestamps in local stash / timestamp area +anymore. Thus, the cache state is set to CACHE_NOT_NEEDED, which allows +timestamp_add to store all timestamps directly into the cbmem area. + + +table +----- +This field is represented by a structure which provides overall +information about the entries in the timestamp area: + +struct timestamp_table { + uint64_t base_time; + uint32_t max_entries; + uint32_t num_entries; + struct timestamp_entry entries[0]; /* Variable number of entries */ +} __attribute__((packed)); + +It indicates the base time for all timestamp entries, maximum number +of entries that can be stored, total number of entries that currently +exist and an entry structure to hold variable number of entries. + + +entries +------- +This field holds the details of each timestamp entry, upto a maximum +of MAX_TIMESTAMP_CACHE which is defined as 16 entries. Each entry is +defined by: + +struct timestamp_entry { + uint32_t entry_id; + uint64_t entry_stamp; +} __attribute__((packed)); + +entry_id holds the timestamp id corresponding to this entry and +entry_stamp holds the actual timestamp. + + +For timestamps stored in the cbmem area, a timestamp_table is allocated +with space for MAX_TIMESTAMPS equal to 30. Thus, the cbmem area holds +base_time, max_entries (which is 30), current number of entries and the +actual entries represented by timestamp_entry. + + +Function APIs +============= + +timestamp_init +-------------- +This function initializes the timestamp cache and should be run as early +as possible. On platforms with SRAM, this might mean in bootblock, on +x86 with its CAR backed memory in romstage, this means romstage before +memory init. + +timestamp_add +------------- +This function accepts from user a timestamp id and time to record in the +timestamp table. It stores the entry in the appropriate table in cbmem +or _timestamp region or local stash. + + +timestamp_add_now +----------------- +This function calls timestamp_add with user-provided id and current time. + + +Use / Test Cases +================ + +The following cases have been considered while designing the timestamp +library. It is important to ensure that any changes made to this library satisfy +each of the following use cases: + +Case 1: Timestamp Region Exists (Fresh Boot / Resume) +----------------------------------------------------- + +In this case, the library needs to call timestamp_init as early as possible to +enable the timestamp cache. Once cbmem is available, the values will be +transferred automatically. + +All regions are automatically reset on initialization. + +Case 2: No timestamp region, fresh boot, cbmem_initialize called after timestamp_init +------------------------------------------------------------------------------------- + +timestamp_init will set up a local cache. cbmem must be initialized before that +cache vanishes - as happens when jumping to the next stage. + +Case 3: No timestamp region, fresh boot, cbmem_initialize called before timestamp_init +-------------------------------------------------------------------------------------- + +This case is not supported right now, just don't call timestamp_init after +cbmem_initialize. (Patches to make this more robust are welcome.) + +Case 4: No timestamp region, resume, cbmem_initialize called after timestamp_init +--------------------------------------------------------------------------------- + +We always reset the cbmem region before using it, so pre-suspend timestamps +will be gone. + +Case 5: No timestamp region, resume, cbmem_initialize called before timestamp_init +---------------------------------------------------------------------------------- + +We always reset the cbmem region before using it, so pre-suspend timestamps +will be gone. diff --git a/Documentation/beginverbatim.tex b/Documentation/beginverbatim.tex deleted file mode 100644 index 453714c..0000000 --- a/Documentation/beginverbatim.tex +++ /dev/null @@ -1 +0,0 @@ -\begin{verbatim} diff --git a/Documentation/cbfs.txt b/Documentation/cbfs.txt deleted file mode 100644 index 7ecc901..0000000 --- a/Documentation/cbfs.txt +++ /dev/null @@ -1,421 +0,0 @@ - -Received: from www.crouse-house.com ([199.45.160.146] - for coreboot@coreboot.org; Fri, 19 Dec 2008 23:11:59 +0100 -From: Jordan Crouse jordan@cosmicpenguin.net - - -Greetings. I apologize for the incompleteness of what I am about to -discuss. I was planning on working on it leisurely, but my employment -circumstances changed and I've been trying to get it completed in a -hurry before I had to leave it behind. - -I've been thinking a lot about LAR lately, and ways to make it more -extensible and robust. Marc and I have been trading ideas back and -forth for a number of months, and over time a clear idea of what I -wanted to do started to take shape. - -My goal was to add small things to LAR while retaining the overall -scheme. Over time, the scheme evolved slightly, but I think you'll find -that it remains true to the original idea. Below is the beginnings of -an architecture document - I did it in text form, but if met with -aclaim, it should be wikified. This presents what I call CBFS - the -next generation LAR for next generation Coreboot. Its easier to -describe what it is by describing what changed: - -A header has been added somewhere in the bootblock similar to Carl -Daniel's scheme. In addition to the coreboot information, the header -reports the size of the ROM, the alignment of the blocks, and the offset -of the first component in the CBFS. The master header provides all -the information LAR needs plus the magic number information flashrom needs. - -Each "file" (or component, as I style them) now has a type associated -with it. The type is used by coreboot to identify the type of file that -it is loading, and it can also be used by payloads to group items in the -CBFS by type (i.e - bayou can ask for all components that are payloads). - -The header on each "file" (or component, as I like to style them) has -been simplified - We now only store the length, the type, the checksum, -and the offset to the data. The name scheme remains the same. The -addtional information, which is component specific, has been moved to -the component itself (see below). - -The components are arranged in the ROM aligned along the specified -alignment from the master header - this is to facilitate partial re-write. - -Other then that, the LAR ideas remain pretty much the same. - -The plan for moving the metadata to the components is to allow many -different kinds of components, not all of which are groked by coreboot. - However, there are three essential component types that are groked by -coreboot, and they are defined: - -stage - the stage is being parsed from the original ELF, and stored in -the ROM as a single blob of binary data. The load address, start -address, compression type and length are stored in the component sub-header. - -payload - this is essentially SELF in different clothing - same idea as -SELF, with the sub-header as above. - -optionrom - This is in flux - right now, the optionrom is stored -unadulterated and uncompressed, but that is likely to be changed. - -Following this email are two replies containing the v3 code and a new -ROM tool to implement this respectively. I told you that I was trying -to get this out before I disappear, and I'm not kidding - the code is -compile tested and not run-tested. I hope that somebody will embrace -this code and take it the rest of the way, otherwise it will die a -pretty short death. - -I realize that this will start an awesome flamewar, and I'm looking -forward to it. Thanks for listening to me over the years - and good -luck with coreboot. When you all make a million dollars, send me a few -bucks, will you? - -Jordan - -Coreboot CBFS Specification -Jordan Crouse jordan@cosmicpenguin.net - -= Introduction = - -This document describes the coreboot CBFS specification (from here -referred to as CBFS). CBFS is a scheme for managing independent chunks -of data in a system ROM. Though not a true filesystem, the style and -concepts are similar. - - -= Architecture = - -The CBFS architecture looks like the following: - -/---------------\ <-- Start of ROM -| /-----------\ | --| -| | Header | | | -| |-----------| | | -| | Name | | |-- Component -| |-----------| | | -| |Data | | | -| |.. | | | -| -----------/ | --| -| | -| /-----------\ | -| | Header | | -| |-----------| | -| | Name | | -| |-----------| | -| |Data | | -| |.. | | -| -----------/ | -| | -| ... | -| /-----------\ | -| | | | -| | Bootblock | | -| | --------- | | -| | Reset | | <- 0xFFFFFFF0 -| -----------/ | ----------------/ - - -The CBFS architecture consists of a binary associated with a physical -ROM disk referred hereafter as the ROM. A number of independent of -components, each with a header prepended on to data are located within -the ROM. The components are nominally arranged sequentially, though they -are aligned along a pre-defined boundary. - -The bootblock occupies the last 20k of the ROM. Within -the bootblock is a master header containing information about the ROM -including the size, alignment of the components, and the offset of the -start of the first CBFS component within the ROM. - -= Master Header = - -The master header contains essential information about the ROM that is -used by both the CBFS implementation within coreboot at runtime as well -as host based utilities to create and manage the ROM. The master header -will be located somewhere within the bootblock (last 20k of the ROM). A -pointer to the location of the header will be located at offset --4 from the end of the ROM. This translates to address 0xFFFFFFFC on a -normal x86 system. The pointer will be to physical memory somewhere -between - 0xFFFFB000 and 0xFFFFFFF0. This makes it easier for coreboot -to locate the header at run time. Build time utilities will -need to read the pointer and do the appropriate math to locate the header. - -The following is the structure of the master header: - -struct cbfs_header { - u32 magic; - u32 version; - u32 romsize; - u32 bootblocksize; - u32 align; - u32 offset; - u32 architecture; - u32 pad[1]; -} __attribute__((packed)); - -The meaning of each member is as follows: - -'magic' is a 32 bit number that identifies the ROM as a CBFS type. The -magic -number is 0x4F524243, which is 'ORBC' in ASCII. - -'version' is a version number for CBFS header. cbfs_header structure may be -different if version is not matched. - -'romsize' is the size of the ROM in bytes. Coreboot will subtract 'size' from -0xFFFFFFFF to locate the beginning of the ROM in memory. - -'bootblocksize' is the size of bootblock reserved in firmware image. - -'align' is the number of bytes that each component is aligned to within the -ROM. This is used to make sure that each component is aligned correctly -with -regards to the erase block sizes on the ROM - allowing one to replace a -component at runtime without disturbing the others. - -'offset' is the offset of the the first CBFS component (from the start of -the ROM). This is to allow for arbitrary space to be left at the beginning -of the ROM for things like embedded controller firmware. - -'architecture' describes which architecture (x86, arm, ...) this CBFS is created -for. - -= Bootblock = -The bootblock is a mandatory component in the ROM. It is located in the -last -20k of the ROM space, and contains, among other things, the location of the -master header and the entry point for the loader firmware. The bootblock -does not have a component header attached to it. - -= Components = - -CBFS components are placed in the ROM starting at 'offset' specified in -the master header and ending at the bootblock. Thus the total size -available -for components in the ROM is (ROM size - 20k - 'offset'). Each CBFS -component is to be aligned according to the 'align' value in the header. -Thus, if a component of size 1052 is located at offset 0 with an 'align' -value -of 1024, the next component will be located at offset 2048. - -Each CBFS component will be indexed with a unique ASCII string name of -unlimited size. - -Each CBFS component starts with a header: - -struct cbfs_file { - char magic[8]; - unsigned int len; - unsigned int type; - unsigned int checksum; - unsigned int offset; -}; - -'magic' is a magic value used to identify the header. During runtime, -coreboot will scan the ROM looking for this value. The default magic is -the string 'LARCHIVE'. - -'len' is the length of the data, not including the size of the header and -the size of the name. - -'type' is a 32 bit number indicating the type of data that is attached. -The data type is used in a number of ways, as detailed in the section -below. - -'checksum' is a 32bit checksum of the entire component, including the -header and name. - -'offset' is the start of the component data, based off the start of the -header. -The difference between the size of the header and offset is the size of the -component name. - -Immediately following the header will be the name of the component, -which will -null terminated and 16 byte aligned. The following picture shows the -structure of the header: - -/--------\ <- start -| Header | -|--------| <- sizeof(struct cbfs_file) -| Name | -|--------| <- 'offset' -| Data | -| ... | ---------/ <- start + 'offset' + 'len' - -== Searching Alogrithm == - -To locate a specific component in the ROM, one starts at the 'offset' -specified in the CBFS master header. For this example, the offset will -be 0. - - From that offset, the code should search for the magic string on the -component, jumping 'align' bytes each time. So, assuming that 'align' is -16, the code will search for the string 'LARCHIVE' at offset 0, 16, 32, etc. -If the offset ever exceeds the allowable range for CBFS components, then no -component was found. - -Upon recognizing a component, the software then has to search for the -specific name of the component. This is accomplished by comparing the -desired name with the string on the component located at -offset + sizeof(struct cbfs_file). If the string matches, then the -component -has been located, otherwise the software should add 'offset' + 'len' to -the offset and resume the search for the magic value. - -== Data Types == - -The 'type' member of struct cbfs_file is used to identify the content -of the component data, and is used by coreboot and other -run-time entities to make decisions about how to handle the data. - -There are three component types that are essential to coreboot, and so -are defined here. - -=== Stages === - -Stages are code loaded by coreboot during the boot process. They are -essential to a successful boot. Stages are comprised of a single blob -of binary data that is to be loaded into a particular location in memory -and executed. The uncompressed header contains information about how -large the data is, and where it should be placed, and what additional memory -needs to be cleared. - -Stages are assigned a component value of 0x10. When coreboot sees this -component type, it knows that it should pass the data to a sub-function -that will process the stage. - -The following is the format of a stage component: - -/--------\ -| Header | -|--------| -| Binary | -| .. | ---------/ - -The header is defined as: - -struct cbfs_stage { - unsigned int compression; - unsigned long long entry; - unsigned long long load; - unsigned int len; - unsigned int memlen; -}; - -'compression' is an integer defining how the data is compressed. There -are three compression types defined by this version of the standard: -none (0x0), lzma (0x1), and nrv2b (0x02, deprecated), though additional -types may be added assuming that coreboot understands how to handle the scheme. - -'entry' is a 64 bit value indicating the location where the program -counter should jump following the loading of the stage. This should be -an absolute physical memory address. - -'load' is a 64 bit value indicating where the subsequent data should be -loaded. This should be an absolute physical memory address. - -'len' is the length of the compressed data in the component. - -'memlen' is the amount of memory that will be used by the component when -it is loaded. - -The component data will start immediately following the header. - -When coreboot loads a stage, it will first zero the memory from 'load' to -'memlen'. It will then decompress the component data according to the -specified scheme and place it in memory starting at 'load'. Following that, -it will jump execution to the address specified by 'entry'. -Some components are designed to execute directly from the ROM - coreboot -knows which components must do that and will act accordingly. - -=== Payloads === - -Payloads are loaded by coreboot following the boot process. - -Stages are assigned a component value of 0x20. When coreboot sees this -component type, it knows that it should pass the data to a sub-function -that will process the payload. Furthermore, other run time -applications such as 'bayou' may easily index all available payloads -on the system by searching for the payload type. - - -The following is the format of a stage component: - -/-----------\ -| Header | -| Segment 1 | -| Segment 2 | -| ... | -|-----------| -| Binary | -| .. | ------------/ - -The header is as follows: - -struct cbfs_payload { - struct cbfs_payload_segment segments; -} - -The header contains a number of segments corresponding to the segments -that need to be loaded for the payload. - -The following is the structure of each segment header: - -struct cbfs_payload_segment { - unsigned int type; - unsigned int compression; - unsigned int offset; - unsigned long long load_addr; - unsigned int len; - unsigned int mem_len; -}; - -'type' is the type of segment, one of the following: - -PAYLOAD_SEGMENT_CODE 0x45444F43 The segment contains executable code -PAYLOAD_SEGMENT_DATA 0x41544144 The segment contains data -PAYLOAD_SEGMENT_BSS 0x20535342 The memory speicfied by the segment - should be zeroed -PAYLOAD_SEGMENT_PARAMS 0x41524150 The segment contains information for - the payload -PAYLOAD_SEGMENT_ENTRY 0x52544E45 The segment contains the entry point - for the payload - -'compression' is the compression scheme for the segment. Each segment can -be independently compressed. There are three compression types defined by -this version of the standard: none (0x0), lzma (0x1), and nrv2b -(0x02, deprecated), though additional types may be added assuming that -coreboot understands how to handle the scheme. - -'offset' is the address of the data within the component, starting from -the component header. - -'load_addr' is a 64 bit value indicating where the segment should be placed -in memory. - -'len' is a 32 bit value indicating the size of the segment within the -component. - -'mem_len' is the size of the data when it is placed into memory. - -The data will located immediately following the last segment. - -=== Option ROMS === - -The third specified component type will be Option ROMs. Option ROMS will -have component type '0x30'. They will have no additional header, the -uncompressed binary data will be located in the data portion of the -component. - -=== NULL === - -There is a 4th component type ,defined as NULL (0xFFFFFFFF). This is -the "don't care" component type. This can be used when the component -type is not necessary (such as when the name of the component is unique. -i.e. option_table). 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b/Documentation/config.toml @@ -0,0 +1,53 @@ +baseurl = "http://docs.coreboot.org" +languageCode = "en-us" +title = "Coreboot Documentation" +theme = "hugo-material-docs" +metadataformat = "yaml" +canonifyurls = true +googleAnalytics = "" + +[params] + # General information + author = "Coreboot Developers" + description = "The documentation base of coreboot." + copyright = "GPLv2" + + # Repository + provider = "Gerrit" + repo_url = "https://review.coreboot.org" + + version = "" + logo = "images/logo.png" + favicon = "favicon.ico" + + permalink = "#" + + # Custom assets + custom_css = [] + custom_js = [] + + # Syntax highlighting theme + highlight_css = "" + +[params.palette] + primary = "grey" + accent = "blue grey" + +[params.font] + text = "Ubuntu" + code = "Ubuntu Mono" + +[social] + twitter = "coreboot_org" + github = "coreboot" + +[[menu.main]] + name = "The Project" + url = "/" + weight = 0 + +[blackfriday] + smartypants = true + fractions = true + smartDashes = true + plainIDAnchors = true diff --git a/Documentation/content/docs/core/index.md b/Documentation/content/docs/core/index.md new file mode 100644 index 0000000..433b764 --- /dev/null +++ b/Documentation/content/docs/core/index.md @@ -0,0 +1,8 @@ +--- +date: 2016-07-01T19:25:34.000Z +title: Core Documentation +name: Core Documentation +weight: 10 +menu: + main: +--- diff --git a/Documentation/content/docs/core/timestamps.md b/Documentation/content/docs/core/timestamps.md new file mode 100644 index 0000000..6c316f0 --- /dev/null +++ b/Documentation/content/docs/core/timestamps.md @@ -0,0 +1,116 @@ +--- +date: 2016-07-01T19:25:34.000Z +title: Timestamps +name: Timestamps +weight: 20 +menu: + main: + parent: Core Documentation +--- + +## Table of Contents + +Introduction Transition from cache to cbmem + +Data structures used cache_state table entries + +Function APIs timestamp_init timestamp_add timestamp_add_now timestamp_sync + +Use / Test Cases Case 1: Timestamp Region Exists Case 2: No timestamp region, fresh boot, cbmem_initialize called after timestamp_init Case 3: No timestamp region, fresh boot, cbmem_initialize called before timestamp_init Case 4: No timestamp region, resume, cbmem_initialize called after timestamp_init Case 5: No timestamp region, resume, cbmem_initialize called before timestamp_init + +## Introduction + +The aim of the timestamp library is to make it easier for different boards to save timestamps in cbmem / stash (until cbmem is brought up) by providing a simple API to initialize, add and sync timestamps. In order to make the timestamps persistent and accessible from the kernel, we need to ensure that all the saved timestamps end up in cbmem under the CBMEM_ID_TIMESTAMP tag. However, until the cbmem area is available, the timestamps can be saved to a SoC-defined _timestamp region or in a local stage-specific stash. The work of identifying the right location for storing timestamps is done by the library and is not exposed to the user. + +Working of timestamp library from a user perspective can be outlined in the following steps: + +1. Initialize the base time and reset cbmem timestamp area +2. Start adding timestamps + +Behind the scenes, the timestamp library takes care of: + +1. Identifying the correct location for storing timestamps (cbmem or timestamp region or local stash). +2. Once cbmem is up, ensure that all timestamps are synced from timestamp region or local stash into the cbmem area. +3. Add a new cbmem timestamp area based on whether a reset of the cbmem timestamp region is required or not. + +## Transition from cache to cbmem + +To move timestamps from the cache to cbmem (and initialize the cbmem area in the first place), we use the CBMEM_INIT_HOOK infrastructure of coreboot. + +When cbmem is initialized, the hook is called, which creates the area, copies all timestamps to cbmem and disables the cache. + +After such a transition, timestamp_init() must not be run again. + +# Data structures used + +The main structure that maintains information about the timestamp cache is: struct **attribute**((**packed**)) timestamp_cache { uint16_t cache_state; struct timestamp_table table; struct timestamp_entry entries[MAX_TIMESTAMP_CACHE]; }; + +## cache_state + +The state of the cache is maintained by cache_state attribute which can be any one of the following: + +enum { TIMESTAMP_CACHE_UNINITIALIZED = 0, TIMESTAMP_CACHE_INITIALIZED, TIMESTAMP_CACHE_NOT_NEEDED, }; + +By default, if the cache is stored in local stash (bss area), then it will be reset to uninitialized state. However, if the cache is stored in timestamp region, then it might have garbage in any of the attributes. Thus, if the timestamp region is being used by any board, it is initialized to default values by the library. + +Once the cache is initialized, its state is set to CACHE_INITIALIZED. Henceforth, the calls to cache i.e. timestamp_add know that the state reflected is valid and timestamps can be directly saved in the cache. + +Once the cbmem area is up (i.e. call to timestamp_sync_cache_to_cbmem), we do not need to store the timestamps in local stash / timestamp area anymore. Thus, the cache state is set to CACHE_NOT_NEEDED, which allows timestamp_add to store all timestamps directly into the cbmem area. + +## table + +This field is represented by a structure which provides overall information about the entries in the timestamp area: + +struct timestamp_table { uint64_t base_time; uint32_t max_entries; uint32_t num_entries; struct timestamp_entry entries[0]; / _Variable number of entries_ / } __attribute__((packed)); + +It indicates the base time for all timestamp entries, maximum number of entries that can be stored, total number of entries that currently exist and an entry structure to hold variable number of entries. + +### entries + +This field holds the details of each timestamp entry, upto a maximum of MAX_TIMESTAMP_CACHE which is defined as 16 entries. Each entry is defined by: + +struct timestamp_entry { uint32_t entry_id; uint64_t entry_stamp; } __attribute__((packed)); + +entry_id holds the timestamp id corresponding to this entry and entry_stamp holds the actual timestamp. + +For timestamps stored in the cbmem area, a timestamp_table is allocated with space for MAX_TIMESTAMPS equal to 30. Thus, the cbmem area holds base_time, max_entries (which is 30), current number of entries and the actual entries represented by timestamp_entry. + +## Function APIs + +### timestamp_init + +This function initializes the timestamp cache and should be run as early as possible. On platforms with SRAM, this might mean in bootblock, on x86 with its CAR backed memory in romstage, this means romstage before memory init. + +### timestamp_add + +This function accepts from user a timestamp id and time to record in the timestamp table. It stores the entry in the appropriate table in cbmem or _timestamp region or local stash. + +## timestamp_add_now + +This function calls timestamp_add with user-provided id and current time. + +# Use / Test Cases + +The following cases have been considered while designing the timestamp library. It is important to ensure that any changes made to this library satisfy each of the following use cases: + +## Case 1: Timestamp Region Exists (Fresh Boot / Resume) + +In this case, the library needs to call timestamp_init as early as possible to enable the timestamp cache. Once cbmem is available, the values will be transferred automatically. + +All regions are automatically reset on initialization. + +## Case 2: No timestamp region, fresh boot, cbmem_initialize called after timestamp_init + +timestamp_init will set up a local cache. cbmem must be initialized before that cache vanishes - as happens when jumping to the next stage. + +## Case 3: No timestamp region, fresh boot, cbmem_initialize called before timestamp_init + +This case is not supported right now, just don't call timestamp_init after cbmem_initialize. (Patches to make this more robust are welcome.) + +## Case 4: No timestamp region, resume, cbmem_initialize called after timestamp_init + +We always reset the cbmem region before using it, so pre-suspend timestamps will be gone. + +## Case 5: No timestamp region, resume, cbmem_initialize called before timestamp_init + +We always reset the cbmem region before using it, so pre-suspend timestamps will be gone. diff --git a/Documentation/content/docs/vendor/intel/boards/boards.md b/Documentation/content/docs/vendor/intel/boards/boards.md new file mode 100644 index 0000000..0ae64d3 --- /dev/null +++ b/Documentation/content/docs/vendor/intel/boards/boards.md @@ -0,0 +1,169 @@ +--- +date: 2016-07-01T19:25:34.000Z +title: Boards +name: Boards +weight: 60 +menu: + main: + parent: Intel Documentation +--- + +## x86 Board Development + +Board development requires System-on-a-Chip (SoC) support. The combined steps are listed [here](../development.html). The development steps for the board are listed below: + +1. [Required Files](#RequiredFiles) +2. Enable [Serial Output](#SerialOutput) +3. Load the [Memory Timing Data](#SpdData) +4. [Disable](#DisablePciDevices) the PCI devices +5. [ACPI Tables](#AcpiTables) + +-------------------------------------------------------------------------------- + +## [Required Files]() + +Create the board directory as src/mainboard/<Vendor>/<Board>. + +The following files are required to build a new board: + +1. Kconfig.name - Defines the Kconfig value for the board +2. Kconfig + + 1. Selects the SoC for the board and specifies the SPI flash size + + 1. BOARD_ROMSIZE_KB_<Size> + 2. SOC_<Vendor>_<Chip Family> + + 2. Declare the Kconfig values for: + + 1. MAINBOARD_DIR + 2. MAINBOARD_PART_NUMBER + 3. MAINBOARD_VENDOR + +3. devicetree.cb - Enable root bridge and serial port + + 1. The first line must be "chip soc/Intel/<soc family>"; this path is used by the generated static.c to include the chip.h header file + +4. romstage.c + + 1. Add routine mainboard_romstage_entry which calls romstage_common + +5. Configure coreboot build: + + 1. Set LOCALVERSION + 2. Select vendor for the board + 3. Select the board + 4. CBFS_SIZE = 0x00100000 + 5. Set the CPU_MICROCODE_CBFS_LEN + 6. Set the CPU_MICROCODE_CBFS_LOC + 7. Set the FSP_IMAGE_ID_STRING + 8. Set the FSP_LOC + 9. Disable GOP_SUPPORT + 10. No payload + 11. Choose the default value for all other options + +-------------------------------------------------------------------------------- + +# [Enable Serial Output]() + +Use the following steps to enable serial output: + +1. Implement the car_mainboard_pre_console_init routine in the com_init.c file: + + 1. Power on and enable the UART controller + 2. Connect the UART receive and transmit data lines to the appropriate SoC pins + +2. Add Makefile.inc + + 1. Add com_init.c to romstage + +-------------------------------------------------------------------------------- + +# [Memory Timing Data]() + +Memory timing data is located in the flash. This data is in the format of [serial presence detect](https://en.wikipedia.org/wiki/Serial_presence_detect) (SPD) data. Use the following steps to load the SPD data: + +1. Edit Kconfig to add the DISPLAY_SPD_DATA" value which enables the display of the SPD data being passed to MemoryInit +2. Create an "spd" subdirectory +3. Create an spd/spd.c file for the SPD implementation + + 1. Implement the mainboard_fill_spd_data routine + + 1. Read the SPD data either from the spd.bin file or using I2C or SMBUS + 2. Fill in the pei_data structure with SPD data for each of the DIMMs + 3. Set the DIMM channel configuration + +4. Add an .spd.hex file containing the memory timing data to the spd subdirectory + +5. Create spd/Makefile.inc + + 1. Add spd.c to romstage + 2. Add the .spd.hex file to SPD_SOURCES + +6. Edit Makefile.inc to add the spd subdirectory + +7. Edit romstage.c + + 1. Call mainboard_fill_spd_data + 2. Add mainboard_memory_init_params to copy the SPD and DRAM configuration data from the pei_data structure into the UPDs for MemoryInit + +8. Edit devicetree.cb + + 1. Include the UPD parameters for MemoryInit except for: + + - Address of SPD data + - DRAM configuration set above + +9. A working FSP [MemoryInit](../fsp1_1.html#MemoryInit) routine is required to complete debugging + +10. Debug the result until port 0x80 outputs + + 1. 0x34: - Just after entering [raminit](http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/...) + 2. 0x36: - Just before displaying the [UPD parameters](http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/...) for FSP MemoryInit + 3. 0x92: [POST_FSP_MEMORY_INIT](http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/consol...) - Just before calling FSP [MemoryInit](http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/...) + 4. 0x37: - Just after returning from FSP [MemoryInit](http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/...) + +11. Continue debugging with CONFIG_DISPLAY_HOBS enabled until TempRamExit is called + +-------------------------------------------------------------------------------- + +# [Disable PCI Devices]() + +Ramstage's BS_DEV_ENUMERATE state displays the PCI vendor and device IDs for all of the devices in the system. Edit the devicetree.cb file: + +1. Edit the devicetree.cb file: + + 1. Add an entry for a PCI device.function and turn it off. The entry should look similar to: + + ``` + device pci 14.0 off end + ``` + + 2. Turn on the devices for: + + - Memory Controller + - Debug serial device + +2. Debug until the BS_DEV_ENUMERATE state shows the proper state for all of the devices + +-------------------------------------------------------------------------------- + +# [ACPI Tables]() + +1. Edit Kconfig + + 1. Add "select HAVE_ACPI_TABLES" + +2. Add the acpi_tables.c module: + + 1. Include soc/acpi.h + 2. Add the acpi_create_fadt routine + + 1. fill in the ACPI header + 2. Call the acpi_fill_in_fadt routine + +3. Add the dsdt.asl module: + +-------------------------------------------------------------------------------- + +Modified: 20 February 2016 diff --git a/Documentation/content/docs/vendor/intel/boards/galileo.md b/Documentation/content/docs/vendor/intel/boards/galileo.md new file mode 100644 index 0000000..c557834 --- /dev/null +++ b/Documentation/content/docs/vendor/intel/boards/galileo.md @@ -0,0 +1,100 @@ +--- +date: 2016-07-01T19:25:34.000Z +title: Galileo Board +name: Galileo Board +weight: 70 +menu: + main: + parent: Intel Documentation +--- + +## Intel® Galileo Development Board + ++--------------------------------------+--------------------------------------+ +| [](http | Intel® [Quark™](../SoC/quark.html) | +| ://www.mouser.com/images/microsites/ | SoC: | +| Intel_Galileo2_lrg.jpg) | - [Overall](../development.html) | +| | development | +| | - [SoC](../SoC/soc.html) support | +| | - [FSP 1.1](../fsp1_1.html) | +| | integration | +| | - [Board](board.html) support | +| | - [Implementation | +| | Checklist](Galileo_checklist.htm | +| | l) | ++--------------------------------------+--------------------------------------+ + +## Galileo Board Documentation + +- Common Components + + - A/D: Texas Instruments [ADC108S102](http://www.ti.com/lit/ds/symlink/adc108s102.pdf) + - Analog Switch: Texas Instruments [TS5A23159](http://www.ti.com/lit/ds/symlink/ts5a23159.pdf) + - Ethernet (10/100 MB/S): Texas Instruments [DP83848](http://www.ti.com/lit/ds/symlink/dp83848-ep.pdf) + - Load Switch: Texas Instruments [TPS22920x](http://www.ti.com/lit/ds/symlink/tps22920.pdf) + - Memory (256 MiB): Micron [MT41K128M8](https://www.micron.com/~/media/Documents/Products/Data%20Sheet/DRAM/DDR3/1Gb...) + - SoC: Intel® Quark™ [X-1000](../SoC/quark.html) + - Serial EEPROM (1 KiB): ON Semiconductor® [CAT24C08](http://www.onsemi.com/pub_link/Collateral/CAT24C01-D.PDF) + - SPI Flash (8 MiB): Winbond™ [W25Q64FV](http://www.winbond-usa.com/resource-files/w25q64fv_revl1_100713.pdf) + - Step Down Converter: Texas Instruments [TPS62130](http://www.ti.com/lit/ds/slvsag7c/slvsag7c.pdf) + - Step Down Converter: Texas Instruments [TPS652510](http://www.ti.com/lit/ug/slvu570/slvu570.pdf) + - Termination Regulator: Texas Instruments [TPS51200](http://www.ti.com/lit/ds/symlink/tps51200.pdf) + +- Make a bootable [micro SD card](https://software.intel.com/en-us/get-started-galileo-linux-step1) + +### Galileo Gen 2 Board Documentation + +- [Block Diagram](http://files.linuxgizmos.com/intel_galileo_gen2_blockdiagram.jpg) +- [Getting Started](https://software.intel.com/en-us/iot/library/galileo-getting-started) +- [Overview](http://www.intel.com/content/www/us/en/embedded/products/galileo/galileo-ove...) +- [Port Diagram](http://files.linuxgizmos.com/intel_galileo_gen2_ports.jpg) +- [Product Brief](http://download.intel.com/support/galileo/sb/intelgalileogen2prodbrief_33073...) +- [Schematic](http://www.intel.com/content/dam/www/public/us/en/documents/guides/galileo-g...) +- [User Guide](http://download.intel.com/support/galileo/sb/galileo_boarduserguide_330237_0...) +- Components + + - A/D: Texas Instruments [ADC108S102](http://www.ti.com/lit/ds/symlink/adc108s102.pdf) + - I2C 16-channel, 12-bit PWM: NXP Semiconductors [PCA9685](http://cache.nxp.com/documents/data_sheet/PCA9685.pdf) + - I2C I/O Ports: NXP Semiconductors [PCAL9535A](http://www.nxp.com/documents/data_sheet/PCAL9535A.pdf) + - Octal Buffer/Driver: Texas Instruments [SN74LV541AT](http://www.ti.com/lit/ds/symlink/sn74lv541at.pdf) + - Quadruple Bus Buffer: Texas Instruments [SN74LV125A](http://www.ti.com/lit/ds/symlink/sn74lv125a.pdf) + - Quadruple Bus Buffer with 3-State Outputs: Texas Instruments [SN74LVC126A](http://www.ti.com/lit/ds/symlink/sn74lvc126a.pdf) + - Serial EEPROM (1 KiB): ON Semiconductor® [CAT24C08](http://www.onsemi.com/pub_link/Collateral/CAT24C01-D.PDF) + - Single 2-input multiplexer: NXP Semiconductors [74LVC1G157](http://www.nxp.com/documents/data_sheet/74LVC1G157.pdf) + - Step Down Converter: Texas Instruments [TPS62130](http://www.ti.com/lit/ds/slvsag7c/slvsag7c.pdf) + +### Galileo Gen 1 Board Documentation + +- [Datasheet](http://www.intel.com/content/dam/www/public/us/en/documents/datasheets/galil...) +- [Schematic](http://www.intel.com/content/dam/www/public/us/en/documents/guides/galileo-g...) +- Components + + - A/D: Analog Devices [AD7298](http://www.analog.com/media/en/technical-documentation/data-sheets/AD7298-1....) + - Analog Switch, 2 channel: Texas Instruments [TS5A23159](http://www.ti.com.cn/cn/lit/ds/symlink/ts5a23159.pdf) + - EEPROM & GPIO: Cypress [CY8C9540A](http://www.cypress.com/file/37971/download) + - Power Distribution Switch: Texas Instruments [TPS2051BDBVR](http://www.ti.com/lit/ds/symlink/tps2044b.pdf) + - RS232 Converter: Texas Instruments [MAX3232](http://www.ti.com/lit/ds/symlink/max3232.pdf) + - Voltage-Level Translator: Texas Instruments[TXS0108E](http://www.ti.com/lit/ds/symlink/txs0108e.pdf) + +-------------------------------------------------------------------------------- + +## Debug Tools + +- Flash Programmer: + + - Dediprog [SF100](http://www.dediprog.com/pd/spi-flash-solution/SF100) ISP IC Programmer + +- JTAG Connector: [Olimex ARM-JTAG-20-10](https://www.google.com/webhp?sourceid=chrome-instant&ion=1&espv=2&am...) +- JTAG Debugger: + + - Olimex LTD [ARM-USB-OCD-H](https://www.google.com/webhp?sourceid=chrome-instant&ion=1&espv=2&am...) + - Tincan Tools [Flyswatter2](https://www.tincantools.com/wiki/Flyswatter2) + +- [Hardware Setup and Software Installation](http://download.intel.com/support/processors/quark/sb/sourcedebugusingopenoc...) +- USB Serial cable: FTDI [TTL-232R-3V3](https://www.google.com/webhp?sourceid=chrome-instant&ion=1&espv=2&am...) + +-------------------------------------------------------------------------------- + +Modified: 29 February 2016 diff --git a/Documentation/content/docs/vendor/intel/boards/galileo_checklist.md b/Documentation/content/docs/vendor/intel/boards/galileo_checklist.md new file mode 100644 index 0000000..d4fd55b --- /dev/null +++ b/Documentation/content/docs/vendor/intel/boards/galileo_checklist.md @@ -0,0 +1,1356 @@ +--- +date: 2016-07-01T19:25:34.000Z +title: Galileo Checklist +name: Galileo Checklist +weight: 80 +menu: + main: + parent: Intel Documentation +--- + +## Galileo Implementation Status + +<table> +<tr> +<td colspan="2"> +**Legend** + +</td> +</tr> +<tr> +<td bgcolor="#ffc0c0"> +Red + +</td> +<td> +Required - To-be-implemented + +</td> +</tr> +<tr> +<td bgcolor="#ffffc0"> +Yellow + +</td> +<td> +Optional + +</td> +</tr> +<tr> +<td bgcolor="#c0ffc0"> +Green + +</td> +<td> +Implemented + +</td> +</tr> +</table> +<table> +<tr valign="top"> +<td> +<table border="1"> +<tr> +<th colspan="2"> +bootblock: 100% Done + +</th> +</tr> +<tr> +<th> +Type + +</th> +<th> +Routine + +</td> +</tr> +<tr bgcolor="#ffffc0"> +<td> +Optional + +</td> +<td> +bootblock_c_entry + +</td> +</tr> +<tr bgcolor="#c0ffc0"> +<td> +Required + +</td> +<td> +bootblock_main_with_timestamp + +</td> +</tr> +<tr bgcolor="#ffffc0"> +<td> +Optional + +</td> +<td> +bootblock_mainboard_early_init + +</td> +</tr> +<tr bgcolor="#ffffc0"> +<td> +Optional + +</td> +<td> +bootblock_mainboard_init + +</td> +</tr> +<tr bgcolor="#c0ffc0"> +<td> +Required + +</td> +<td> +bootblock_pre_c_entry + +</td> +</tr> +<tr bgcolor="#c0ffc0"> +<td> +Required + +</td> +<td> +bootblock_protected_mode_entry + +</td> +</tr> +<tr bgcolor="#c0ffc0"> +<td> +Required + +</td> +<td> +bootblock_soc_early_init + +</td> +</tr> +<tr bgcolor="#ffffc0"> +<td> +Optional + +</td> +<td> +bootblock_soc_init + +</td> +</tr> +<tr bgcolor="#c0ffc0"> +<td> +Required + +</td> +<td> +tsc_freq_mhz + +</td> +</tr> +<tr bgcolor="#c0ffc0"> +<td> +Required + +</td> +<td> +uart_init + +</td> +</tr> +</table> +</td> +<td width="5"> + + +</td> +<td> +<table border="1"> +<tr> +<th colspan="2"> +romstage: 66% Done + +</th> +</tr> +<tr> +<th> +Type + +</th> +<th> +Routine + +</td> +</tr> +<tr bgcolor="#ffffc0"> +<td> +Optional + +</td> +<td> +arch_segment_loaded + +</td> +</tr> +<tr bgcolor="#ffffc0"> +<td> +Optional + +</td> +<td> +backup_top_of_ram + +</td> +</tr> +<tr bgcolor="#ffffc0"> +<td> +Optional + +</td> +<td> +boot_device_init + +</td> +</tr> +<tr bgcolor="#ffffc0"> +<td> +Optional + +</td> +<td> +car_mainboard_post_console_init + +</td> +</tr> +<tr bgcolor="#c0ffc0"> +<td> +Required + +</td> +<td> +car_mainboard_pre_console_init + +</td> +</tr> +<tr bgcolor="#c0ffc0"> +<td> +Required + +</td> +<td> +car_soc_post_console_init + +</td> +</tr> +<tr bgcolor="#c0ffc0"> +<td> +Required + +</td> +<td> +car_soc_pre_console_init + +</td> +</tr> +<tr bgcolor="#c0ffc0"> +<td> +Required + +</td> +<td> +car_stage_entry + +</td> +</tr> +<tr bgcolor="#c0ffc0"> +<td> +Required + +</td> +<td> +cbfs_master_header_locator + +</td> +</tr> +<tr bgcolor="#ffffc0"> +<td> +Optional + +</td> +<td> +cbmem_fail_resume + +</td> +</tr> +<tr bgcolor="#ffffc0"> +<td> +Optional + +</td> +<td> +clear_recovery_mode_switch + +</td> +</tr> +<tr bgcolor="#ffffc0"> +<td> +Optional + +</td> +<td> +cpu_smi_handler + +</td> +</tr> +<tr bgcolor="#c0ffc0"> +<td> +Required + +</td> +<td> +fill_power_state + +</td> +</tr> +<tr bgcolor="#ffffc0"> +<td> +Optional + +</td> +<td> +get_sw_write_protect_state + +</td> +</tr> +<tr bgcolor="#ffffc0"> +<td> +Optional + +</td> +<td> +get_top_of_ram + +</td> +</tr> +<tr bgcolor="#ffffc0"> +<td> +Optional + +</td> +<td> +gpio_acpi_path + +</td> +</tr> +<tr bgcolor="#c0ffc0"> +<td> +Required + +</td> +<td> +init_timer + +</td> +</tr> +<tr bgcolor="#ffffc0"> +<td> +Optional + +</td> +<td> +mainboard_add_dimm_info + +</td> +</tr> +<tr bgcolor="#ffffc0"> +<td> +Optional + +</td> +<td> +mainboard_check_ec_image + +</td> +</tr> +<tr bgcolor="#ffc0c0"> +<td> +Required + +</td> +<td> +mainboard_fill_spd_data + +</td> +</tr> +<tr bgcolor="#ffffc0"> +<td> +Optional + +</td> +<td> +mainboard_io_trap_handler + +</td> +</tr> +<tr bgcolor="#ffc0c0"> +<td> +Required + +</td> +<td> +mainboard_memory_init_params + +</td> +</tr> +<tr bgcolor="#ffffc0"> +<td> +Optional + +</td> +<td> +mainboard_post + +</td> +</tr> +<tr bgcolor="#c0ffc0"> +<td> +Required + +</td> +<td> +mainboard_romstage_entry + +</td> +</tr> +<tr bgcolor="#ffffc0"> +<td> +Optional + +</td> +<td> +mainboard_save_dimm_info + +</td> +</tr> +<tr bgcolor="#ffffc0"> +<td> +Optional + +</td> +<td> +mainboard_smi_apmc + +</td> +</tr> +<tr bgcolor="#ffffc0"> +<td> +Optional + +</td> +<td> +mainboard_smi_gpi + +</td> +</tr> +<tr bgcolor="#ffffc0"> +<td> +Optional + +</td> +<td> +mainboard_smi_sleep + +</td> +</tr> +<tr bgcolor="#ffffc0"> +<td> +Optional + +</td> +<td> +map_oprom_vendev + +</td> +</tr> +<tr bgcolor="#ffc0c0"> +<td> +Required + +</td> +<td> +migrate_power_state + +</td> +</tr> +<tr bgcolor="#ffc0c0"> +<td> +Required + +</td> +<td> +mrc_cache_get_current_with_version + +</td> +</tr> +<tr bgcolor="#ffc0c0"> +<td> +Required + +</td> +<td> +mrc_cache_stash_data_with_version + +</td> +</tr> +<tr bgcolor="#ffffc0"> +<td> +Optional + +</td> +<td> +platform_prog_run + +</td> +</tr> +<tr bgcolor="#ffffc0"> +<td> +Optional + +</td> +<td> +platform_segment_loaded + +</td> +</tr> +<tr bgcolor="#c0ffc0"> +<td> +Required + +</td> +<td> +print_fsp_info + +</td> +</tr> +<tr bgcolor="#c0ffc0"> +<td> +Required + +</td> +<td> +raminit + +</td> +</tr> +<tr bgcolor="#c0ffc0"> +<td> +Required + +</td> +<td> +ramstage_cache_invalid + +</td> +</tr> +<tr bgcolor="#ffc0c0"> +<td> +Required + +</td> +<td> +report_memory_config + +</td> +</tr> +<tr bgcolor="#c0ffc0"> +<td> +Required + +</td> +<td> +romstage_common + +</td> +</tr> +<tr bgcolor="#ffffc0"> +<td> +Optional + +</td> +<td> +save_chromeos_gpios + +</td> +</tr> +<tr bgcolor="#ffc0c0"> +<td> +Required + +</td> +<td> +set_max_freq + +</td> +</tr> +<tr bgcolor="#c0ffc0"> +<td> +Required + +</td> +<td> +setup_stack_and_mtrrs + +</td> +</tr> +<tr bgcolor="#ffc0c0"> +<td> +Required + +</td> +<td> +smm_region + +</td> +</tr> +<tr bgcolor="#ffc0c0"> +<td> +Required + +</td> +<td> +smm_region_size + +</td> +</tr> +<tr bgcolor="#c0ffc0"> +<td> +Required + +</td> +<td> +soc_after_ram_init + +</td> +</tr> +<tr bgcolor="#ffffc0"> +<td> +Optional + +</td> +<td> +soc_display_memory_init_params + +</td> +</tr> +<tr bgcolor="#c0ffc0"> +<td> +Required + +</td> +<td> +soc_display_mtrrs + +</td> +</tr> +<tr bgcolor="#c0ffc0"> +<td> +Required + +</td> +<td> +soc_get_variable_mtrr_count + +</td> +</tr> +<tr bgcolor="#c0ffc0"> +<td> +Required + +</td> +<td> +soc_memory_init_params + +</td> +</tr> +<tr bgcolor="#ffffc0"> +<td> +Optional + +</td> +<td> +soc_pre_ram_init + +</td> +</tr> +<tr bgcolor="#ffffc0"> +<td> +Optional + +</td> +<td> +southbridge_smi_handler + +</td> +</tr> +<tr bgcolor="#ffffc0"> +<td> +Optional + +</td> +<td> +stage_cache_add + +</td> +</tr> +<tr bgcolor="#ffffc0"> +<td> +Optional + +</td> +<td> +stage_cache_load_stage + +</td> +</tr> +<tr bgcolor="#ffffc0"> +<td> +Optional + +</td> +<td> +timestamp_get + +</td> +</tr> +<tr bgcolor="#c0ffc0"> +<td> +Required + +</td> +<td> +tsc_freq_mhz + +</td> +</tr> +<tr bgcolor="#ffffc0"> +<td> +Optional + +</td> +<td> +vb2ex_hwcrypto_digest_extend + +</td> +</tr> +<tr bgcolor="#ffffc0"> +<td> +Optional + +</td> +<td> +vb2ex_hwcrypto_digest_finalize + +</td> +</tr> +<tr bgcolor="#ffffc0"> +<td> +Optional + +</td> +<td> +vb2ex_hwcrypto_digest_init + +</td> +</tr> +<tr bgcolor="#ffffc0"> +<td> +Optional + +</td> +<td> +vboot_platform_prepare_reboot + +</td> +</tr> +<tr bgcolor="#ffffc0"> +<td> +Optional + +</td> +<td> +verstage_mainboard_init + +</td> +</tr> +</table> +</td> +<td width="5"> + + +</td> +<td> +<table border="1"> +<tr> +<th colspan="2"> +ramstage: 55% Done + +</th> +</tr> +<tr> +<th> +Type + +</th> +<th> +Routine + +</td> +</tr> +<tr bgcolor="#ffc0c0"> +<td> +Required + +</td> +<td> +acpi_create_serialio_ssdt + +</td> +</tr> +<tr bgcolor="#ffffc0"> +<td> +Optional + +</td> +<td> +arch_segment_loaded + +</td> +</tr> +<tr bgcolor="#ffffc0"> +<td> +Optional + +</td> +<td> +backup_top_of_ram + +</td> +</tr> +<tr bgcolor="#ffffc0"> +<td> +Optional + +</td> +<td> +boot_device_init + +</td> +</tr> +<tr bgcolor="#c0ffc0"> +<td> +Required + +</td> +<td> +cbfs_master_header_locator + +</td> +</tr> +<tr bgcolor="#ffffc0"> +<td> +Optional + +</td> +<td> +cbmem_fail_resume + +</td> +</tr> +<tr bgcolor="#ffffc0"> +<td> +Optional + +</td> +<td> +clear_recovery_mode_switch + +</td> +</tr> +<tr bgcolor="#ffffc0"> +<td> +Optional + +</td> +<td> +cpu_smi_handler + +</td> +</tr> +<tr bgcolor="#ffffc0"> +<td> +Optional + +</td> +<td> +fw_cfg_acpi_tables + +</td> +</tr> +<tr bgcolor="#ffffc0"> +<td> +Optional + +</td> +<td> +get_sw_write_protect_state + +</td> +</tr> +<tr bgcolor="#ffffc0"> +<td> +Optional + +</td> +<td> +get_top_of_ram + +</td> +</tr> +<tr bgcolor="#ffffc0"> +<td> +Optional + +</td> +<td> +gpio_acpi_path + +</td> +</tr> +<tr bgcolor="#c0ffc0"> +<td> +Required + +</td> +<td> +init_timer + +</td> +</tr> +<tr bgcolor="#ffffc0"> +<td> +Optional + +</td> +<td> +lb_board + +</td> +</tr> +<tr bgcolor="#ffffc0"> +<td> +Optional + +</td> +<td> +lb_framebuffer + +</td> +</tr> +<tr bgcolor="#ffffc0"> +<td> +Optional + +</td> +<td> +mainboard_add_dimm_info + +</td> +</tr> +<tr bgcolor="#ffffc0"> +<td> +Optional + +</td> +<td> +mainboard_io_trap_handler + +</td> +</tr> +<tr bgcolor="#ffffc0"> +<td> +Optional + +</td> +<td> +mainboard_post + +</td> +</tr> +<tr bgcolor="#ffffc0"> +<td> +Optional + +</td> +<td> +mainboard_silicon_init_params + +</td> +</tr> +<tr bgcolor="#ffffc0"> +<td> +Optional + +</td> +<td> +mainboard_smi_apmc + +</td> +</tr> +<tr bgcolor="#ffffc0"> +<td> +Optional + +</td> +<td> +mainboard_smi_gpi + +</td> +</tr> +<tr bgcolor="#ffffc0"> +<td> +Optional + +</td> +<td> +mainboard_smi_sleep + +</td> +</tr> +<tr bgcolor="#ffffc0"> +<td> +Optional + +</td> +<td> +mainboard_suspend_resume + +</td> +</tr> +<tr bgcolor="#ffffc0"> +<td> +Optional + +</td> +<td> +map_oprom_vendev + +</td> +</tr> +<tr bgcolor="#ffffc0"> +<td> +Optional + +</td> +<td> +mirror_payload + +</td> +</tr> +<tr bgcolor="#ffffc0"> +<td> +Optional + +</td> +<td> +northbridge_smi_handler + +</td> +</tr> +<tr bgcolor="#ffffc0"> +<td> +Optional + +</td> +<td> +nvm_mmio_to_flash_offset + +</td> +</tr> +<tr bgcolor="#ffffc0"> +<td> +Optional + +</td> +<td> +platform_prog_run + +</td> +</tr> +<tr bgcolor="#ffffc0"> +<td> +Optional + +</td> +<td> +platform_segment_loaded + +</td> +</tr> +<tr bgcolor="#ffffc0"> +<td> +Optional + +</td> +<td> +save_chromeos_gpios + +</td> +</tr> +<tr bgcolor="#ffffc0"> +<td> +Optional + +</td> +<td> +smbios_mainboard_bios_version + +</td> +</tr> +<tr bgcolor="#ffffc0"> +<td> +Optional + +</td> +<td> +smbios_mainboard_manufacturer + +</td> +</tr> +<tr bgcolor="#ffffc0"> +<td> +Optional + +</td> +<td> +smbios_mainboard_product_name + +</td> +</tr> +<tr bgcolor="#ffffc0"> +<td> +Optional + +</td> +<td> +smbios_mainboard_serial_number + +</td> +</tr> +<tr bgcolor="#ffffc0"> +<td> +Optional + +</td> +<td> +smbios_mainboard_set_uuid + +</td> +</tr> +<tr bgcolor="#c0ffc0"> +<td> +Required + +</td> +<td> +smbios_mainboard_version + +</td> +</tr> +<tr bgcolor="#ffffc0"> +<td> +Optional + +</td> +<td> +smm_disable_busmaster + +</td> +</tr> +<tr bgcolor="#ffffc0"> +<td> +Optional + +</td> +<td> +soc_after_silicon_init + +</td> +</tr> +<tr bgcolor="#ffffc0"> +<td> +Optional + +</td> +<td> +soc_display_silicon_init_params + +</td> +</tr> +<tr bgcolor="#ffc0c0"> +<td> +Required + +</td> +<td> +soc_fill_acpi_wake + +</td> +</tr> +<tr bgcolor="#c0ffc0"> +<td> +Required + +</td> +<td> +soc_silicon_init_params + +</td> +</tr> +<tr bgcolor="#ffffc0"> +<td> +Optional + +</td> +<td> +soc_skip_ucode_update + +</td> +</tr> +<tr bgcolor="#ffffc0"> +<td> +Optional + +</td> +<td> +southbridge_smi_handler + +</td> +</tr> +<tr bgcolor="#ffffc0"> +<td> +Optional + +</td> +<td> +stage_cache_add + +</td> +</tr> +<tr bgcolor="#ffffc0"> +<td> +Optional + +</td> +<td> +stage_cache_load_stage + +</td> +</tr> +<tr bgcolor="#ffc0c0"> +<td> +Required + +</td> +<td> +timestamp_get + +</td> +</tr> +<tr bgcolor="#ffc0c0"> +<td> +Required + +</td> +<td> +timestamp_tick_freq_mhz + +</td> +</tr> +<tr bgcolor="#c0ffc0"> +<td> +Required + +</td> +<td> +tsc_freq_mhz + +</td> +</tr> +<tr bgcolor="#ffffc0"> +<td> +Optional + +</td> +<td> +vb2ex_hwcrypto_digest_extend + +</td> +</tr> +<tr bgcolor="#ffffc0"> +<td> +Optional + +</td> +<td> +vb2ex_hwcrypto_digest_finalize + +</td> +</tr> +<tr bgcolor="#ffffc0"> +<td> +Optional + +</td> +<td> +vb2ex_hwcrypto_digest_init + +</td> +</tr> +<tr bgcolor="#ffffc0"> +<td> +Optional + +</td> +<td> +wifi_regulatory_domain + +</td> +</tr> +<tr bgcolor="#ffffc0"> +<td> +Optional + +</td> +<td> +write_smp_table + +</td> +</tr> +</table> +</td> +<td width="5"> + + +</td> +</tr> +</table> diff --git a/Documentation/content/docs/vendor/intel/development.md b/Documentation/content/docs/vendor/intel/development.md new file mode 100644 index 0000000..61af5b6 --- /dev/null +++ b/Documentation/content/docs/vendor/intel/development.md @@ -0,0 +1,129 @@ +--- +date: 2016-07-01T19:25:34.000Z +title: Development +name: Development +weight: 30 +menu: + main: + parent: Intel Documentation +prev: fsp1_1 +--- + +## Intel® x86 coreboot/FSP Development Process + +The x86 development process for coreboot is broken into the following components: + +- coreboot [SoC](SoC/soc.html) development +- coreboot [mainboard](Board/board.html) development +- [FSP 1.1](fsp1_1.md) integration + +The development process has two main phases: + +1. Minimal coreboot; This phase is single threaded +2. Adding coreboot features + +## Minimal coreboot + +The combined steps below describe how to bring up a minimal coreboot for a system-on-a-chip (SoC) and a development board: + +-------------------------------------------------------------------------------- + +## The initial coreboot steps are single threaded! The initial minimal FSP development is also single threaded. Progress can speed up by adding more developers after the minimal coreboot/FSP implementation reaches the payload. + +1. Get the necessary tools: + + - Linux: Use your package manager to install m4 bison flex and the libcurses development package. + + - Ubuntu or other Linux distribution that use apt, run: + + ``` + sudo apt-get install m4 bison flex libncurses5-dev + ``` + +2. Build the cross tools for i386: + + - Linux: + + ``` + make crossgcc-i386 + ``` + + To use multiple processors for the toolchain build (which takes a long time), use: + + ``` + make crossgcc-i386 CPUS=N + ``` + + where N is the number of cores to use for the build. + +3. Get something to build: + + 1. [FSP 1.1](fsp1_1.html#RequiredFiles) required files + 2. [SoC](SoC/soc.html#RequiredFiles) required files + 3. [Board](Board/board.html#RequiredFiles) required files + +4. Get result to start [booting](SoC/soc.html#Descriptor) + +5. [Early Debug](SoC/soc.html#EarlyDebug) +6. Implement and debug the [bootblock](SoC/soc.html#Bootblock) code +7. Implement and debug the call to [TempRamInit](SoC/soc.html#TempRamInit) +8. Enable the serial port + + 1. Power on, enable and configure GPIOs for the [debug serial UART](Board/board.html#SerialOutput) + 2. Add the [serial outupt](SoC/soc.html#SerialOutput) support to romstage + +9. Enable [coreboot/FSP](fsp1_1.html#corebootFspDebugging) debugging + +10. Determine the [Previous Sleep State](SoC/soc.html#PreviousSleepState) +11. Enable DRAM: + + 1. Implement the SoC [MemoryInit](SoC/soc.html#MemoryInit) Support + 2. Implement the board support to read the [Memory Timing Data](Board/board.html#SpdData) + +12. Disable the [Shadow ROM](SoC/soc.html#DisableShadowRom) + +13. Enable CONFIG_DISPLAY_MTRRS to verify the MTRR configuration +14. Implement the .init routine for the [chip operations](SoC/soc.html#ChipOperations) structure which calls FSP SiliconInit +15. Start ramstage's [device tree processing](SoC/soc.html#DeviceTree) to display the PCI vendor and device IDs +16. Disable the [PCI devices](Board/board.html#DisablePciDevices) +17. Implement the [memory map](SoC/soc.html#MemoryMap) +18. coreboot should now attempt to load the payload + +## Add coreboot Features + +Most of the coreboot development gets done in this phase. Implementation tasks in this phase are easily done in parallel. + +- Payload and OS Features: + + - [ACPI Tables](SoC/soc.html#AcpiTables) + - [Legacy hardware](SoC/soc.html#LegacyHardware) support + +-------------------------------------------------------------------------------- + +| Features ======== +| -------------------------------------- +SoC | Where | Testing +8254 Programmable Interval Timer | [Legacy hardware](SoC/soc.html#LegacyHardware) support | [CorebootPayloadPkg](SoC/quark.html#CorebootPayloadPkg) gets to shell prompt +8259 Programmable Interrupt Controller | [Legacy hardware](SoC/soc.html#LegacyHardware) support | [CorebootPayloadPkg](SoC/quark.html#CorebootPayloadPkg) gets to shell prompt +Cache-as-RAM | [Find](SoC/soc.html#TempRamInit) FSP binary: [cache_as_ram.inc](https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel... Enable: FSP 1.1 [TempRamInit](SoC/soc.html#TempRamInit) called from [cache_as_ram.inc](https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel... Disable: FSP 1.1 TempRamExit called from [after_raminit.S](https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel... | FindFSP: POST code 0x90 ([POST_FSP_TEMP_RAM_INIT](http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/consol...)) is displayed\ Enable: POST code [0x2A](https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel...) is displayed\ Disable: CONFIG_DISPLAY_MTRRS=y, MTRRs displayed after call to TempRamExit +Memory Map | Implement a device driver for the [north cluster](SoC/soc.html#MemoryMap) | coreboot displays the memory map correctly during the BS_WRITE_TABLES state +MTRRs | Set values: src/drivers/intel/fsp1_1/stack.c/[setup_stack_and_mtrrs](https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel... Load values: src/drivers/intel/fsp1_1/[after_raminit.S](https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel...) | Set: Post code 0x91 ([POST_FSP_TEMP_RAM_EXIT](https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/conso...)) is displayed by [after_raminit.S](https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel... Load: Post code 0x3C is displayed by [after_raminit.S](https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel... and CONFIG_DISPLAY_MTRRS=y displays the correct memory regions +PCI Device Support | Implement a PCI [device driver](SoC/soc.html#DeviceDrivers) | The device is detected by coreboot and usable by the payload +Ramstage state machine | Implement the chip and domain operations to start the [device tree](SoC/soc.html#DeviceTree) processing | During the BS_DEV_ENUMERATE state, ramstage now display the device IDs for the PCI devices on the bus. +ROM Shadow\ 0x000E0000 - 0x000FFFFF | Disable: src/soc/<Vendor>/<Chip Family>/romstage/romstage.c/[soc_after_ram_init routine](SoC/soc.html#DisableShadowRom) | Operates as RAM: Writes followed by a read to the 0x000E0000 - 0x000FFFFF region returns the value written +Board | Where | Testing +Device Tree | [List](SoC/soc.html#DeviceTree) PCI vendor and device IDs by starting the device tree processing\ [Disable](Board/board.html#DisablePciDevices) PCI devices\ Enable: Implement a PCI [device driver](SoC/soc.html#DeviceDrivers) | List: BS_DEV_ENUMERATE state displays PCI vendor and device IDs\ Disable: BS_DEV_ENUMERATE state shows the devices as disabled\ Enable: BS_DEV_ENUMERATE state shows the device as on and the device works for the payload +DRAM | Load SPD data: src/soc/mainboard/<Vendor>/<Board>/spd/[spd.c](Board/board.html#SpdData)\ UPD Setup: - src/soc<Vendor>//<Chip Family>/romstage/[romstage.c](SoC/soc.html#MemoryInit) - src/mainboard/<Vendor>/<Board>/[romstage.c](Board/board.html#SpdData) FSP 1.1 MemoryInit called from src/drivers/intel/fsp1_1/[raminit.c](https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel...) | Select the following Kconfig values - DISPLAY_HOBS - DISPLAY_UPD_DATA Testing successful if: - MemoryInit UPD values are correct - MemoryInit returns 0 (success) and - The the message "ERROR - coreboot's requirements not met by FSP binary!" is not displayed +Serial Port | SoC [Support](SoC/soc.html#SerialOutput)\ Enable: src/soc/mainboard/<Board>/com_init.c/[car_mainboard_pre_console_init](Board/board.html#SerialOutput) | Debug serial output works +Payload | Where | Testing +ACPI Tables | SoC [Support](SoC/soc.html#AcpiTables)\ | Verified by payload or OS +FSP | Where | Testing +TempRamInit | FSP [TempRamInit](SoC/soc.html#TempRamInit) | FSP binary found: POST code 0x90 ([POST_FSP_TEMP_RAM_INIT](http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/consol...)) is displayed\ TempRamInit successful: POST code [0x2A](https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel...) is displayed\ +MemoryInit | [SoC](SoC/soc.html#MemoryInit) support\ [Board](Board/board.html#SpdData) support\ | Select the following Kconfig values - DISPLAY_HOBS - DISPLAY_UPD_DATA Testing successful if: - MemoryInit UPD values are correct - MemoryInit returns 0 (success) and - The the message "ERROR - coreboot's requirements not met by FSP binary!" is not displayed +TempRamExit | src/drivers/intel/fsp1_1/[after_raminit.S](http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/...) | Post code 0x91 ([POST_FSP_TEMP_RAM_EXIT](https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/conso...)) is displayed before calling TempRamExit by [after_raminit.S](https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel...), CONFIG_DISPLAY_MTRRS=y displays the correct memory regions and Post code 0x39 is displayed by [after_raminit.S](https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel... +SiliconInit | Implement the .init routine for the [chip operations](SoC/soc.html#ChipOperations) structure | During BS_DEV_INIT_CHIPS state, SiliconInit gets called and returns 0x00000000 +FspNotify | The code which calls FspNotify is located in src/drivers/intel/fsp1_1/[fsp_util.c](http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/...). The fsp_notify_boot_state_callback routine is called three times as specified by the BOOT_STATE_INIT_ENTRY macros below the routine. | The FspNotify routines are called during: - BS_DEV_RESOURCES - on exit - BS_PAYLOAD_LOAD - on exit - BS_OS_RESUME - on entry (S3 resume) + +-------------------------------------------------------------------------------- + +Modified: 4 March 2016 diff --git a/Documentation/content/docs/vendor/intel/fsp1_1.md b/Documentation/content/docs/vendor/intel/fsp1_1.md new file mode 100644 index 0000000..48d58d4 --- /dev/null +++ b/Documentation/content/docs/vendor/intel/fsp1_1.md @@ -0,0 +1,66 @@ +--- +date: 2016-07-01T19:25:34.000Z +title: FSP 1.1 +name: FSP 1.1 +menu: + main: + parent: Intel Documentation +next: development +prev: index +weight: 20 +--- + +## x86 FSP 1.1 Integration + +Firmware Support Package (FSP) integration requires System-on-a-Chip (SoC) and board support. The combined steps are listed [here](development.html). The development steps for FSP are listed below: + +1. [Required Files](#RequiredFiles) +2. Add the [FSP Binary File](#FspBinary) to the coreboot File System +3. Enable [coreboot/FSP Debugging](#corebootFspDebugging) + +FSP Documentation: + +- Intel® Firmware Support Package External Architecture Specification [V1.1](http://www.intel.com/content/dam/www/public/us/en/documents/technical-specif...) + +-------------------------------------------------------------------------------- + +## [Required Files]() + +## [coreboot Required Files]() + +1. Create the following directories if they do not already exist: + + - src/vendorcode/intel/fsp/fsp1_1/<Chip Family> + - 3rdparty/blobs/mainboard/<Board Vendor>/<Board Name> + +2. The following files may need to be copied from the FSP build or release into the directories above if they are not present or are out of date: + + - FspUpdVpd.h: src/vendorcode/intel/fsp/fsp1_1/<Chip Family>/FspUpdVpd.h + - FSP.bin: 3rdparty/blobs/mainboard/<Board Vendor>/<Board Name>/fsp.bin + +-------------------------------------------------------------------------------- + +## [Add the FSP Binary File to coreboot File System]() + +Add the FSP binary to the coreboot flash image using the following command: + +``` +util/cbfstool/cbfstool build/coreboot.rom add -t fsp -n fsp.bin -b <base address> -f fsp.bin +``` + +This command relocates the FSP binary to the 4K byte aligned location in CBFS so that the FSP code for TempRamInit may be executed in place. + +-------------------------------------------------------------------------------- + +## [Enable coreboot/FSP Debugging]() + +Set the following Kconfig values: + +- CONFIG_DISPLAY_FSP_ENTRY_POINTS - Display the FSP entry points in romstage +- CONFIG_DISPLAY_HOBS - Display and verify the hand-off-blocks (HOBs) returned by MemoryInit +- CONFIG_DISPLAY_VBT - Display Video BIOS Table (VBT) used for GOP +- CONFIG_DISPLAY_UPD_DATA - Display the user specified product data passed to MemoryInit and SiliconInit + +-------------------------------------------------------------------------------- + +Modified: 17 May 2016 diff --git a/Documentation/content/docs/vendor/intel/index.md b/Documentation/content/docs/vendor/intel/index.md new file mode 100644 index 0000000..5df16e1 --- /dev/null +++ b/Documentation/content/docs/vendor/intel/index.md @@ -0,0 +1,9 @@ +--- +date: 2016-07-01T19:25:34.000Z +title: Intel Documentation +name: Intel Documentation +weight: 10 +menu: + main: +next: fsp1_1 +--- diff --git a/Documentation/content/docs/vendor/intel/soc/quark.md b/Documentation/content/docs/vendor/intel/soc/quark.md new file mode 100644 index 0000000..16beb0c --- /dev/null +++ b/Documentation/content/docs/vendor/intel/soc/quark.md @@ -0,0 +1,152 @@ +--- +date: 2016-07-01T19:25:34.000Z +title: Quark +name: Quark +weight: 50 +menu: + main: + parent: Intel Documentation +--- + +## Intel® Quark™ SoC + ++--------------------------------------+--------------------------------------+ +| [ board: | +| ed/16x9/edc-quark-block-diagram-16x9 | - [Overall](../development.html) | +| .png)](http://www.intel.com/content/ | development | +| dam/www/public/us/en/images/embedded | - [SoC](soc.html) support | +| /16x9/edc-quark-block-diagram-16x9.p | - [FSP 1.1](../fsp1_1.html) | +| ng) | integration | +| | - [Board](../Board/board.html) | +| | support | +| | - [Quark™ FSP](#QuarkFsp) | +| | - [CorebootPayloadPkg](#CorebootPa | +| | yloadPkg) | ++--------------------------------------+--------------------------------------+ + +## Quark™ Documentation + +- [Block Diagram](http://www.intel.com/content/dam/www/public/us/en/images/embedded/16x9/edc-q...) +- [Specifications](http://www.intel.com/content/www/us/en/embedded/products/quark/specification...): + + - [X1000](http://ark.intel.com/products/79084/Intel-Quark-SoC-X1000-16K-Cache-400-MHz) - [Documentation](http://www.intel.com/content/www/us/en/search.html?keyword=X1000): + + - [Datasheet](http://www.intel.com/content/dam/www/public/us/en/documents/datasheets/quark...) + - [Developer's Manual](http://www.intel.com/content/dam/support/us/en/documents/processors/quark/sb...) + - [Product Brief](http://www.intel.com/content/dam/www/public/us/en/documents/product-briefs/i...) + +- [More documentation](../index.html#Documentation) + +-------------------------------------------------------------------------------- + +## [Quark™ EDK2 CorebootPayloadPkg]() + +Build Instructions: + +1. Set up [build environment](#BuildEnvironment) +2. Linux (assumes GCC48): + + ``` + build -p CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc -a IA32 \ + -t GCC48 -b DEBUG -DDEBUG_PROPERTY_MASK=0x27 \ + -DDEBUG_PRINT_ERROR_LEVEL=0x80000042 -DSHELL_TYPE=BUILD_SHELL \ + -DMAX_LOGICAL_PROCESSORS=1 + ls Build/CorebootPayloadPkgIA32/DEBUG_GCC48/FV/UEFIPAYLOAD.fd + ``` + +3. Windows (assumes Visual Studio 2015): + + ``` + build -p CorebootPayloadPkg\CorebootPayloadPkgIa32.dsc -a IA32 -t VS2015x86 -b DEBUG -DDEBUG_PROPERTY_MASK=0x27 -DDEBUG_PRINT_ERROR_LEVEL=0x80000042 -DSHELL_TYPE=BUILD_SHELL -DMAX_LOGICAL_PROCESSORS=1 + dir Build\CorebootPayloadPkgIA32\DEBUG_VS2015x86\FV\UEFIPAYLOAD.fd + ``` + +4. In the .config for coreboot, set the following Kconfig values: + + - CONFIG_PAYLOAD_ELF=y + - CONFIG_PAYLOAD_FILE="path to UEFIPAYLOAD.fd" + +5. Build coreboot + +6. Copy the image build/coreboot.rom into flash + +-------------------------------------------------------------------------------- + +## [Quark™ EDK2 Build Environment]() + +Use the following steps to setup a build environment: + +1. Get the EDK2 sources: + + 1. EDK2: git clone https://github.com/tianocore/edk2.git + 2. EDK2-non-osi: git clone https://github.com/tianocore/edk2-non-osi.git + 3. Win32 BaseTools: git clone https://github.com/tianocore/edk2-BaseTools-win32.git + +2. Set up a build window: + + - Linux: + + ``` + export WORKSPACE=$PWD + export PACKAGES_PATH="$PWD/edk2:$PWD/edk2-non-osi" + cd edk2 + export WORKSPACE=$PWD + . edksetup.sh + ``` + + - Windows: + + ``` + set WORKSPACE=%CD% + set PACKAGES_PATH=%WORKSPACE%\edk2;%WORKSPACE%\edk2-non-osi + set EDK_TOOLS_BIN=%WORKSPACE%\edk2-BaseTools-win32 + cd edk2 + edksetup.bat + ``` + +-------------------------------------------------------------------------------- + +## [Quark™ FSP]() + +Getting the Quark FSP source: + +1. Set up an EDK-II [Build Environment](#BuildEnvironment) +2. cd edk2 +3. mkdir QuarkFspPkg +4. cd QuarkFspPkg +5. Use git to clone [QuarkFspPkg](https://review.gerrithub.io/#/admin/projects/LeeLeahy/quarkfsp) into the QuarkFpsPkg directory (.) + +Building QuarkFspPkg: + +- Linux: QuarkFspPkg/BuildFsp.sh -d32 +- Windows: QuarkFspPkg/BuildFsp.bat -d32 + +-------------------------------------------------------------------------------- + +## Quark™ EDK2 BIOS + +Build Instructions: + +1. Set up [build environment](#BuildEnvironment) +2. Build the image: + + - Linux: + + ``` + build -p QuarkPlatformPkg/Quark.dsc -a IA32 -t GCC48 -b DEBUG -DDEBUG_PROPERTY_MASK=0x27 -DDEBUG_PRINT_ERROR_LEVEL=0x80000042 + ls Build/Quark/DEBUG_GCC48/FV/Quark.fd + ``` + + - Windows: + + ``` + build -p QuarkPlatformPkg/Quark.dsc -a IA32 -t VS2012x86 -b DEBUG -DDEBUG_PROPERTY_MASK=0x27 -DDEBUG_PRINT_ERROR_LEVEL=0x80000042 + dir Build\Quark\DEBUG_VS2012x86\FV\Quark.fd + ``` + +Documentation: + +- [EDK II firmware for Intel® Quark™ SoC X1000 based platforms](https://github.com/tianocore/edk2/tree/master/QuarkPlatformPkg) +- Intel® Quark™ SoC X1000 [UEFI Firmware Writer's Guide](http://www.intel.com/content/dam/www/public/us/en/documents/guides/quark-x10...) diff --git a/Documentation/content/docs/vendor/intel/soc/soc.md b/Documentation/content/docs/vendor/intel/soc/soc.md new file mode 100644 index 0000000..fc2b309 --- /dev/null +++ b/Documentation/content/docs/vendor/intel/soc/soc.md @@ -0,0 +1,593 @@ +--- +date: 2016-07-01T19:25:34.000Z +title: SoC +name: SoC +weight: 40 +menu: + main: + parent: Intel Documentation +--- + +## x86 System on a Chip (SoC) Development + +SoC development is best done in parallel with development for a specific board. The combined steps are listed [here](../development.html). The development steps for the SoC are listed below: + +1. [FSP 1.1](../fsp1_1.html#RequiredFiles) required files +2. SoC [Required Files](#RequiredFiles) +3. [Start Booting](#Descriptor) +4. [Early Debug](#EarlyDebug) +5. [Bootblock](#Bootblock) +6. [TempRamInit](#TempRamInit) +7. [Romstage](#Romstage) + + 1. Enable [Serial Output"](#SerialOutput) + 2. Get the [Previous Sleep State](#PreviousSleepState) + 3. Add the [MemoryInit](#MemoryInit) Support + 4. Disable the [Shadow ROM](#DisableShadowRom) + +8. [Ramstage](#Ramstage) + + 1. [Start Device Tree Processing](#DeviceTree) + 2. Set up the [Memory Map"](#MemoryMap) + +9. [ACPI Tables](#AcpiTables) + +10. [Legacy Hardware](#LegacyHardware) + +-------------------------------------------------------------------------------- + +## [Required Files]() + +Create the directory as src/soc/<Vendor>/<Chip Family>. + +The following files are required to build a new SoC: + +- Include files + + - include/soc/pei_data.h + - include/soc/pm.h + +- Kconfig - Defines the Kconfig value for the SoC and selects the tool chains for the various stages: + + - select ARCH_BOOTBLOCK_<Tool Chain> + - select ARCH_RAMSTAGE_<Tool Chain> + - select ARCH_ROMSTAGE_<Tool Chain> + - select ARCH_VERSTAGE_<Tool Chain> + +- Makefile.inc - Specify the include paths +- memmap.c - Top of usable RAM + +-------------------------------------------------------------------------------- + +## [Start Booting]() + +Some SoC parts require additional firmware components in the flash. This section describes how to add those pieces. + +### Intel Firmware Descriptor + +The Intel Firmware Descriptor (IFD) is located at the base of the flash part. The following command overwrites the base of the flash image with the Intel Firmware Descriptor: + +``` +dd if=descriptor.bin of=build/coreboot.rom conv=notrunc >/dev/null 2>&1 +``` + +### [Management Engine Binary]() + +Some SoC parts contain and require that the Management Engine (ME) be running before it is possible to bring the x86 processor out of reset. A binary file containing the management engine code must be added to the firmware using the ifdtool. The following commands add this binary blob: + +``` +util/ifdtool/ifdtool -i ME:me.bin build/coreboot.rom +mv build/coreboot.rom.new build/coreboot.rom +``` + +### [Early Debug]() + +Early debugging between the reset vector and the time the serial port is enabled is most easily done by writing values to port 0x80. + +### Success + +When the reset vector is successfully invoked, port 0x80 will output the following value: + +- 0x01: [POST_RESET_VECTOR_CORRECT](http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/consol...) - Bootblock successfully executed the [reset vector](http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/16bit/...) and entered the 16-bit code at [_start](http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/16bit/...) + +-------------------------------------------------------------------------------- + +## [Bootblock]() + +Implement the bootblock using the following steps: + +1. Create the directory as src/soc/<Vendor>/<Chip Family>/bootblock +2. Add the timestamp.inc file which initializes the floating point registers and saves the initial timestamp. +3. Add the bootblock.c file which: + + 1. Enables memory-mapped PCI config access + 2. Updates the microcode by calling intel_update_microcode_from_cbfs + 3. Enable ROM caching + +4. Edit the src/soc/<Vendor>/<Chip Family>/Kconfig file + + 1. Add the BOOTBLOCK_CPU_INIT value to point to the bootblock.c file + 2. Add the CHIPSET_BOOTBLOCK_INCLUDE value to point to the timestamp.inc file + +5. Edit the src/soc/<Vendor>/<Chip Family>/Makefile.inc file + + 1. Add the bootblock subdirectory + +6. Edit the src/soc/<Vendor>/<Chip Family>/memmap.c file + + 1. Add the fsp/memmap.h include file + 2. Add the mmap_region_granularity routine + +7. Add the necessary .h files to define the necessary values and structures + +8. When successful port 0x80 will output the following values: + + 1. 0x01: [POST_RESET_VECTOR_CORRECT](http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/consol...) - Bootblock successfully executed the [reset vector](http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/16bit/...) and entered the 16-bit code at [_start](http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/16bit/...) + 2. 0x10: [POST_ENTER_PROTECTED_MODE](http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/consol...) - Bootblock executing in [32-bit mode](http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/32bit/...) + 3. 0x10 - Verstage/romstage reached 32-bit mode + +**Build Note:** The following files are included into the default bootblock image: + +- [src/arch/x86/bootblock_romcc.S](http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/bootb...) added by [src/arch/x86/Makefile.inc](http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/Makef...) and includes the following files: + + - [src/arch/x86/prologue.inc](http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/prolo...) + - [src/cpu/x86/16bit/reset16.inc](http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/16bit/...) + - [src/cpu/x86/16bit/entry16.inc](http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/16bit/...) + - [src/cpu/x86/32bit/entry32.inc](http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/32bit/...) + - The code in [src/arch/x86/bootblock_romcc.S](http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/bootb...) includes src/soc/<Vendor>/<Chip Family>/bootblock/timestamp.inc using the CONFIG_CHIPSET_BOOTBLOCK_INCLUDE value set above + - [src/cpu/x86/sse_enable.inc](http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/sse_en...) + - The code in [src/arch/x86/Makefile.inc](http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/Makef...) invokes the ROMCC tool to convert the following "C" code into assembler as bootblock.inc: + + - [src/arch/x86/include/arch/bootblock_romcc.h](http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/inclu...) + - [src/cpu/x86/lapic/boot_cpu.c](http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/lapic/...) + - The CONFIG_BOOTBLOCK_CPU_INIT value set above typically points to the code in src/soc/<Vendor>/<Chip Family>/bootblock/bootblock.c + +- [src/arch/x86/id.S](http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/id.S) added by [src/arch/x86/Makefile.inc](http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/Makef...) +- [src/cpu/intel/fit/fit.S](http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/intel/fit/...) added by [src/cpu/intel/fit/Makefile.inc](http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/intel/fit/...) +- [src/arch/x86/walkcbfs.S](http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/walkc...) added by [src/arch/x86/Makefile.inc](http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/Makef...) + +-------------------------------------------------------------------------------- + +## [TempRamInit]() + +Enable the call to TempRamInit in two stages: + +1. Finding the FSP binary in the read-only CBFS region +2. Call TempRamInit + +### Find FSP Binary + +Use the following steps to locate the FSP binary: + +1. Edit the src/soc/<Vendor>/<Chip Family>/Kconfig file + + 1. Add "select USE_GENERIC_FSP_CAR_INC" to enable the use of [src/drivers/intel/fsp1_1/cache_as_ram.inc](http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/...) + 2. Add "select SOC_INTEL_COMMON" to enable the use of the files from src/soc/intel/common specifically building [util.c](http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/soc/intel/comm...) + +2. Debug the result until port 0x80 outputs + + 1. 0x90: [POST_FSP_TEMP_RAM_INIT](http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/consol...) - Just before calling [TempRamInit](http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/...) + 2. Alternating 0xba and 0x01 - The FSP image was not found + +3. Add the [FSP binary file](../fsp1_1.html#FspBinary) to the flash image + +4. Set the following Kconfig values: + + - CONFIG_FSP_LOC to the FSP base address specified in the previous step + - CONFIG_FSP_IMAGE_ID_STRING + +5. Debug the result until port 0x80 outputs + + 1. 0x90: [POST_FSP_TEMP_RAM_INIT](http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/consol...) - Just before calling [TempRamInit](http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/...) + 2. Alternating 0xbb and 0x02 - TempRamInit executed, no CPU microcode update found + +### Calling TempRamInit + +Use the following steps to debug the call to TempRamInit: + +1. Add the CPU microcode update file + + 1. Add the microcode file with the following command + + ``` + util/cbfstool/cbfstool build/coreboot.rom add -t microcode -n cpu_microcode_blob.bin -b <base address> -f cpu_microcode_blob.bin + ``` + + 2. Set the Kconfig values + + - CONFIG_CPU_MICROCODE_CBFS_LOC set to the value from the previous step + - CONFIG_CPU_MICROCODE_CBFS_LEN + +2. Debug the result until port 0x80 outputs + + 1. 0x90: [POST_FSP_TEMP_RAM_INIT](http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/consol...) - Just before calling [TempRamInit](http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/...) + 2. 0x2A - Just before calling [cache_as_ram_main](http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/...) which is the start of the verstage code which may be part of romstage + +-------------------------------------------------------------------------------- + +## [Romstage]() + +### [Serial Output]() + +The following steps add the serial output support for romstage: + +1. Create the romstage subdirectory +2. Add romstage/romstage.c + + 1. Program the necessary base addresses + 2. Disable the TCO + +3. Add romstage/Makefile.inc + + 1. Add romstage.c to romstage + +4. Add gpio configuration support if necessary + +5. Add the necessary .h files to support the build +6. Update Makefile.inc + + 1. Add the romstage subdirectory + 2. Add the gpio configuration support file to romstage + +7. Set the necessary Kconfig values to enable serial output: + + - CONFIG_DRIVERS_UART_<driver>=y + - CONFIG_CONSOLE_SERIAL=y + - CONFIG_UART_FOR_CONSOLE=<port> + - CONFIG_CONSOLE_SERIAL_115200=y + +### [Determine Previous Sleep State]() + +The following steps implement the code to get the previous sleep state: + +1. Implement the fill_power_state routine which determines the previous sleep state +2. Debug the result until port 0x80 outputs + + 1. 0x32: - Just after entering [romstage_common](http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/...) + 2. 0x33 - Just after calling [soc_pre_ram_init](http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/...) + 3. 0x34: - Just after entering [raminit](http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/...) + +### [MemoryInit Support]() + +The following steps implement the code to support the FSP MemoryInit call: + +1. Add the chip.h header file to define the UPD values which get passed to MemoryInit. Skip the values containing SPD addresses and DRAM configuration data which is determined by the board. + + **Build Note**: The src/mainboard/<Vendor>/<Board>/devicetree.cb file specifies the default values for these parameters. The build process creates the static.c module which contains the config data structure containing these values. + +2. Edit romstage/romstage.c + + 1. Implement the romstage/romstage.c/soc_memory_init_params routine to copy the values from the config structure into the UPD structure + 2. Implement the soc_display_memory_init_params routine to display the updated UPD parameters by calling fsp_display_upd_value + +### [Disable Shadow ROM]() + +A shadow of the SPI flash part is mapped from 0x000e0000 to 0x000fffff. This shadow needs to be disabled to allow RAM to properly respond to this address range. + +1. Edit romstage/romstage.c and add the soc_after_ram_init routine + +-------------------------------------------------------------------------------- + +## [Ramstage]() + +### [Start Device Tree Processing]() + +The src/mainboard/<Vendor>/<Board>/devicetree.cb file drives the execution during ramstage. This file is processed by the util/sconfig utility to generate build/mainboard/<Vendor>/<Board>/static.c. The various state routines in src/lib/[hardwaremain.c](http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/lib/hardwarema...) call dev_* routines which use the tables in static.c to locate operation tables associated with the various chips and devices. After location the operation tables, the state routines call one or more functions depending upon the state of the state machine. + +#### [Chip Operations]() + +Kick-starting the ramstage state machine requires creating the operation table for the chip listed in devicetree.cb: + +1. Edit src/soc/<SoC Vendor>/<SoC Family>/chip.c: + + 1. This chip's operation table has the name soc_<SoC Vendor>_<SoC Family>_ops which is derived from the chip path specified in the devicetree.cb file. + 2. Use the CHIP_NAME macro to specify the name for the chip + 3. For FSP 1.1, specify a .init routine which calls intel_silicon_init + +2. Edit src/soc/<SoC Vendor>/<SoC Family>/Makefile.inc and add chip.c to ramstage + +### Domain Operations + +coreboot uses the domain operation table to initiate operations on all of the devices in the domain. By default coreboot enables all PCI devices which it finds. Listing a device in devicetree.cb gives the board vendor control over the device state. Non-PCI devices may also be listed under PCI device such as the LPC bus or SMbus devices. + +1. Edit src/soc/<SoC Vendor>/<SoC Family>/chip.c: + + 1. The domain operation table is typically placed in src/soc/<SoC Vendor>/<SoC Family>/chip.c. The table typically looks like the following: + + ``` + static struct device_operations pci_domain_ops = { + .read_resources = pci_domain_read_resources, + .set_resources = pci_domain_set_resources, + .scan_bus = pci_domain_scan_bus, + .ops_pci_bus = pci_bus_default_ops, + }; + ``` + + 2. Create a .enable_dev entry in the chip operations table which points to a routine which sets the domain table for the device with the DEVICE_PATH_DOMAIN. + + ``` + if (dev->path.type == DEVICE_PATH_DOMAIN) { + dev->ops = &pci_domain_ops; + } + ``` + + 3. During the BS_DEV_ENUMERATE state, ramstage now display the device IDs for the PCI devices on the bus. + +2. Set CONFIG_DEBUG_BOOT_STATE=y in the .config file + +3. Debug the result until the PCI vendor and device IDs are displayed during the BS_DEV_ENUMERATE state. + +## [PCI Device Drivers]() + +PCI device drivers consist of a ".c" file which contains a "pci_driver" data structure at the end of the file with the attribute tag "__pci_driver". This attribute tag places an entry into a link time table listing the various coreboot device drivers. + +Specify the following fields in the table: + +1. .vendor - PCI vendor ID value of the device +2. .device - PCI device ID value of the device or\ .devices - Address of a zero terminated array of PCI device IDs +3. .ops - Operations table for the device. This is the address of a "static struct device_operations" data structure specifying the routines to execute during the different states and sub-states of ramstage's processing. +4. Turn on the device in mainboard/<Vendor>/<Board>/devicetree.cb +5. Debug until the device is on and properly configured in coreboot and usable by the payload + +### [Subsystem IDs]() + +PCI subsystem IDs are assigned during the BS_DEV_ENABLE state. The device driver may use the common mechanism to assign subsystem IDs by adding the ".ops_pci" to the pci_driver data structure. This field points to a "struct pci_operations" that specifies a routine to set the subsystem IDs for the device. The routine might look something like this: + +``` +static void pci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +{ + if (!vendor || !device) { + vendor = pci_read_config32(dev, PCI_VENDOR_ID); + device = vendor >> 16; + } + printk(BIOS_SPEW, + "PCI: %02x:%02x:%d subsystem vendor: 0x%04x, device: 0x%04x\n", + 0, PCI_SLOT(dev->path.pci.devfn), PCI_FUNC(dev->path.pci.devfn), + vendor & 0xffff, device); + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + ((device & 0xffff) << 16) | (vendor & 0xffff)); +} +``` + +## Set up the [Memory Map]() + +The memory map is built by the various PCI device drivers during the BS_DEV_RESOURCES state of ramstage. The northcluster driver will typically specify the DRAM resources while the other drivers will typically specify the IO resources. These resources are hung off the device_t data structure by src/device/device_util.c/[new_resource](http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/device/device_...). + +During the BS_WRITE_TABLES state, coreboot collects these resources and places them into a data structure identified by LB_MEM_TABLE. + +Edit the device driver file: + +1. Implement a read_resources routine which calls macros defined in src/include/device/[device.h](http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/device...) like: + + - ram_resource + - reserved_ram_resource + - bad_ram_resource + - uma_resource + - mmio_resource + +Testing: Verify that the resources are properly displayed by coreboot during the BS_WRITE_TABLES state. + +-------------------------------------------------------------------------------- + +# [ACPI Tables]() + +One of the payloads that needs ACPI tables is the EDK2 [CorebootPayloadPkg](quark.html#CorebootPayloadPkg). + +## FADT + +The EDK2 module CorebootModulePkg/Library/CbParseLib/[CbParseLib.c](https://github.com/tianocore/edk2/blob/master/CorebootModulePkg/Library/CbPa...) requires that the FADT contains the values in the table below. These values are placed into a HOB identified by [gUefiAcpiBoardInfoGuid](https://github.com/tianocore/edk2/blob/master/CorebootModulePkg/CorebootModu...) by routine CorebootModulePkg/CbSupportPei/CbSupportPei/[CbPeiEntryPoint](https://github.com/tianocore/edk2/blob/master/CorebootModulePkg/CbSupportPei...). + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +Coreboot Field | EDK2 Field | gUefiAcpiBoardInfoGuid | Use | [ACPI Spec.](http://www.uefi.org/sites/default/files/resources/ACPI_6.0.pdf) Section +---------------------- | ------------------- | ------------------------------------------------------------------------------------------------------------------- | ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | ------------------------------------------------------------------------------------ +gpe0_blk\ gpe0_blk_len | Gpe0Blk\ Gpe0BlkLen | [PmGpeEnBase](https://github.com/tianocore/edk2/blob/master/CorebootModulePkg/Library/CbPa...) | [Shutdown](https://github.com/tianocore/edk2/blob/master/CorebootPayloadPkg/Library/Res...) | 4.8.4.1 +pm1a_cnt_blk | Pm1aCntBlk | PmCtrlRegBase | [Shutdown](https://github.com/tianocore/edk2/blob/master/CorebootPayloadPkg/Library/Res... + + + +[Suspend](https://github.com/tianocore/edk2/blob/master/CorebootPayloadPkg/Library/Res...) | 4.8.3.2.1 +pm1a_evt_blk | Pm1aEvtBlk | PmEvtBase | [Shutdown](https://github.com/tianocore/edk2/blob/master/CorebootPayloadPkg/Library/Res...) | 4.8.3.1.1 +pm_tmr_blk | PmTmrBlk | PmTimerRegBase | [Timer](https://github.com/tianocore/edk2/blob/master/CorebootPayloadPkg/Library/Acp...) | 4.8.3.3 +reset_reg. | ResetReg.Address | ResetRegAddress | [Cold](https://github.com/tianocore/edk2/blob/master/CorebootPayloadPkg/Library/Res...) and [Warm](https://github.com/tianocore/edk2/blob/master/CorebootPayloadPkg/Library/Res...) resets | 4.3.3.6 +reset_value | ResetValue | ResetValue | [Cold](https://github.com/tianocore/edk2/blob/master/CorebootPayloadPkg/Library/Res...) and [Warm](https://github.com/tianocore/edk2/blob/master/CorebootPayloadPkg/Library/Res...) resets | 4.8.3.6 + + The EDK2 data structure is defined in MdeModulePkg/Include/IndustryStandard/[Acpi61.h](https://github.com/tianocore/edk2/blob/master/MdePkg/Include/IndustryStandar...) The coreboot data structure is defined in src/arch/x86/include/arch/[acpi.h](http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/inclu...) + + + +1. Select [HAVE_ACPI_TABLES](../Board/board.html#AcpiTables) in the board's Kconfig file +2. Create a acpi.c module: + + 1. Add the acpi_fill_in_fadt routine and initialize the values above + +-------------------------------------------------------------------------------- + +# [Legacy Hardware]() + +One of the payloads that needs legacy hardare is the EDK2 [CorebootPayloadPkg](quark.html#CorebootPayloadPkg). + +-------------------------------------------------------------------------------- + +Peripheral Use 8259 Interrupt Vector IDT Base Offset Interrupt Handler + +-------------------------------------------------------------------------------- + +[8254](http://www.scs.stanford.edu/10wi-cs140/pintos/specs/8254.pdf) Programmable Interval Timer EDK2: PcAtChipsetPkg/8254TimerDxe/[Timer.c](https://github.com/tianocore/edk2/blob/master/PcAtChipsetPkg/8254TimerDxe/Ti...) 0 0x340 [TimerInterruptHandler](https://github.com/tianocore/edk2/blob/master/PcAtChipsetPkg/8254TimerDxe/Ti...) + +[8259](https://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&a...) Programmable Interrupt Controller EDK2: PcAtChipsetPkg/8259InterruptControllerDxe/[8259.c](https://github.com/tianocore/edk2/blob/master/PcAtChipsetPkg/8259InterruptCo...) Master interrupts: 0, 2 - 7\ Master: 0x340, 0x350 - 0x378<br> +Slave interrupts: 8 - 15\ Slave: 0x380 - 0x3b8\ + +``` + Interrupt vector 1 is never generated, the cascaded input generates interrupts 8 - 15 Interrupt descriptors are 8 bytes each +``` + +-------------------------------------------------------------------------------- + +-------------------------------------------------------------------------------- + +Modified: 4 March 2016 diff --git a/Documentation/content/docs/vendor/intel/tableofcontents.md b/Documentation/content/docs/vendor/intel/tableofcontents.md new file mode 100644 index 0000000..9625eba --- /dev/null +++ b/Documentation/content/docs/vendor/intel/tableofcontents.md @@ -0,0 +1,70 @@ +--- +date: 2016-07-01T19:25:34.000Z +title: Table of Contents +name: Table of Contents +menu: + main: + parent: Intel Documentation +next: fsp1_1 +prev: index +weight: 10 +--- + +## Intel® x86 Boards + +- [Galileo](Board/galileo.html) +- [MinnowBoard MAX](http://wiki.minnowboard.org/Coreboot) + +# Intel® x86 SoCs + +- [Quark™](SoC/quark.html) + +-------------------------------------------------------------------------------- + +## x86 coreboot Development + +- Get the [coreboot source](https://www.coreboot.org/Git) +[](https://www.coreboot.org/Git)- [](https://www.coreboot.org/Git)%5BOverall%5D(development.html) development +- [FSP 1.1](fsp1_1.md) integration +- {{< relref "fsp1_1.md" >}} +- [SoC](SoC/soc.html) support +- [Board](Board/board.html) support + +-------------------------------------------------------------------------------- + +## Payload Development + +- [CorebootPayloadPkg](SoC/quark.html#CorebootPayloadPkg) + + - [EDK II Development Process](https://github.com/tianocore/tianocore.github.io/wiki/EDK-II-Development-Pro...) + - EDK II [White Papers](https://github.com/tianocore/tianocore.github.io/wiki/EDK%20II%20White%20pap...) + - [SourceForge to Github Quick Start](https://github.com/tianocore/tianocore.github.io/wiki/SourceForge-to-Github-...) + - UEFI [2.5 Errata A](http://www.uefi.org/sites/default/files/resources/UEFI%20Spec%202_5_Errata_A...) + +-------------------------------------------------------------------------------- + +## [Documentation]() + +- [ACPI Specifications](http://www.uefi.org/specifications) +- Intel® 64 and IA-32 Architectures [Software Developer Manual](http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32...) +- [UEFI Specifications](http://www.uefi.org/specifications) + +## [EDK-II Documentation]() + +- Build [V1.26](https://github.com/tianocore-docs/Docs/raw/master/Specifications/Build_Spec_...) +- Coding Standards [V2.1](https://github.com/tianocore-docs/Docs/raw/master/Specifications/CCS_2_1_Dra...) +- DEC [V1.25](https://github.com/tianocore-docs/Docs/raw/master/Specifications/DEC_Spec_1_...) +- DSC [V1.26](https://github.com/tianocore-docs/Docs/raw/master/Specifications/DSC_Spec_1_...) +- [Driver Writer's Guide](https://github.com/tianocore/tianocore.github.io/wiki/UEFI-Driver-Writer%27s...) +- Expression Syntax [V1.1](https://github.com/tianocore-docs/Docs/raw/master/Specifications/ExpressionS...) +- FDF [V1.26](https://github.com/tianocore-docs/Docs/raw/master/Specifications/FDF_Spec_1_...) +- INF [V1.25](https://github.com/tianocore-docs/Docs/raw/master/Specifications/INF_Spec_1_...) +- PCD [PCD](https://github.com/tianocore-docs/Docs/raw/master/Specifications/PCD_Infrast... +- UNI [V1.2 Errata A](https://github.com/tianocore-docs/Docs/raw/master/Specifications/UNI_File_Sp...) +- VRF [V1.9](https://github.com/tianocore-docs/Docs/raw/master/Specifications/VFR_1_9.pdf) + +## [FSP Documentation]() + +- Intel® Firmware Support Package External Architecture Specification [V2.0](http://www.intel.com/content/dam/www/public/us/en/documents/technical-specif...) +- Intel® Firmware Support Package External Architecture Specification [V1.1](http://www.intel.com/content/dam/www/public/us/en/documents/technical-specif...) +- Intel® Firmware Support Package External Architecture Specification [V1.0](http://www.intel.com/content/dam/www/public/us/en/documents/technical-specif...) diff --git a/Documentation/content/getting-started/gerrit.md b/Documentation/content/getting-started/gerrit.md new file mode 100644 index 0000000..878a90c --- /dev/null +++ b/Documentation/content/getting-started/gerrit.md @@ -0,0 +1,126 @@ +--- +date: 2016-07-01T19:25:34.000Z +title: Gerrit Guidelines +weight: 20 +menu: + main: + parent: Getting Started +name: Gerrit Guidelines +next: Submodules +prev: Getting Started +--- + +## Gerrit Guidelines + +### Gerrit Etiquette and Guidelines + +The following rules are the requirements for behavior in the coreboot codebase in gerrit. These have mainly been unwritten rules up to this point, and should be familiar to most users who have been active in coreboot for a period of time. Following these rules will help reduce friction in the community. + +Note that as with many rules, there are exceptions. Some have been noted in the 'More Detail' section. If you feel there is an exception not listed here, please discuss it in the mailing list to get this document updated. Don't just assume that it's okay, even if someone on IRC says it is. + +### Summary: + +These are the expectations for committing, reviewing, and submitting code into coreboot git and gerrit. While breaking individual rules may not have immediate consequences, the coreboot leadership may act on repeated or flagrant violations with or without notice. + +- Don't violate the licenses. +- Let non-trivial patches sit in a review state for at least 24 hours before submission. +- Try to coordinate with platform maintainers when making changes to platforms. +- If you give a patch a -2, you are responsible for giving concrete recommendations for what could be changed to resolve the issue the patch addresses. +- Don't modify other people's patches without their consent. +- Be respectful to others when commenting. +- Don't submit patches that you know will break other platforms. + +### More detail: + +- Don't violate the licenses. If you're submitting code that you didn't write yourself, make sure the license is compatible with the license of the project you're submitting the changes to. If you're submitting code that you wrote that might be owned by your employer, make sure that your employer is aware and you are authorized to submit the code. For clarification, see the Developer's Certificate of Origin in the coreboot [Signed-off-by policy](http://www.coreboot.org/Development_Guidelines#Sign-off_Procedure). + +- Let non-trivial patches sit in a review state for at least 24 hours before submission. Remember that there are coreboot developers in timezones all over the world, and everyone should have a chance to contribute. Trivial patches would be things like whitespace changes or spelling fixes. In general, small changes that don't impact the final binary output. The 24-hour period would start at submission, and would be restarted at any update which significantly changes any part of the patch. Patches can be 'Fast-tracked' and submitted in under this 24 hour with the agreement of at least 3 +2 votes. + +- Do not +2 patches that you authored or own, even for something as trivial as whitespace fixes. When working on your own patches, it's easy to overlook something like accidentally updating file permissions or git submodule commit IDs. Let someone else review the patch. An exception to this would be if two people worked in the patch together. If both +2 the patch, that is acceptable, as each is giving a +2 to the other's work. + +- Try to coordinate with platform maintainers and other significant contributors to the code when making changes to platforms. The platform maintainers are the users who initially pushed the code for that platform, as well as users who have made significant changes to a platform. To find out who maintains a piece of code, please use util/scripts/maintainers.go or refer to the original author of the code in git log. + +- If you give a patch a -2, you are responsible for giving concrete recommendations for what could be changed to resolve the issue the patch addresses. If you feel strongly that a patch should NEVER be merged, you are responsible for defending your position and listening to other points of view. Giving a -2 and walking away is not acceptable, and may cause your -2 to be removed by the coreboot leadership after no less than a week. A notification that the -2 will be removed unless there is a response will be sent out at least 2 days before it is removed. + +- Don't modify other people's patches unless you have coordinated this with the owner of that patch. Not only is this considered rude, but your changes could be unintentionally lost. An exception to this would be for patches that have not been updated for more than 90 days. In that case, the patch can be taken over if the original author does not respond to requests for updates. Alternatively, a new patch can be pushed with the original content, and both patches should be updated to reference the other. + +- Be respectful to others when commenting on patches. Comments should be kept to the code, and should be kept in a polite tone. We are a worldwide community and English is a difficult language. Assume your colleagues are intelligent and do not intend disrespect. Resist the urge to retaliate against perceived verbal misconduct, such behavior is not conducive to getting patches merged. + +- Don't submit code that you know will break other platforms. If your patch affects code that is used by other platforms, it should be compatible with those platforms. While it would be nice to update any other platforms, you must at least provide a path that will allow other platforms to continue working. + +### Recommendations for gerrit activity: + +These guidelines are less strict than the ones listed above. These are more of the "good idea" variety. You are requested to follow the below guidelines, but there will probably be no actual consequences if they're not followed. That said, following the recommendations below will speed up review of your patches, and make the members of the community do less work. + +- Each patch should be kept to one logical change, which should be described in the title of the patch. Unrelated changes should be split out into separate patches. Fixing whitespace on a line you're editing is reasonable. Fixing whitespace around the code you're working on should be a separate 'cleanup' patch. Larger patches that touch several areas are fine, so long as they are one logical change. Adding new chips and doing code cleanup over wide areas are two examples of this. + +- Test your patches before submitting them to gerrit. It's also appreciated if you add a line to the commit message describing how the patch was tested. This prevents people from having to ask whether and how the patch was tested. Examples of this sort of comment would be 'TEST=Built platform' or 'Tested by building and booting platform'. Stating that the patch was not tested is also fine, although you might be asked to do some testing in cases where that would be reasonable. + +- Take advantage of the lint tools to make sure your patches don't contain trivial mistakes. By running 'make gitconfig', the lint-stable tools are automatically put in place and will test your patches before they are committed. As a violation of these tools will cause the jenkins build test to fail, it's to your advantage to test this before pushing to gerrit. + +- Don't submit patch trains longer than around 20 patches unless you understand how to manage long patch trains. Long patch trains can become difficult to handle and tie up the build servers for long periods of time if not managed well. Rebasing a patch train over and over as you fix earlier patches in the train can hide comments, and make people review the code multiple times to see if anything has changed between revisions. When pushing long patch trains, it is recommended to only push the full patch train once - the initial time, and only to rebase three or four patches at a time. + +- Run 'make what-jenkins-does' locally on patch trains before submitting. This helps verify that the patch train won't tie up the jenkins builders for no reason if there are failing patches in the train. For running parallel builds, you can specify the number of cores to use by setting the the CPUS environment variable. Example: + + ```sh + make what-jenkins-does CPUS=8 + ``` + +- Use a topic when pushing a train of patches. This groups the commits together so people can easily see the connection at the top level of gerrit. Topics can be set for individual patches in gerrit by going into the patch and clicking on the icon next to the topic line. Topics can also be set when you push the patches into gerrit. For example, to push a set of commits with the the i915-kernel-x60 set, use the command: + + ```sh + git push origin HEAD:refs/for/master/i915-kernel-x60 + ``` + +- If one of your patches isn't ready to be merged, make sure it's obvious that you don't feel it's ready for merge yet. The preferred way to show this is by marking in the commit message that it's not ready until X. The commit message can be updated easily when it's ready to be pushed. Examples of this are "WIP: title" or "[NEEDS_TEST]: title". Another way to mark the patch as not ready would be to give it a -1 or -2 review, but isn't as obvious as the commit message. These patches can also be pushed as drafts as shown in the next guideline. + +- When pushing patches that are not for submission, these should be marked as such. This can be done in the title '[DONOTSUBMIT]', or can be pushed as draft commits, so that only explicitly added reviewers will see them. These sorts of patches are frequently posted as ideas or RFCs for the community to look at. To push a draft, use the command: + + ```sh + git push origin HEAD:refs/drafts/master + ``` + +- Respond to anyone who has taken the time to review your patches, even if it's just to say that you disagree. While it may seem annoying to address a request to fix spelling or 'trivial' issues, it's generally easy to handle in gerrit's built-in editor. If you do use the built-in editor, remember to get that change to your local copy before re-pushing. It's also acceptable to add fixes for these sorts of comments to another patch, but it's recommended that that patch be pushed to gerrit before the initial patch gets submitted. + +- Consider breaking up large individual patches into smaller patches grouped by areas. This makes the patches easier to review, but increases the number of patches. The way you want to handle this is a personal decision, as long as each patch is still one logical change. + +- If you have an interest in a particular area or mainboard, set yourself up as a 'maintainer' of that area by adding yourself to the MAINTAINERS file in the coreboot root directory. Eventually, this should automatically add you as a reviewer when an area that you're listed as a maintainer is changed. + +- Submit mainboards that you're working on to the board-status repo. This helps others and shows that these mainboards are currently being maintained. At some point, boards that are not up to date in the board-status repo will probably end up getting removed from the coreboot master branch. + +- Abandon patches that are no longer useful, or that you don't intend to keep working on to get submitted. + +- Bring attention to patches that you would like reviewed. Add reviewers, ask for reviewers on IRC or even just rebase it against the current codebase to bring it to the top of the gerrit list. If you're not sure who would be a good reviewer, look in the MAINTAINERS file or git history of the files that you've changed, and add those people. + +- Familiarize yourself with the coreboot [commit message guidelines](http://www.coreboot.org/Git#Commit_messages), before pushing patches. This will help to keep annoying requests to fix your commit message to a minimum. + +- If there have been comments or discussion on a patch, verify that the comments have been addressed before giving a +2. If you feel that a comment is invalid, please respond to that comment instead of just ignoring it. + +- Be conscientious when reviewing patches. As a reviewer who approves (+2) a patch, you are responsible for the patch and the effect it has on the codebase. In the event that the patch breaks things, you are expected to be actively involved in the cleanup effort. This means you shouldn't +2 a patch just because you trust the author of a patch - Make sure you understand what the implications of a patch might be, or leave the review to others. Partial reviews, reviewing code style, for example, can be given a +1 instead of a +2. This also applies if you think the patch looks good, but may not have the experience to know if there may be unintended consequences. + +- If there is still ongoing discussion to a patch, try to wait for a conclusion to the discussion before submitting it to the tree. If you feel that someone is just bikeshedding, maybe just state that and give a time that the patch will be submitted if no new objections are raised. + +- When working with patch trains, for minor requests it's acceptable to create a fix addressing a comment in another patch at the end of the patch train. This minimizes rebases of the patch train while still addressing the request. For major problems where the change doesn't work as intended or breaks other platforms, the change really needs to go into the original patch. + +- When bringing in a patch from another git repo, update the original git/gerrit tags by prepending the lines with 'Original-'. Marking the original text this way makes it much easier to tell what changes happened in which repository. This applies to these lines, not the actual commit message itself: + + ``` + Commit-Id: + Change-Id: + Signed-off-by: + Reviewed-on: + Tested-by: + Reviewed-by: + ``` + + The script 'util/gitconfig/rebase.sh' can be used to help automate this. Other tags such as 'Commit-Queue' can simply be removed. + +### Expectations contributors should have: + +- Don't expect that people will review your patch unless you ask them to. Adding other people as reviewers is the easiest way. Asking for reviews for individual patches in the IRC channel, or by sending a direct request to an individual through your favorite messenger is usually the best way to get a patch reviewed quickly. + +- Don't expect that your patch will be submitted immediately after getting a +2. As stated previously, non-trivial patches should wait at least 24 hours before being submitted. That said, if you feel that your patch or series of patches has been sitting longer than needed, you can ask for it to be submitted on IRC, or comment that it's ready for submission in the patch. This will move it to the top of the list where it's more likely to be noticed and acted upon. + +- Reviews are about the code. It's easy to take it personally when someone is criticising your code, but the whole idea is to get better code into our codebase. Again, this also applies in the other direction: review code, criticize code, but don't make it personal. + +Requests for clarification and suggestions for updates to these guidelines should be sent to the coreboot mailing list at [coreboot@coreboot.org](mailto:coreboot@coreboot.org). diff --git a/Documentation/content/getting-started/index.md b/Documentation/content/getting-started/index.md new file mode 100644 index 0000000..ff4b5b9 --- /dev/null +++ b/Documentation/content/getting-started/index.md @@ -0,0 +1,10 @@ +--- +date: 2016-07-01T19:25:34.000Z +title: Getting Started +weight: 10 +menu: + main: +name: Getting Started +url: getting-started/ +next: Gerrit Guidelines +--- diff --git a/Documentation/content/getting-started/submodules.md b/Documentation/content/getting-started/submodules.md new file mode 100644 index 0000000..c1c895d --- /dev/null +++ b/Documentation/content/getting-started/submodules.md @@ -0,0 +1,43 @@ +--- +date: 2016-07-01T19:25:34.000Z +title: Git Submodules +weight: 30 +menu: + main: + parent: Getting Started +name: Submodules +--- + +## Use of git submodules in coreboot + +coreboot uses git submodules to keep certain parts of the tree separate, with two major use cases: + +First, we use a vendor tool by NVIDIA for systems based on their SoC and since they publish it through git, we can just import it into our tree using submodules. + +Second, lots of boards these days require binaries and we want to keep them separate from coreboot proper to clearly delineate shiny Open Source from ugly blobs. Since we don't want to impose blobs on users who really don't need them, that repository is only downloaded and checked out on explicit request. + +### Handling submodules + +For the most part, submodules should be automatically checked out on the first execution of the coreboot Makefile. + +To manually fetch all repositories (eg. when you want to prepare the tree for archiving, or to use it without network access), run + +``` +$ git submodule update --init --checkout +``` + +This also checks out the binaries below `3rdparty/` + +### Mirroring coreboot + +When running a coreboot mirror to checkout from, for full operation, you should also mirror the blobs and nvidia-cbootimage repository, and place them in the same directory as the coreboot repository mirror. + +That is, when residing in coreboot's repository, `cd ../blobs.git` should move you to the blobs repository. + +With that, no matter what the URL of your coreboot repository is, the git client (of a sufficiently new version) is able to pick up the other repositories transparently. + +### Minimum requirements + +git needs to be able to handle relative paths to submodule repositories, and it needs to know about non-automatic submodules. + +For these features, we require git version 1.7.6.1 or newer. diff --git a/Documentation/content/index.md b/Documentation/content/index.md new file mode 100644 index 0000000..0c7ee73 --- /dev/null +++ b/Documentation/content/index.md @@ -0,0 +1,10 @@ +--- +date: 2016-03-08T21:07:13+01:00 +title: The Project +type: index +weight: 0 +--- + +## Introduction + +Welcome to coreboot diff --git a/Documentation/content/licenses/index.md b/Documentation/content/licenses/index.md new file mode 100644 index 0000000..11979f5 --- /dev/null +++ b/Documentation/content/licenses/index.md @@ -0,0 +1,9 @@ +--- +date: 2016-07-01T19:25:34.000Z +title: Licenses +weight: 99 +menu: + main: +name: Licenses +url: licenses/ +--- diff --git a/Documentation/coreboot_logo.png b/Documentation/coreboot_logo.png deleted file mode 100644 index dde1aa6..0000000 Binary files a/Documentation/coreboot_logo.png and /dev/null differ diff --git a/Documentation/endverbatim.tex b/Documentation/endverbatim.tex deleted file mode 100644 index f832f3f..0000000 --- a/Documentation/endverbatim.tex +++ /dev/null @@ -1 +0,0 @@ -\end{verbatim} diff --git a/Documentation/gcov.txt b/Documentation/gcov.txt deleted file mode 100644 index 896ec93..0000000 --- a/Documentation/gcov.txt +++ /dev/null @@ -1,227 +0,0 @@ -This patch contains our local modifications for gcov-io.h and libgcov.c. -The file gcov-iov.h is taken from a gcc build (produced at compile -time). The file gcov-io.c is unchanged. - ---- gcc-4.7.2/gcc/gcov-io.h 2011-12-04 10:27:19.000000000 -0800 -+++ coreboot/src/lib/gcov-io.h 2013-01-12 16:45:57.000000000 -0800 -@@ -163,6 +163,24 @@ - #ifndef GCC_GCOV_IO_H - #define GCC_GCOV_IO_H - -+#ifdef __COREBOOT__ -+#define GCOV_LINKAGE /* nothing */ -+/* We need the definitions for -+ BITS_PER_UNIT and -+ LONG_LONG_TYPE_SIZE -+ They are defined in gcc/defaults.h and gcc/config/<arch_depend_files> -+ (like, gcc/config/i386/i386.h). And it can be overridden by setting -+ in build scripts. Here I hardcoded the value for x86. */ -+#define BITS_PER_UNIT 8 -+#define LONG_LONG_TYPE_SIZE 64 -+ -+/* There are many gcc_assertions. Set the vaule to 1 if we want a warning -+ message if the assertion fails. */ -+#ifndef ENABLE_ASSERT_CHECKING -+#define ENABLE_ASSERT_CHECKING 1 -+#endif -+#endif /* __COREBOOT__ */ -+ - #if IN_LIBGCOV - /* About the target */ - -@@ -232,7 +250,9 @@ - is not also used in a DSO. */ - #if IN_LIBGCOV - -+#ifndef __COREBOOT__ - #include "tconfig.h" -+#endif /* __COREBOOT__ */ - - #define gcov_var __gcov_var - #define gcov_open __gcov_open -@@ -455,8 +475,10 @@ - /* Register a new object file module. */ - extern void __gcov_init (struct gcov_info *) ATTRIBUTE_HIDDEN; - -+#ifndef __COREBOOT__ - /* Called before fork, to avoid double counting. */ - extern void __gcov_flush (void) ATTRIBUTE_HIDDEN; -+#endif - - /* The merge function that just sums the counters. */ - extern void __gcov_merge_add (gcov_type *, unsigned) ATTRIBUTE_HIDDEN; ---- gcc-4.7.2/libgcc/libgcov.c 2012-01-11 10:50:21.000000000 -0800 -+++ coreboot/src/lib/libgcov.c 2013-01-16 09:45:11.000000000 -0800 -@@ -25,12 +25,41 @@ - see the files COPYING3 and COPYING.RUNTIME respectively. If not, see - http://www.gnu.org/licenses/. */ - -+#define __COREBOOT__ -+#ifdef __COREBOOT__ -+#include <stdlib.h> -+#include <string.h> -+#include <console/console.h> -+#include <assert.h> -+typedef s32 pid_t; -+#define gcc_assert(x) ASSERT(x) -+#define fprintf(file, x...) printk(BIOS_ERR, x) -+#define alloca(size) __builtin_alloca (size) -+#include "gcov-glue.c" -+ -+/* Define MACROs to be used by coreboot compilation. */ -+# define L_gcov -+# define L_gcov_interval_profiler -+# define L_gcov_pow2_profiler -+# define L_gcov_one_value_profiler -+# define L_gcov_indirect_call_profiler -+# define L_gcov_average_profiler -+# define L_gcov_ior_profiler -+ -+# define HAVE_CC_TLS 0 -+# define __GCOV_KERNEL__ -+ -+# define IN_LIBGCOV 1 -+# define IN_GCOV 0 -+#else /* __COREBOOT__ */ - #include "tconfig.h" - #include "tsystem.h" - #include "coretypes.h" - #include "tm.h" - #include "libgcc_tm.h" -+#endif /* __COREBOOT__ */ - -+#ifndef __COREBOOT__ - #if defined(inhibit_libc) - #define IN_LIBGCOV (-1) - #else -@@ -41,6 +70,7 @@ - #define GCOV_LINKAGE /* nothing */ - #endif - #endif -+#endif /* __COREBOOT__ */ - #include "gcov-io.h" - - #if defined(inhibit_libc) -@@ -68,12 +98,17 @@ - - #else - -+#ifndef __COREBOOT__ - #include <string.h> - #if GCOV_LOCKED - #include <fcntl.h> - #include <errno.h> - #include <sys/stat.h> - #endif -+#else -+void __gcov_merge_add(gcov_type *counters __attribute__ ((unused)), -+ unsigned n_counters __attribute__ ((unused))) {} -+#endif /* __COREBOOT__ */ - - #ifdef L_gcov - #include "gcov-io.c" -@@ -99,6 +134,10 @@ - static int - create_file_directory (char *filename) - { -+#ifdef __COREBOOT__ -+ (void) filename; -+ return 0; -+#else - #if !defined(TARGET_POSIX_IO) && !defined(_WIN32) - (void) filename; - return -1; -@@ -137,6 +176,7 @@ - }; - return 0; - #endif -+#endif - } - - static struct gcov_fn_buffer * -@@ -279,7 +319,7 @@ - struct gcov_ctr_summary *cs_ptr; - const struct gcov_ctr_info *ci_ptr; - unsigned t_ix; -- int f_ix; -+ int f_ix = 0; - gcov_unsigned_t c_num; - const char *gcov_prefix; - int gcov_prefix_strip = 0; -@@ -329,6 +369,7 @@ - } - } - -+#ifndef __COREBOOT__ - { - /* Check if the level of dirs to strip off specified. */ - char *tmp = getenv("GCOV_PREFIX_STRIP"); -@@ -352,6 +393,7 @@ - prefix_length--; - } - else -+#endif - prefix_length = 0; - - /* If no prefix was specified and a prefix stip, then we assume -@@ -696,8 +738,10 @@ - if (filename_length > gcov_max_filename) - gcov_max_filename = filename_length; - -+#ifndef __COREBOOT__ - if (!gcov_list) - atexit (gcov_exit); -+#endif - - info->next = gcov_list; - gcov_list = info; -@@ -767,14 +811,15 @@ - - #ifdef L_gcov_merge_single - /* The profile merging function for choosing the most common value. -- It is given an array COUNTERS of N_COUNTERS old counters and it -- reads the same number of counters from the gcov file. The counters -- are split into 3-tuples where the members of the tuple have -- meanings: -- -- -- the stored candidate on the most common value of the measured entity -- -- counter -- -- total number of evaluations of the value */ -+ * It is given an array COUNTERS of N_COUNTERS old counters and it -+ * reads the same number of counters from the gcov file. The counters -+ * are split into 3-tuples where the members of the tuple have -+ * meanings: -+ * -+ * -- the stored candidate on the most common value of the measured entity -+ * -- counter -+ * -- total number of evaluations of the value -+ */ - void - __gcov_merge_single (gcov_type *counters, unsigned n_counters) - { -@@ -805,15 +850,16 @@ - - #ifdef L_gcov_merge_delta - /* The profile merging function for choosing the most common -- difference between two consecutive evaluations of the value. It is -- given an array COUNTERS of N_COUNTERS old counters and it reads the -- same number of counters from the gcov file. The counters are split -- into 4-tuples where the members of the tuple have meanings: -- -- -- the last value of the measured entity -- -- the stored candidate on the most common difference -- -- counter -- -- total number of evaluations of the value */ -+ * difference between two consecutive evaluations of the value. It is -+ * given an array COUNTERS of N_COUNTERS old counters and it reads the -+ * same number of counters from the gcov file. The counters are split -+ * into 4-tuples where the members of the tuple have meanings: -+ * -+ * -- the last value of the measured entity -+ * -- the stored candidate on the most common difference -+ * -- counter -+ * -- total number of evaluations of the value -+ */ - void - __gcov_merge_delta (gcov_type *counters, unsigned n_counters) - { diff --git a/Documentation/gerrit_guidelines.md b/Documentation/gerrit_guidelines.md deleted file mode 100644 index 1833b0a..0000000 --- a/Documentation/gerrit_guidelines.md +++ /dev/null @@ -1,277 +0,0 @@ -coreboot Gerrit Etiquette and Guidelines -======================================== - -The following rules are the requirements for behavior in the coreboot -codebase in gerrit. These have mainly been unwritten rules up to this -point, and should be familiar to most users who have been active in -coreboot for a period of time. Following these rules will help reduce -friction in the community. - -Note that as with many rules, there are exceptions. Some have been noted -in the 'More Detail' section. If you feel there is an exception not listed -here, please discuss it in the mailing list to get this document updated. -Don't just assume that it's okay, even if someone on IRC says it is. - - -Summary: --------- -These are the expectations for committing, reviewing, and submitting code -into coreboot git and gerrit. While breaking individual rules may not have -immediate consequences, the coreboot leadership may act on repeated or -flagrant violations with or without notice. - -* Don't violate the licenses. -* Let non-trivial patches sit in a review state for at least 24 hours -before submission. -* Try to coordinate with platform maintainers when making changes to -platforms. -* If you give a patch a -2, you are responsible for giving concrete -recommendations for what could be changed to resolve the issue the patch -addresses. -* Don't modify other people's patches without their consent. -* Be respectful to others when commenting. -* Don’t submit patches that you know will break other platforms. - - -More detail: ------------- -* Don't violate the licenses. If you're submitting code that you didn't -write yourself, make sure the license is compatible with the license of the -project you're submitting the changes to. If you’re submitting code that -you wrote that might be owned by your employer, make sure that your -employer is aware and you are authorized to submit the code. For -clarification, see the Developer's Certificate of Origin in the coreboot -[Signed-off-by policy](http://www.coreboot.org/Development_Guidelines#Sign-off_Procedure). - -* Let non-trivial patches sit in a review state for at least 24 hours -before submission. Remember that there are coreboot developers in timezones -all over the world, and everyone should have a chance to contribute. -Trivial patches would be things like whitespace changes or spelling fixes. -In general, small changes that don’t impact the final binary output. The -24-hour period would start at submission, and would be restarted at any -update which significantly changes any part of the patch. Patches can be -'Fast-tracked' and submitted in under this 24 hour with the agreement of at -least 3 +2 votes. - -* Do not +2 patches that you authored or own, even for something as trivial -as whitespace fixes. When working on your own patches, it’s easy to -overlook something like accidentally updating file permissions or git -submodule commit IDs. Let someone else review the patch. An exception to -this would be if two people worked in the patch together. If both +2 the -patch, that is acceptable, as each is giving a +2 to the other's work. - -* Try to coordinate with platform maintainers and other significant -contributors to the code when making changes to platforms. The platform -maintainers are the users who initially pushed the code for that platform, -as well as users who have made significant changes to a platform. To find -out who maintains a piece of code, please use util/scripts/maintainers.go -or refer to the original author of the code in git log. - -* If you give a patch a -2, you are responsible for giving concrete -recommendations for what could be changed to resolve the issue the patch -addresses. If you feel strongly that a patch should NEVER be merged, you -are responsible for defending your position and listening to other points -of view. Giving a -2 and walking away is not acceptable, and may cause your - -2 to be removed by the coreboot leadership after no less than a week. A - notification that the -2 will be removed unless there is a response will - be sent out at least 2 days before it is removed. - -* Don't modify other people's patches unless you have coordinated this with -the owner of that patch. Not only is this considered rude, but your changes -could be unintentionally lost. An exception to this would be for patches -that have not been updated for more than 90 days. In that case, the patch -can be taken over if the original author does not respond to requests for -updates. Alternatively, a new patch can be pushed with the original -content, and both patches should be updated to reference the other. - -* Be respectful to others when commenting on patches. Comments should -be kept to the code, and should be kept in a polite tone. We are a -worldwide community and English is a difficult language. Assume your -colleagues are intelligent and do not intend disrespect. Resist the urge to -retaliate against perceived verbal misconduct, such behavior is not -conducive to getting patches merged. - -* Don’t submit code that you know will break other platforms. If your patch -affects code that is used by other platforms, it should be compatible with -those platforms. While it would be nice to update any other platforms, you -must at least provide a path that will allow other platforms to continue -working. - - -Recommendations for gerrit activity: ------------------------------------- -These guidelines are less strict than the ones listed above. These are more -of the “good idea” variety. You are requested to follow the below -guidelines, but there will probably be no actual consequences if they’re -not followed. That said, following the recommendations below will speed up -review of your patches, and make the members of the community do less work. - -* Each patch should be kept to one logical change, which should be -described in the title of the patch. Unrelated changes should be split out -into separate patches. Fixing whitespace on a line you’re editing is -reasonable. Fixing whitespace around the code you’re working on should be a -separate ‘cleanup’ patch. Larger patches that touch several areas are fine, -so long as they are one logical change. Adding new chips and doing code -cleanup over wide areas are two examples of this. - -* Test your patches before submitting them to gerrit. It's also appreciated -if you add a line to the commit message describing how the patch was -tested. This prevents people from having to ask whether and how the patch -was tested. Examples of this sort of comment would be ‘TEST=Built -platform’ or ‘Tested by building and booting platform’. Stating that the -patch was not tested is also fine, although you might be asked to do some -testing in cases where that would be reasonable. - -* Take advantage of the lint tools to make sure your patches don’t contain -trivial mistakes. By running ‘make gitconfig’, the lint-stable tools are -automatically put in place and will test your patches before they are -committed. As a violation of these tools will cause the jenkins build test -to fail, it’s to your advantage to test this before pushing to gerrit. - -* Don't submit patch trains longer than around 20 patches unless you -understand how to manage long patch trains. Long patch trains can become -difficult to handle and tie up the build servers for long periods of time -if not managed well. Rebasing a patch train over and over as you fix -earlier patches in the train can hide comments, and make people review the -code multiple times to see if anything has changed between revisions. When -pushing long patch trains, it is recommended to only push the full patch -train once - the initial time, and only to rebase three or four patches at -a time. - -* Run 'make what-jenkins-does' locally on patch trains before submitting. -This helps verify that the patch train won’t tie up the jenkins builders -for no reason if there are failing patches in the train. For running -parallel builds, you can specify the number of cores to use by setting the -the CPUS environment variable. Example: - make what-jenkins-does CPUS=8 - -* Use a topic when pushing a train of patches. This groups the commits -together so people can easily see the connection at the top level of -gerrit. Topics can be set for individual patches in gerrit by going into -the patch and clicking on the icon next to the topic line. Topics can also -be set when you push the patches into gerrit. For example, to push a set of -commits with the the i915-kernel-x60 set, use the command: - git push origin HEAD:refs/for/master/i915-kernel-x60 - -* If one of your patches isn't ready to be merged, make sure it's obvious -that you don't feel it's ready for merge yet. The preferred way to show -this is by marking in the commit message that it’s not ready until X. The -commit message can be updated easily when it’s ready to be pushed. -Examples of this are "WIP: title" or "[NEEDS_TEST]: title". Another way to -mark the patch as not ready would be to give it a -1 or -2 review, but -isn't as obvious as the commit message. These patches can also be pushed as -drafts as shown in the next guideline. - -* When pushing patches that are not for submission, these should be marked -as such. This can be done in the title ‘[DONOTSUBMIT]’, or can be pushed as -draft commits, so that only explicitly added reviewers will see them. These -sorts of patches are frequently posted as ideas or RFCs for the community -to look at. To push a draft, use the command: - git push origin HEAD:refs/drafts/master - -* Respond to anyone who has taken the time to review your patches, even if -it's just to say that you disagree. While it may seem annoying to address a -request to fix spelling or 'trivial' issues, it’s generally easy to handle -in gerrit’s built-in editor. If you do use the built-in editor, remember to -get that change to your local copy before re-pushing. It's also acceptable -to add fixes for these sorts of comments to another patch, but it's -recommended that that patch be pushed to gerrit before the initial patch -gets submitted. - -* Consider breaking up large individual patches into smaller patches -grouped by areas. This makes the patches easier to review, but increases -the number of patches. The way you want to handle this is a personal -decision, as long as each patch is still one logical change. - -* If you have an interest in a particular area or mainboard, set yourself -up as a ‘maintainer’ of that area by adding yourself to the MAINTAINERS -file in the coreboot root directory. Eventually, this should automatically -add you as a reviewer when an area that you’re listed as a maintainer is -changed. - -* Submit mainboards that you’re working on to the board-status repo. This -helps others and shows that these mainboards are currently being -maintained. At some point, boards that are not up to date in the -board-status repo will probably end up getting removed from the coreboot -master branch. - -* Abandon patches that are no longer useful, or that you don’t intend to -keep working on to get submitted. - -* Bring attention to patches that you would like reviewed. Add reviewers, -ask for reviewers on IRC or even just rebase it against the current -codebase to bring it to the top of the gerrit list. If you’re not sure who -would be a good reviewer, look in the MAINTAINERS file or git history of -the files that you’ve changed, and add those people. - -* Familiarize yourself with the coreboot [commit message -guidelines](http://www.coreboot.org/Git#Commit_messages), before pushing -patches. This will help to keep annoying requests to fix your commit -message to a minimum. - -* If there have been comments or discussion on a patch, verify that the -comments have been addressed before giving a +2. If you feel that a comment -is invalid, please respond to that comment instead of just ignoring it. - -* Be conscientious when reviewing patches. As a reviewer who approves (+2) -a patch, you are responsible for the patch and the effect it has on the -codebase. In the event that the patch breaks things, you are expected to -be actively involved in the cleanup effort. This means you shouldn’t +2 a -patch just because you trust the author of a patch - Make sure you -understand what the implications of a patch might be, or leave the review -to others. Partial reviews, reviewing code style, for example, can be given -a +1 instead of a +2. This also applies if you think the patch looks good, -but may not have the experience to know if there may be unintended -consequences. - -* If there is still ongoing discussion to a patch, try to wait for a -conclusion to the discussion before submitting it to the tree. If you feel -that someone is just bikeshedding, maybe just state that and give a time -that the patch will be submitted if no new objections are raised. - -* When working with patch trains, for minor requests it’s acceptable to -create a fix addressing a comment in another patch at the end of the patch -train. This minimizes rebases of the patch train while still addressing the -request. For major problems where the change doesn’t work as intended or -breaks other platforms, the change really needs to go into the original -patch. - -* When bringing in a patch from another git repo, update the original -git/gerrit tags by prepending the lines with 'Original-'. Marking -the original text this way makes it much easier to tell what changes -happened in which repository. This applies to these lines, not the actual -commit message itself: - Commit-Id: - Change-Id: - Signed-off-by: - Reviewed-on: - Tested-by: - Reviewed-by: -The script 'util/gitconfig/rebase.sh' can be used to help automate this. -Other tags such as 'Commit-Queue' can simply be removed. - - -Expectations contributors should have: --------------------------------------- -* Don't expect that people will review your patch unless you ask them to. -Adding other people as reviewers is the easiest way. Asking for reviews for -individual patches in the IRC channel, or by sending a direct request to an -individual through your favorite messenger is usually the best way to get a -patch reviewed quickly. - -* Don't expect that your patch will be submitted immediately after getting -a +2. As stated previously, non-trivial patches should wait at least 24 -hours before being submitted. That said, if you feel that your patch or -series of patches has been sitting longer than needed, you can ask for it -to be submitted on IRC, or comment that it's ready for submission in the -patch. This will move it to the top of the list where it's more likely to -be noticed and acted upon. - -* Reviews are about the code. It's easy to take it personally when someone -is criticising your code, but the whole idea is to get better code into our -codebase. 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a/Documentation/mainboard_io_trap_handler_sample.c +++ /dev/null @@ -1,51 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/io.h> -#include <console/console.h> -#include <cpu/x86/smm.h> -#include <soc/pm.h> -#include <soc/smm.h> -#include <elog.h> -#include <ec/google/chromeec/ec.h> -#include <soc/gpio.h> -#include <soc/iomap.h> -#include <soc/nvs.h> -#include <soc/pm.h> -#include <soc/smm.h> -#include "ec.h" -#include "gpio.h" - -int mainboard_io_trap_handler(int smif) -{ - switch (smif) { - case 0x99: - printk(BIOS_DEBUG, "Sample\n"); - smm_get_gnvs()->smif = 0; - break; - default: - return 0; - } - - /* On success, the IO Trap Handler returns 0 - * On failure, the IO Trap Handler returns a value != 0 - * - * For now, we force the return value to 0 and log all traps to - * see what's going on. - */ - //smm_get_gnvs()->smif = 0; - return 1; -} diff --git a/Documentation/static/favicon.ico b/Documentation/static/favicon.ico new file mode 100644 index 0000000..cab4e60 Binary files /dev/null and b/Documentation/static/favicon.ico differ diff --git a/Documentation/static/images/favicon.ico b/Documentation/static/images/favicon.ico new file mode 100644 index 0000000..ca4d789 Binary files /dev/null and b/Documentation/static/images/favicon.ico differ diff --git a/Documentation/static/images/logo.png b/Documentation/static/images/logo.png new file mode 100644 index 0000000..0e02535 Binary files /dev/null and b/Documentation/static/images/logo.png differ diff --git a/Documentation/submodules.txt b/Documentation/submodules.txt deleted file mode 100644 index 631e3513..0000000 --- a/Documentation/submodules.txt +++ /dev/null @@ -1,46 +0,0 @@ -Use of git submodules in coreboot -================================= -coreboot uses git submodules to keep certain parts of the tree separate, -with two major use cases: - -First, we use a vendor tool by NVIDIA for systems based on their SoC -and since they publish it through git, we can just import it into our -tree using submodules. - -Second, lots of boards these days require binaries and we want to keep -them separate from coreboot proper to clearly delineate shiny Open Source -from ugly blobs. -Since we don't want to impose blobs on users who really don't need them, -that repository is only downloaded and checked out on explicit request. - -Handling submodules -------------------- -For the most part, submodules should be automatically checked out on the -first execution of the coreboot Makefile. - -To manually fetch all repositories (eg. when you want to prepare the tree -for archiving, or to use it without network access), run - - $ git submodule update --init --checkout - -This also checks out the binaries below `3rdparty/` - -Mirroring coreboot ------------------- -When running a coreboot mirror to checkout from, for full operation, you -should also mirror the blobs and nvidia-cbootimage repository, and place -them in the same directory as the coreboot repository mirror. - -That is, when residing in coreboot's repository, `cd ../blobs.git` -should move you to the blobs repository. - -With that, no matter what the URL of your coreboot repository is, the -git client (of a sufficiently new version) is able to pick up the other -repositories transparently. - -Minimum requirements --------------------- -git needs to be able to handle relative paths to submodule repositories, -and it needs to know about non-automatic submodules. - -For these features, we require git version 1.7.6.1 or newer. diff --git a/Documentation/themes/hugo-material-docs b/Documentation/themes/hugo-material-docs new file mode 160000 index 0000000..75ecc75 --- /dev/null +++ b/Documentation/themes/hugo-material-docs @@ -0,0 +1 @@ +Subproject commit 75ecc75cc16425c72adda67ab7f24af49ddb2644 diff --git a/Documentation/timestamp.md b/Documentation/timestamp.md deleted file mode 100644 index 3a4c73b..0000000 --- a/Documentation/timestamp.md +++ /dev/null @@ -1,200 +0,0 @@ -Table of Contents -================= -Introduction - Transition from cache to cbmem - -Data structures used - cache_state - table - entries - -Function APIs - timestamp_init - timestamp_add - timestamp_add_now - timestamp_sync - -Use / Test Cases - Case 1: Timestamp Region Exists - Case 2: No timestamp region, fresh boot, cbmem_initialize called after - timestamp_init - Case 3: No timestamp region, fresh boot, cbmem_initialize called before - timestamp_init - Case 4: No timestamp region, resume, cbmem_initialize called after - timestamp_init - Case 5: No timestamp region, resume, cbmem_initialize called before - timestamp_init - - -Introduction -============ -The aim of the timestamp library is to make it easier for different boards -to save timestamps in cbmem / stash (until cbmem is brought up) by -providing a simple API to initialize, add and sync timestamps. In order -to make the timestamps persistent and accessible from the kernel, we -need to ensure that all the saved timestamps end up in cbmem under -the CBMEM_ID_TIMESTAMP tag. However, until the cbmem area is available, -the timestamps can be saved to a SoC-defined _timestamp region or in a -local stage-specific stash. The work of identifying the right location for -storing timestamps is done by the library and is not exposed to the user. - -Working of timestamp library from a user perspective can be outlined in -the following steps: -1. Initialize the base time and reset cbmem timestamp area -2. Start adding timestamps - -Behind the scenes, the timestamp library takes care of: -1. Identifying the correct location for storing timestamps (cbmem or timestamp - region or local stash). -2. Once cbmem is up, ensure that all timestamps are synced from timestamp - region or local stash into the cbmem area. -3. Add a new cbmem timestamp area based on whether a reset of the cbmem - timestamp region is required or not. - -Transition from cache to cbmem ------------------------------- -To move timestamps from the cache to cbmem (and initialize the cbmem area in -the first place), we use the CBMEM_INIT_HOOK infrastructure of coreboot. - -When cbmem is initialized, the hook is called, which creates the area, -copies all timestamps to cbmem and disables the cache. - -After such a transition, timestamp_init() must not be run again. - - -Data structures used -==================== -The main structure that maintains information about the timestamp cache is: -struct __attribute__((__packed__)) timestamp_cache { - uint16_t cache_state; - struct timestamp_table table; - struct timestamp_entry entries[MAX_TIMESTAMP_CACHE]; -}; - -cache_state ------------ -The state of the cache is maintained by cache_state attribute which can -be any one of the following: - -enum { - TIMESTAMP_CACHE_UNINITIALIZED = 0, - TIMESTAMP_CACHE_INITIALIZED, - TIMESTAMP_CACHE_NOT_NEEDED, -}; - -By default, if the cache is stored in local stash (bss area), then -it will be reset to uninitialized state. However, if the cache is -stored in timestamp region, then it might have garbage in any of the -attributes. Thus, if the timestamp region is being used by any board, it is -initialized to default values by the library. - -Once the cache is initialized, its state is set to -CACHE_INITIALIZED. Henceforth, the calls to cache i.e. timestamp_add -know that the state reflected is valid and timestamps can be directly -saved in the cache. - -Once the cbmem area is up (i.e. call to timestamp_sync_cache_to_cbmem), -we do not need to store the timestamps in local stash / timestamp area -anymore. Thus, the cache state is set to CACHE_NOT_NEEDED, which allows -timestamp_add to store all timestamps directly into the cbmem area. - - -table ------ -This field is represented by a structure which provides overall -information about the entries in the timestamp area: - -struct timestamp_table { - uint64_t base_time; - uint32_t max_entries; - uint32_t num_entries; - struct timestamp_entry entries[0]; /* Variable number of entries */ -} __attribute__((packed)); - -It indicates the base time for all timestamp entries, maximum number -of entries that can be stored, total number of entries that currently -exist and an entry structure to hold variable number of entries. - - -entries -------- -This field holds the details of each timestamp entry, upto a maximum -of MAX_TIMESTAMP_CACHE which is defined as 16 entries. Each entry is -defined by: - -struct timestamp_entry { - uint32_t entry_id; - uint64_t entry_stamp; -} __attribute__((packed)); - -entry_id holds the timestamp id corresponding to this entry and -entry_stamp holds the actual timestamp. - - -For timestamps stored in the cbmem area, a timestamp_table is allocated -with space for MAX_TIMESTAMPS equal to 30. Thus, the cbmem area holds -base_time, max_entries (which is 30), current number of entries and the -actual entries represented by timestamp_entry. - - -Function APIs -============= - -timestamp_init --------------- -This function initializes the timestamp cache and should be run as early -as possible. On platforms with SRAM, this might mean in bootblock, on -x86 with its CAR backed memory in romstage, this means romstage before -memory init. - -timestamp_add -------------- -This function accepts from user a timestamp id and time to record in the -timestamp table. It stores the entry in the appropriate table in cbmem -or _timestamp region or local stash. - - -timestamp_add_now ------------------ -This function calls timestamp_add with user-provided id and current time. - - -Use / Test Cases -================ - -The following cases have been considered while designing the timestamp -library. It is important to ensure that any changes made to this library satisfy -each of the following use cases: - -Case 1: Timestamp Region Exists (Fresh Boot / Resume) ------------------------------------------------------ - -In this case, the library needs to call timestamp_init as early as possible to -enable the timestamp cache. Once cbmem is available, the values will be -transferred automatically. - -All regions are automatically reset on initialization. - -Case 2: No timestamp region, fresh boot, cbmem_initialize called after timestamp_init -------------------------------------------------------------------------------------- - -timestamp_init will set up a local cache. cbmem must be initialized before that -cache vanishes - as happens when jumping to the next stage. - -Case 3: No timestamp region, fresh boot, cbmem_initialize called before timestamp_init --------------------------------------------------------------------------------------- - -This case is not supported right now, just don't call timestamp_init after -cbmem_initialize. (Patches to make this more robust are welcome.) - -Case 4: No timestamp region, resume, cbmem_initialize called after timestamp_init ---------------------------------------------------------------------------------- - -We always reset the cbmem region before using it, so pre-suspend timestamps -will be gone. - -Case 5: No timestamp region, resume, cbmem_initialize called before timestamp_init ----------------------------------------------------------------------------------- - -We always reset the cbmem region before using it, so pre-suspend timestamps -will be gone.