[coreboot-gerrit] Change in coreboot[master]: soc/intel/cannonlake: Disable USB2 PHY Power gating [WIP]

[Surendranath R Gurivireddy (Code Review)]

Hello Patrick Rudolph, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/36519

to look at the new patch set (#2).

Change subject: soc/intel/cannonlake: Disable USB2 PHY Power gating [WIP]
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soc/intel/cannonlake: Disable USB2 PHY Power gating [WIP]

Workaround for an issue seen when a specific charger is connected while in S0ix state

Signed-off-by: Surendranath Gurivireddy 
Change-Id: I95909c73de758fccc7f616a330c1e1f0667e8c25
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M src/soc/intel/cannonlake/fsp_params.c
1 file changed, 3 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/36519/2